Lines Matching +full:7 +full:- +full:pin

2 # SPDX-License-Identifier: Apache-2.0
7   The NXP S32 pin controller is a singleton node responsible for controlling
8   the pin function selection and pin properties. This node, labeled 'pinctrl' in
9   the SoC's devicetree, will define pin configurations in pin groups. Each group
10   within the pin configuration defines the pin configuration for a peripheral,
11   and each numbered subgroup in the pin group defines all the pins for that
20     #include <nxp/s32/S32Z27-BGA594-pinctrl.h>
26           output-enable;
30           input-enable;
35   The 'uart0_default' node contains the pin configurations for a particular state
40   'bias-pull-up' or 'slew-rate' that will be applied to all the pins defined in
41   'pinmux' array. To enable the input buffer use 'input-enable' and to enable the
42   output buffer use 'output-enable'.
44   To link the pin configurations with UART0 device, use pinctrl-N property in the
45   device node, where 'N' is the zero-based state index (0 is the default state).
49       pinctrl-0 = <&uart0_default>;
50       pinctrl-names = "default";
54   If only the required properties are supplied, the pin configuration register
56     - input and output buffers disabled
57     - internal pull not enabled
58     - open drain disabled
59     - slew rate 4 (see description in property below).
60     - termination resistor disabled (affect LVDS pads only).
61     - current reference control disabled (affect LVDS pads only).
62     - Rx current boost disabled  (affect LVDS pads only).
65   - Safe Mode is always kept as reset value (disabled).
66   - Receiver Select is always kept as reset value (enables the differential vref based receiver).
68 compatible: "nxp,s32ze-pinctrl"
72 child-binding:
73   description: NXP S32 pin controller pin group.
74   child-binding:
75     description: NXP S32 pin controller pin configuration node.
78       - name: pincfg-node.yaml
79         property-allowlist:
80           - bias-pull-down
81           - bias-pull-up
82           - drive-open-drain
83           - slew-rate
84           - input-enable
85           - output-enable
94           encode all the pin muxing information in a 32-bit value.
96       slew-rate:
97         enum: [0, 4, 5, 6, 7]
101           - For 3.3 V / 1.8 V FAST pads:
106             7: FMAX_3318 = 100 MHz (at 1.8 V), 83 MHz (at 3.3 V)
107           - For 1.8 V GPIO pads:
112             7: FMAX_18 = 50 MHz
113           - For 3.3 V GPIO pads:
118             7: FMAX_33 = 1 MHz
120       nxp,current-reference-control:
124           the associated pin. It is only applicable to LVDS pads and
127       nxp,termination-resistor:
131           the associated pin. It is only applicable to LVDS pads and
134       nxp,rx-current-boost: