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/Zephyr-latest/dts/bindings/clock/
Dnuvoton,npcx-pcc.yaml14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
35 120000000, 120 MHz
36 100000000, 100 MHz
37 96000000, 96 MHz
38 90000000, 90 MHz
39 80000000, 80 MHz
[all …]
Dnuvoton,npcm-pcc.yaml14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
19 apb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
20 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
21 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
38 100000000, 100 MHz
39 96000000, 96 MHz
[all …]
Dst,stm32u5-msi-clock.yaml22 - 0 # range 0 around 48 MHz
23 - 1 # range 1 around 24 MHz
24 - 2 # range 2 around 16 MHz
25 - 3 # range 3 around 12 MHz
26 - 4 # range 4 around 4 MHz (reset value)
27 - 5 # range 5 around 2 MHz
28 - 6 # range 6 around 1.33 MHz
29 - 7 # range 7 around 1 MHz
30 - 8 # range 8 around 3.072 MHz
31 - 9 # range 9 around 1.536 MHz
[all …]
Dst,stm32-msi-clock.yaml23 - 5 # range 5 around 2 MHz
24 - 6 # range 6 around 4 MHz (reset value)
25 - 7 # range 7 around 8 MHz
26 - 8 # range 8 around 16 MHz
27 - 9 # range 9 around 24 MHz
28 - 10 # range 10 around 32 MHz
29 - 11 # range 11 around 48 MHz
Dst,stm32l0-msi-clock.yaml17 default: 5
25 - 4 # range 4, around 1.048 MHz
26 - 5 # range 5, around 2.097 MHz (reset value)
27 - 6 # range 6, around 4.194 MHz
Dst,stm32f105-pll-clock.yaml19 The PLL output frequency must not exceed 72 MHz.
38 Note: For x6.5 multiplier value, please use "mul = <15>;"
41 - 5 # x5
46 - 15 # x6.5
58 Optional PLL output divisor to generate a 48MHz USB clock.
/Zephyr-latest/soc/nxp/imx/imx8m/m4_mini/
Dsoc.c61 .preDiv = 5U,
70 .preDiv = 5U,
98 /* Switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ in SOC_ClockInit()
101 /* Set root clock to 800MHZ/ 2= 400MHZ */ in SOC_ClockInit()
108 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
110 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
114 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
116 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
120 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
122 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
[all …]
/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,s32ze-pinctrl.yaml97 enum: [0, 4, 5, 6, 7]
102 0: FMAX_3318 = 208 MHz (at 1.8 V), 166 MHz (at 3.3 V)
103 4: FMAX_3318 = 166 MHz (at 1.8 V), 150 MHz (at 3.3 V)
104 5: FMAX_3318 = 150 MHz (at 1.8 V), 133 MHz (at 3.3 V)
105 6: FMAX_3318 = 133 MHz (at 1.8 V), 100 MHz (at 3.3 V)
106 7: FMAX_3318 = 100 MHz (at 1.8 V), 83 MHz (at 3.3 V)
108 0: FMAX_18 = 208 MHz
109 4: FMAX_18 = 150 MHz
110 5: FMAX_18 = 133 MHz
111 6: FMAX_18 = 100 MHz
[all …]
/Zephyr-latest/boards/nxp/mimxrt1024_evk/
Dmimxrt1024_evk-pinctrl.dtsi19 nxp,speed = "100-mhz";
29 nxp,speed = "50-mhz";
39 drive-strength = "r0-5";
43 nxp,speed = "200-mhz";
49 nxp,speed = "100-mhz";
57 drive-strength = "r0-5";
61 nxp,speed = "200-mhz";
65 drive-strength = "r0-5";
69 nxp,speed = "100-mhz";
73 drive-strength = "r0-5";
[all …]
/Zephyr-latest/boards/shields/st_b_lcd40_dsi1_mb1166/boards/
Dstm32h747i_disco_stm32h747xx_m7.overlay24 div-m = <5>;
28 div-r = <24>; /* 27.5 MHz */
37 * = 25 MHz / 5 * 2 * 100 / 2 / (1<<0) / 8 = 62.5 MHz
40 pll-idf = <5>;
/Zephyr-latest/soc/atmel/sam/sam4l/
Dsoc.h73 * Internal 80 MHz RC oscillator
74 * Internal 4-8-12 MHz RCFAST oscillator
75 * Internal 1 MHz RC oscillator
83 #define OSC_ID_RC1M 5
91 * 80 MHz RC oscillator
92 * 4-8-12 MHz RC oscillator
93 * 1 MHz RC oscillator
100 #define OSC_SRC_RCFAST 5
103 #define PM_CLOCK_MASK(bus, per) ((bus << 5) + per)
108 #define PM_CLK_GRP_CPU 5
[all …]
/Zephyr-latest/boards/nxp/mimxrt1020_evk/
Dmimxrt1020_evk-pinctrl.dtsi19 nxp,speed = "100-mhz";
30 nxp,speed = "50-mhz";
40 drive-strength = "r0-5";
44 nxp,speed = "200-mhz";
50 nxp,speed = "100-mhz";
58 drive-strength = "r0-5";
62 nxp,speed = "200-mhz";
66 drive-strength = "r0-5";
70 nxp,speed = "100-mhz";
74 drive-strength = "r0-5";
[all …]
/Zephyr-latest/soc/nxp/imx/imx8m/m7/
Dsoc.c64 .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
72 .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
80 .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 600MHZ */
88 * to 800Mhz when power up the SOC, meanwhile A core would enable SYSTEM PLL1, SYSTEM PLL2 in SOC_ClockInit()
104 /* Set root clock freq to 133M / 1= 133MHZ */ in SOC_ClockInit()
111 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
113 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
117 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
119 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
123 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
[all …]
/Zephyr-latest/drivers/spi/
Dspi_esp32_spim.h17 #define SPI_MASTER_FREQ_9M (APB_CLK_FREQ/9) /* 8.89MHz */
18 #define SPI_MASTER_FREQ_10M (APB_CLK_FREQ/8) /* 10MHz */
19 #define SPI_MASTER_FREQ_11M (APB_CLK_FREQ/7) /* 11.43MHz */
20 #define SPI_MASTER_FREQ_13M (APB_CLK_FREQ/6) /* 13.33MHz */
21 #define SPI_MASTER_FREQ_16M (APB_CLK_FREQ/5) /* 16MHz */
22 #define SPI_MASTER_FREQ_20M (APB_CLK_FREQ/4) /* 20MHz */
23 #define SPI_MASTER_FREQ_26M (APB_CLK_FREQ/3) /* 26.67MHz */
24 #define SPI_MASTER_FREQ_40M (APB_CLK_FREQ/2) /* 40MHz */
25 #define SPI_MASTER_FREQ_80M (APB_CLK_FREQ/1) /* 80MHz */
/Zephyr-latest/drivers/modem/
DKconfig.hl780079 bool "Band 1 (2000MHz)"
82 Enable Band 1 (2000MHz)
85 bool "Band 2 (1900MHz)"
88 Enable Band 2 (1900MHz)
91 bool "Band 3 (1800MHz)"
94 Enable Band 3 (1800MHz)
97 bool "Band 4 (1700MHz)"
100 Enable Band 4 (1700MHz)
103 bool "Band 5 (850MHz)"
106 Enable Band 5 (850MHz)
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dti,fdc2x1x.yaml46 The internal clock oscillates at around 43360 KHz (43.36 MHz)
48 Recommended external clock source frequency is 40000 KHz (40 MHz).
97 1 = 1MHz
98 4 = 3.3MHz
99 5 = 10MHz
100 7 = 33MHz
104 - 5
234 0.01MHz and 8.75MHz
235 2 = divide by 2. Choose for sensor frequencies between 5MHz
236 and 10MHz
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/ethernet/
Dxlnx_gem.h28 #define XLNX_GEM_MDC_DIVIDER_8 0 /* cpu_1x or IOU_SWITCH_CLK < 20 MHz */
29 #define XLNX_GEM_MDC_DIVIDER_16 1 /* cpu_1x or IOU_SWITCH_CLK 20 - 40 MHz */
30 #define XLNX_GEM_MDC_DIVIDER_32 2 /* cpu_1x or IOU_SWITCH_CLK 40 - 80 MHz */
31 #define XLNX_GEM_MDC_DIVIDER_48 3 /* cpu_1x or IOU_SWITCH_CLK 80 - 120 MHz */
32 #define XLNX_GEM_MDC_DIVIDER_64 4 /* cpu_1x or IOU_SWITCH_CLK 120 - 160 MHz */
33 #define XLNX_GEM_MDC_DIVIDER_96 5 /* cpu_1x or IOU_SWITCH_CLK 160 - 240 MHz */
34 #define XLNX_GEM_MDC_DIVIDER_128 6 /* cpu_1x or IOU_SWITCH_CLK 240 - 320 MHz */
35 #define XLNX_GEM_MDC_DIVIDER_224 7 /* cpu_1x or IOU_SWITCH_CLK 320 - 540 MHz */
/Zephyr-latest/soc/ite/ec/it8xxx2/
Dsoc.c55 pllfreq = MHZ(8); in chip_get_pll_freq()
58 pllfreq = MHZ(16); in chip_get_pll_freq()
61 pllfreq = MHZ(24); in chip_get_pll_freq()
64 pllfreq = MHZ(32); in chip_get_pll_freq()
67 pllfreq = MHZ(48); in chip_get_pll_freq()
69 case 5: in chip_get_pll_freq()
70 pllfreq = MHZ(64); in chip_get_pll_freq()
73 pllfreq = MHZ(72); in chip_get_pll_freq()
76 pllfreq = MHZ(96); in chip_get_pll_freq()
121 * PLL frequency setting = 4 (48MHz)
[all …]
/Zephyr-latest/samples/sensor/fdc2x1x/
DREADME.rst39 at pages 4-5.
63 ch0: 5.318888 MHz ch1: 5.150293 MHz
66 ch0: 5.318819 MHz ch1: 5.150307 MHz
69 ch0: 5.318822 MHz ch1: 5.150200 MHz
72 ch0: 5.318752 MHz ch1: 5.150265 MHz
83 ch0: 4.966171 MHz ch1: 4.946465 MHz ch2: 4.985879 MHz ch3: 4.907051 MHz
86 ch0: 4.966171 MHz ch1: 4.946465 MHz ch2: 4.985879 MHz ch3: 4.907051 MHz
89 ch0: 4.966171 MHz ch1: 4.946465 MHz ch2: 4.985879 MHz ch3: 4.907051 MHz
92 ch0: 4.966171 MHz ch1: 4.946465 MHz ch2: 4.985879 MHz ch3: 4.907051 MHz
/Zephyr-latest/boards/infineon/cy8cproto_063_ble/
Dcy8cproto_063_ble.dts19 uart-5 = &uart5;
103 /* CM4 core clock = 100MHz
104 * &fll clock-frequency / &clk_hf0 clock-div / &clk_fast clock-div = 100MHz / 1 / 1 = 100MHz
110 /* CM0+ core clock = 50MHz
111 * &fll clock-frequency / &clk_hf0 clock-div / &clk_slow clock-div = 100MHz / 1 / 2 = 50MHz
117 /* PERI core clock = 100MHz
118 * &fll clock-frequency / &clk_hf0 clock-div / &clk_peri clock-div = 100MHz / 1 / 1 = 100MHz
/Zephyr-latest/boards/nxp/mimxrt1062_fmurt6/
Dmimxrt1062_fmurt6-pinctrl.dtsi19 nxp,speed = "100-mhz";
28 nxp,speed = "50-mhz";
40 drive-strength = "r0-5";
43 nxp,speed = "200-mhz";
48 drive-strength = "r0-5";
50 nxp,speed = "200-mhz";
54 drive-strength = "r0-5";
58 nxp,speed = "50-mhz";
68 nxp,speed = "100-mhz";
78 nxp,speed = "100-mhz";
[all …]
/Zephyr-latest/tests/drivers/pinctrl/gd32/boards/
Dgd32f450i_eval.overlay36 pinmux = <GD32_PINMUX_AF('C', 5, AF5)>;
45 slew-rate = "max-speed-2mhz";
49 slew-rate = "max-speed-25mhz";
53 slew-rate = "max-speed-50mhz";
57 slew-rate = "max-speed-200mhz";
/Zephyr-latest/dts/bindings/timer/
Dambiq,stimer.yaml24 1 - HFRC_DIV16 : 3MHz from the HFRC clock divider.
28 5 - XTAL_DIV32 : 1024Hz from the crystal oscillator.
34 1 - HFRC_6MHZ : 6MHz from the HFRC clock divider.
38 5 - XTAL_1KHZ : 1024Hz from the crystal oscillator.
/Zephyr-latest/dts/bindings/can/
Dti,tcan4x5x.yaml18 bosch,mram-cfg = <0x0 15 15 5 5 0 10 10>;
39 TCAN4x5x oscillator clock frequency in Hz (20MHz or 40MHz).
/Zephyr-latest/boards/st/nucleo_l4r5zi/doc/
Dindex.rst20 - USB VBUS or external source(3.3V, 5V, 7 - 12V)
34 and 100 uA/MHz run mode)
37 execution from Flash memory, frequency up to 120 MHz, MPU, 150
38 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
41 - 4 to 48 MHz crystal oscillator
43 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
44 - Internal low-power 32 kHz RC ( |plusminus| 5%)
45 - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
47 - Internal 48 MHz with clock recovery
64 - 2 x 32-bit and 5 x 16-bit general purpose
[all …]

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