Lines Matching +full:5 +full:mhz
61 .preDiv = 5U,
70 .preDiv = 5U,
98 /* Switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ in SOC_ClockInit()
101 /* Set root clock to 800MHZ/ 2= 400MHZ */ in SOC_ClockInit()
108 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
110 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
114 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
116 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
120 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
122 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
126 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
128 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
135 /* Set ECSPI1 source to SYSTEM PLL1 800MHZ */ in SOC_ClockInit()
137 /* Set root clock to 800MHZ / 10 = 80MHZ */ in SOC_ClockInit()
138 CLOCK_SetRootDivider(kCLOCK_RootEcspi1, 2U, 5U); in SOC_ClockInit()
142 /* Set ECSPI2 source to SYSTEM PLL1 800MHZ */ in SOC_ClockInit()
144 /* Set root clock to 800MHZ / 10 = 80MHZ */ in SOC_ClockInit()
145 CLOCK_SetRootDivider(kCLOCK_RootEcspi2, 2U, 5U); in SOC_ClockInit()
149 /* Set ECSPI3 source to SYSTEM PLL1 800MHZ */ in SOC_ClockInit()
151 /* Set root clock to 800MHZ / 10 = 80MHZ */ in SOC_ClockInit()
152 CLOCK_SetRootDivider(kCLOCK_RootEcspi3, 2U, 5U); in SOC_ClockInit()