| /Zephyr-latest/drivers/pinctrl/ |
| D | pinctrl_b91.c | 4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/pinctrl/b91-pinctrl.h>
17 * gpio_en: PORT_A[0-7]
18 * gpio_en + 1*8: PORT_B[0-7]
19 * gpio_en + 2*8: PORT_C[0-7]
20 * gpio_en + 3*8: PORT_D[0-7]
21 * gpio_en + 4*8: PORT_E[0-7]
22 * gpio_en + 5*8: PORT_F[0-7]
24 #define reg_gpio_en(pin) (*(volatile uint8_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, gpio_en) + \ argument
25 ((pin >> 8) * 8)))
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| D | pinctrl_imx_scmi.c | 4 * SPDX-License-Identifier: Apache-2.0
10 static int scmi_pinctrl_configure_pin(const pinctrl_soc_pin_t *pin) in scmi_pinctrl_configure_pin() argument
18 settings.id = (pin->pinmux.mux_register - IOMUXC_MUXREG) / 4; in scmi_pinctrl_configure_pin()
20 settings.config[1] = IOMUXC_INPUT_ENABLE(pin->pin_ctrl_flags) in scmi_pinctrl_configure_pin()
21 ? (pin->pinmux.mux_mode | IOMUXC_SION(1)) in scmi_pinctrl_configure_pin()
22 : pin->pinmux.mux_mode; in scmi_pinctrl_configure_pin()
25 if (pin->pinmux.input_register) { in scmi_pinctrl_configure_pin()
27 settings.config[3] = (pin->pinmux.input_register - IOMUXC_DAISYREG) / 4; in scmi_pinctrl_configure_pin()
30 settings.config[4] = PIN_CONFIG_TYPE_DAISY_CFG; in scmi_pinctrl_configure_pin()
31 settings.config[5] = pin->pinmux.input_daisy; in scmi_pinctrl_configure_pin()
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| D | pinctrl_numicro.c | 4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/pinctrl/numicro-pinctrl.h>
15 #define MODE_PIN_SHIFT(pin) ((pin) * 2) argument
16 #define MODE_MASK(pin) (3 << MODE_PIN_SHIFT(pin)) argument
17 #define DINOFF_PIN_SHIFT(pin) ((pin) + 16) argument
18 #define DINOFF_MASK(pin) (1 << DINOFF_PIN_SHIFT(pin)) argument
19 #define PUSEL_PIN_SHIFT(pin) ((pin) * 2) argument
20 #define PUSEL_MASK(pin) (3 << PUSEL_PIN_SHIFT(pin)) argument
21 #define SLEWCTL_PIN_SHIFT(pin) ((pin) * 2) argument
22 #define SLEWCTL_MASK(pin) (3 << SLEWCTL_PIN_SHIFT(pin)) argument
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| /Zephyr-latest/drivers/pinctrl/renesas/rcar/ |
| D | pfc_rcar.c | 2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
43 /* POC Control Register can control IO voltage level that is supplied to the pin */
53 * 24/4 mA or 24/8 mA.
57 (size == 2 ? PFC_RCAR_DRIVE_MAX / 4 : PFC_RCAR_DRIVE_MAX / 8)
68 /* Set the pin either in gpio or peripheral */
70 uint16_t pin, bool peripheral) in pfc_rcar_set_gpsr() argument
74 uint8_t bank = pin / 32; in pfc_rcar_set_gpsr()
79 uint8_t bit = pin % 32; in pfc_rcar_set_gpsr()
95 uint16_t reg_offs = PFC_RCAR_IPSR + rcar_func->bank * sizeof(uint32_t); in pfc_rcar_set_ipsr()
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| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | adi,max32-pinctrl.yaml | 1 # Copyright (c) 2023-2024 Analog Devices, Inc.
2 # SPDX-License-Identifier: Apache-2.0
5 MAX32 Pin controller Node
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` are default pin configurations.
10 compatible: "adi,max32-pinctrl"
19 child-binding:
24 - name: pincfg-node.yaml
25 property-allowlist:
26 - bias-disable
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| D | nxp,s32ze-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The NXP S32 pin controller is a singleton node responsible for controlling
8 the pin function selection and pin properties. This node, labeled 'pinctrl' in
9 the SoC's devicetree, will define pin configurations in pin groups. Each group
10 within the pin configuration defines the pin configuration for a peripheral,
11 and each numbered subgroup in the pin group defines all the pins for that
20 #include <nxp/s32/S32Z27-BGA594-pinctrl.h>
26 output-enable;
30 input-enable;
35 The 'uart0_default' node contains the pin configurations for a particular state
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| D | raspberrypi,pico-pinctrl.yaml | 3 # SPDX-License-Identifier: Apache-2.0
6 The RPi Pico pin controller is a node responsible for controlling
7 pin function selection and pin properties, such as routing a UART0 Rx
8 to pin 1 and enabling the pullup resistor on that pin.
17 All device pin configurations should be placed in child nodes of the
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
39 /* enable input on pin 1 */
40 input-enable;
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| D | ti,cc13xx-cc26xx-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 Device pin configuration should be placed in the child nodes of this node.
8 Populate the 'pinmux' field with a pair consisting of a pin number and its IO
18 All device pin configurations should be placed in child nodes of the
22 supported standard pin properties:
24 - bias-disable: Disable pull-up/down.
25 - bias-pull-down: Enable pull-down resistor.
26 - bias-pull-up: Enable pull-up resistor.
27 - drive-open-drain: Output driver is open-drain.
28 - drive-open-drain: Output driver is open-source.
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| D | pinctrl-device.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 This file needs to be included by devices that need to specify a set of pin
6 controller states. The maximum number of supported states is 5 (pinctrl-0 ...
7 pinctrl-4) but it can be incremented if required.
9 The bindings file for each pin controller driver implementation should provide
10 more information on what is the expected pin configuration format.
13 pinctrl-0:
16 Pin configuration/s for the first state. Content is specific to the
17 selected pin controller driver implementation.
19 pinctrl-1:
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| D | ambiq,apollo4-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 The Ambiq Apollo4 pin controller is a node responsible for controlling
6 pin function selection and pin properties, such as routing a UART0 TX
7 to pin 60 and enabling the pullup resistor on that pin.
16 All device pin configurations should be placed in child nodes of the
19 /* You can put this in places like a board-pinctrl.dtsi file in
23 /* include pre-defined combinations for the SoC variant used by the board */
24 #include <dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h>
33 input-enable;
38 The 'uart0_default' child node encodes the pin configurations for a
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| D | microchip,xec-pinctrl.yaml | 3 # SPDX-License-Identifier: Apache-2.0
6 Microchip XEC Pin controller Node
7 Based on pincfg-node.yaml binding.
8 The MCHP XEC pin controller is a singleton node responsible for controlling
9 pin function selection and pin properties. For example, you can use this
10 node to select peripheral pin functions.
19 All device pin configurations should be placed in child nodes of the
22 A group can also specify shared pin properties common to all the specified
23 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
24 supported standard pin properties:
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| D | microchip,mec5-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 Microchip XEC Pin controller Node
6 Based on pincfg-node.yaml binding.
7 The MCHP XEC pin controller is a singleton node responsible for controlling
8 pin function selection and pin properties. For example, you can use this
9 node to select peripheral pin functions.
18 All device pin configurations should be placed in child nodes of the
21 A group can also specify shared pin properties common to all the specified
22 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
23 supported standard pin properties:
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| D | nordic,nrf-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 The nRF pin controller is a singleton node responsible for controlling
6 pin function selection and pin properties. For example, you can use this
7 node to route UART0 RX to pin P0.1 and enable the pull-up resistor on the
8 pin.
17 All device pin configurations should be placed in child nodes of the
20 /* You can put this in places like a board-pinctrl.dtsi file in
33 /* configure P0.3 as UART_RX and P0.4 as UART_CTS */
34 psels = <NRF_PSEL(UART_RX, 0, 3)>, <NRF_PSEL(UART_CTS, 0, 4)>;
35 /* both P0.3 and P0.4 are configured with pull-up */
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| /Zephyr-latest/drivers/pinctrl/renesas/rz/ |
| D | pinctrl_rzt2m.c | 4 * SPDX-License-Identifier: Apache-2.0
21 #define DRCTL(port, pin) (PORT_NSR + 0xa00 + (0x8 * port) + pin) argument
27 #define DRCTL_SCHMITT(val) ((val & 0x1) << 4)
32 #define PFC_FUNC_MASK(pin) (0xf << (pin * 4)) argument
34 static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin) in pinctrl_configure_pin() argument
36 uint8_t rselp = sys_read8(RSELP(pin->port)); in pinctrl_configure_pin()
37 uint32_t pfc = sys_read32(PFC(pin->port)) & ~(PFC_FUNC_MASK(pin->pin)); in pinctrl_configure_pin()
38 uint8_t pmc = sys_read8(PMC(pin->port)); in pinctrl_configure_pin()
40 /* Set proper bit in the RSELP register to use as non-safety domain. */ in pinctrl_configure_pin()
41 sys_write8(rselp | BIT(pin->pin), RSELP(pin->port)); in pinctrl_configure_pin()
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| /Zephyr-latest/dts/bindings/gpio/ |
| D | digilent,pmod.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 through 3 correspond to IO1 through IO4, and parent pins 4 through 7
9 correspond to IO5 through IO8, as depicted below for a 12-pin connector.
11 12-pin Pmod interface:
13 0 IO1 IO5 4
17 - GND GND -
18 - VDD VDD -
20 This binding can also be used with the 6-pin Pmod connector variant which
21 is a proper subset of the 12-pin connector. In that case parent pins 4
25 6-pin Pmod interface:
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| D | nxp,pca_series.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Base binding for PCA series I2C-based GPIO expander
6 include: [gpio-controller.yaml, i2c-device.yaml]
21 # (b) PCAL6534 has 34 GPIO pins in 4x 8-bit port and 1x
22 # 2-bit port. This driver only support 4x 8-bit port.
25 reset-gpios:
26 type: phandle-array
28 Reset GPIO pin (active-low)
29 Left blank if the device does not have reset pin
30 or the pin is not connected in your application.
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| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/ |
| D | pinctrl-rcar-common.h | 2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
13 * Each IPSR bank can hold 8 cellules of 4 bits coded function.
17 * @param func the 4 bits encoded alternate function.
20 * Function shift [ 4 : 8 ]
25 #define IPSR(bank, shift, func) (((bank) << 10U) | ((shift) << 4U) | (func))
27 /* Arbitrary number to encode non capable gpio pin */
31 * @brief Utility macro to encode a GPIO capable pin
34 * @param pin the pin within the GPIO bank (0..31)
36 #define RCAR_GP_PIN(bank, pin) (((bank) * 32U) + (pin)) argument
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_renesas_rz.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/gpio/renesas-rz-gpio.h>
13 #define GPIO_RZ_IOPORT_P_REG_BASE_GET (&R_GPIO->P_20)
14 #define GPIO_RZ_IOPORT_PM_REG_BASE_GET (&R_GPIO->PM_20)
16 #define GPIO_RZ_REG_OFFSET(port, pin) (port + (pin / 4)) argument
18 #define GPIO_RZ_P_VALUE_GET(value, pin) ((value >> pin) & 1U) argument
19 #define GPIO_RZ_PM_VALUE_GET(value, pin) ((value >> (pin * 2)) & 3U) argument
32 #define GPIO_RZ_TSSR_VAL(port, pin) (0x80 | (gpio_rz_int[port] + pin)) argument
33 #define GPIO_RZ_TSSR_OFFSET(irq) ((irq % 4) * 8)
44 static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23, 28, 33, 38, 43,
|
| /Zephyr-latest/dts/bindings/sdhc/ |
| D | espressif,esp32-sdhc-slot.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "espressif,esp32-sdhc-slot"
8 include: [sdhc.yaml, pinctrl-device.yaml]
14 pinctrl-0:
17 pinctrl-names:
20 bus-width:
23 - 1
24 - 4
25 default: 4
28 clk-pin:
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| /Zephyr-latest/include/zephyr/drivers/pinctrl/ |
| D | pinctrl_rcar_common.h | 4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rcar-common.h>
17 uint8_t bank:5; /* bank number 0 - 18 */
18 uint8_t shift:5; /* bit shift 0 - 28 */
19 uint8_t func:4; /* choice from 0x0 to 0xF */
22 /** Pull-up, pull-down, or bias disable is requested */
26 /** Select pull-up resistor if set pull-down otherwise */
28 /** Alternate function for the pin is requested */
30 /** Ignore IPSR settings for alternate function pin */
31 #define RCAR_PIN_FLAGS_FUNC_DUMMY BIT(4)
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| /Zephyr-latest/dts/bindings/sensor/ |
| D | st,iis328dq-common.yaml | 3 # SPDX-License-Identifier: Apache-2.0
5 include: sensor-device.yaml
8 int1-gpios:
9 type: phandle-array
11 INT_1 pin
13 This pin defaults to active high when produced by the sensor. The property value should ensure
16 int2-gpios:
17 type: phandle-array
19 INT_2 pin
21 This pin defaults to active high when produced by the sensor. The property value should ensure
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| D | nxp,fxls8974-common.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: FXLS8974 3-axis accelerometer sensor
6 include: sensor-device.yaml
9 reset-gpios:
10 type: phandle-array
12 RST pin
13 This pin defaults to active high when consumed by the sensor.
17 int1-gpios:
18 type: phandle-array
20 INT1 pin
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| /Zephyr-latest/drivers/i2s/ |
| D | Kconfig.sam_ssc | 4 # SPDX-License-Identifier: Apache-2.0
20 default 4
24 default 4
27 bool "RF pin enabled"
30 If enabled RF signal is connected to RF pin. It will be configured as
34 If disabled RF signal is disconnected from RF pin and connected
38 bool "RK pin enabled"
41 If enabled RK signal is connected to RK pin. It will be configured as
45 If disabled RK signal is disconnected from RK pin and connected
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| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | numicro-pinctrl.h | 4 * SPDX-License-Identifier: Apache-2.0
12 #define NUMICRO_PIN_SHIFT 4U
18 * @brief Pin configuration configuration bit field.
22 * - mfp [ 0 : 3 ]
23 * - pin [ 4 : 7 ]
24 * - port [ 8 : 11 ]
27 * @param pin Pin (0..15)
28 * @param mfp Multi-function value (0..15)
30 #define NUMICRO_PINMUX(port, pin, mfp) \ argument
31 (((((port) - 'A') & NUMICRO_PORT_MASK) << NUMICRO_PORT_SHIFT) | \
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| /Zephyr-latest/dts/bindings/net/wireless/ |
| D | nordic,nrf-radio.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 SoCs, which is available for use with Bluetooth, 802.15.4,
15 Front-End Module (FEM) support
16 ------------------------------
18 External front-end modules are range extenders used for boosting
27 nrf_radio_fem: my-fem {
34 - generic-fem-two-ctrl-pins
35 - nordic,nrf21540-fem
41 ---------------------------
44 The 'dfe-supported' property will be set when it is available.
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