Lines Matching +full:4 +full:- +full:pin
2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
43 /* POC Control Register can control IO voltage level that is supplied to the pin */
53 * 24/4 mA or 24/8 mA.
57 (size == 2 ? PFC_RCAR_DRIVE_MAX / 4 : PFC_RCAR_DRIVE_MAX / 8)
68 /* Set the pin either in gpio or peripheral */
70 uint16_t pin, bool peripheral) in pfc_rcar_set_gpsr() argument
74 uint8_t bank = pin / 32; in pfc_rcar_set_gpsr()
79 uint8_t bit = pin % 32; in pfc_rcar_set_gpsr()
95 uint16_t reg_offs = PFC_RCAR_IPSR + rcar_func->bank * sizeof(uint32_t); in pfc_rcar_set_ipsr()
98 val &= ~(0xFU << rcar_func->shift); in pfc_rcar_set_ipsr()
99 val |= (rcar_func->func << rcar_func->shift); in pfc_rcar_set_ipsr()
103 static uint32_t pfc_rcar_get_drive_reg(uint16_t pin, uint8_t *offset, in pfc_rcar_get_drive_reg() argument
108 while (drive_regs->reg != 0U) { in pfc_rcar_get_drive_reg()
109 for (size_t i = 0U; i < ARRAY_SIZE(drive_regs->fields); i++) { in pfc_rcar_get_drive_reg()
110 if (drive_regs->fields[i].pin == pin) { in pfc_rcar_get_drive_reg()
111 *offset = drive_regs->fields[i].offset; in pfc_rcar_get_drive_reg()
112 *size = drive_regs->fields[i].size; in pfc_rcar_get_drive_reg()
113 return drive_regs->reg; in pfc_rcar_get_drive_reg()
125 * some have 4 steps (2 bits size encoded).
127 static int pfc_rcar_set_drive_strength(uintptr_t pfc_base, uint16_t pin, in pfc_rcar_set_drive_strength() argument
133 reg = pfc_rcar_get_drive_reg(pin, &offset, &size); in pfc_rcar_set_drive_strength()
135 return -EINVAL; in pfc_rcar_set_drive_strength()
140 return -EINVAL; in pfc_rcar_set_drive_strength()
146 strength = (strength / step) - 1U; in pfc_rcar_set_drive_strength()
149 val &= ~GENMASK(offset + size - 1U, offset); in pfc_rcar_set_drive_strength()
157 static const struct pfc_bias_reg *pfc_rcar_get_bias_reg(uint16_t pin, in pfc_rcar_get_bias_reg() argument
162 /* Loop around all the registers to find the bit for a given pin */ in pfc_rcar_get_bias_reg()
163 while (bias_regs->puen && bias_regs->pud) { in pfc_rcar_get_bias_reg()
164 for (size_t i = 0U; i < ARRAY_SIZE(bias_regs->pins); i++) { in pfc_rcar_get_bias_reg()
165 if (bias_regs->pins[i] == pin) { in pfc_rcar_get_bias_reg()
176 int pfc_rcar_set_bias(uintptr_t pfc_base, uint16_t pin, uint16_t flags) in pfc_rcar_set_bias() argument
180 const struct pfc_bias_reg *bias_reg = pfc_rcar_get_bias_reg(pin, &bit); in pfc_rcar_set_bias()
183 return -EINVAL; in pfc_rcar_set_bias()
187 val = sys_read32(pfc_base + bias_reg->puen); in pfc_rcar_set_bias()
189 sys_write32(val & ~BIT(bit), pfc_base + bias_reg->puen); in pfc_rcar_set_bias()
192 sys_write32(val | BIT(bit), pfc_base + bias_reg->puen); in pfc_rcar_set_bias()
194 /* pull - up/down */ in pfc_rcar_set_bias()
195 val = sys_read32(pfc_base + bias_reg->pud); in pfc_rcar_set_bias()
197 sys_write32(val | BIT(bit), pfc_base + bias_reg->pud); in pfc_rcar_set_bias()
199 sys_write32(val & ~BIT(bit), pfc_base + bias_reg->pud); in pfc_rcar_set_bias()
214 [4] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
222 [12] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
223 [13] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
224 [14] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
225 [15] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
226 [16] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
227 [17] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
228 [18] = RCAR_GP_PIN(4, 6), /* SD2_DS */
229 [19] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
230 [20] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
231 [21] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
232 [22] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
233 [23] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
234 [24] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
235 [25] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
236 [26] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
237 [27] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
238 [28] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
239 [29] = RCAR_GP_PIN(4, 17), /* SD3_DS */
240 [30] = -1,
241 [31] = -1,
252 static const struct pfc_pocctrl_reg *pfc_rcar_get_pocctrl_reg(uint16_t pin, uint8_t *bit) in pfc_rcar_get_pocctrl_reg() argument
256 BUILD_ASSERT(ARRAY_SIZE(voltage_regs->pins) < UINT8_MAX); in pfc_rcar_get_pocctrl_reg()
258 /* Loop around all the registers to find the bit for a given pin */ in pfc_rcar_get_pocctrl_reg()
259 while (voltage_regs && voltage_regs->offset) { in pfc_rcar_get_pocctrl_reg()
262 for (i = 0U; i < ARRAY_SIZE(voltage_regs->pins); i++) { in pfc_rcar_get_pocctrl_reg()
263 if (voltage_regs->pins[i] == pin) { in pfc_rcar_get_pocctrl_reg()
274 static void pfc_rcar_set_voltage(uintptr_t pfc_base, uint16_t pin, uint16_t voltage) in pfc_rcar_set_voltage() argument
280 voltage_reg = pfc_rcar_get_pocctrl_reg(pin, &bit); in pfc_rcar_set_voltage()
285 val = sys_read32(pfc_base + voltage_reg->offset); in pfc_rcar_set_voltage()
304 pfc_rcar_write(pfc_base, voltage_reg->offset, val); in pfc_rcar_set_voltage()
308 int pinctrl_configure_pin(const pinctrl_soc_pin_t *pin) in pinctrl_configure_pin() argument
314 ret = pfc_rcar_get_reg_index(pin->pin, ®_index); in pinctrl_configure_pin()
320 return -EINVAL; in pinctrl_configure_pin()
325 /* Set pin as GPIO if capable */ in pinctrl_configure_pin()
326 if (RCAR_IS_GP_PIN(pin->pin)) { in pinctrl_configure_pin()
327 pfc_rcar_set_gpsr(pfc_base, pin->pin, false); in pinctrl_configure_pin()
328 } else if ((pin->flags & RCAR_PIN_FLAGS_FUNC_SET) == 0U) { in pinctrl_configure_pin()
329 /* A function must be set for non GPIO capable pin */ in pinctrl_configure_pin()
330 return -EINVAL; in pinctrl_configure_pin()
334 if (pin->voltage != PIN_VOLTAGE_NONE) { in pinctrl_configure_pin()
335 pfc_rcar_set_voltage(pfc_base, pin->pin, pin->voltage); in pinctrl_configure_pin()
339 /* Select function for pin */ in pinctrl_configure_pin()
340 if ((pin->flags & RCAR_PIN_FLAGS_FUNC_SET) != 0U) { in pinctrl_configure_pin()
342 if ((pin->flags & RCAR_PIN_FLAGS_FUNC_DUMMY) == 0U) { in pinctrl_configure_pin()
343 pfc_rcar_set_ipsr(pfc_base, &pin->func); in pinctrl_configure_pin()
346 if (RCAR_IS_GP_PIN(pin->pin)) { in pinctrl_configure_pin()
347 pfc_rcar_set_gpsr(pfc_base, pin->pin, true); in pinctrl_configure_pin()
350 if ((pin->flags & RCAR_PIN_FLAGS_PULL_SET) != 0U) { in pinctrl_configure_pin()
351 ret = pfc_rcar_set_bias(pfc_base, pin->pin, pin->flags); in pinctrl_configure_pin()
358 if (pin->drive_strength != 0U) { in pinctrl_configure_pin()
359 ret = pfc_rcar_set_drive_strength(pfc_base, pin->pin, in pinctrl_configure_pin()
360 pin->drive_strength); in pinctrl_configure_pin()
372 while (pin_cnt-- > 0U) { in pinctrl_configure_pins()