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/Zephyr-latest/samples/drivers/counter/maxim_ds3231/boards/
Dparticle_xenon.overlay4 * SPDX-License-Identifier: Apache-2.0
7 &i2c0 { /* SDA P0.26, SCL P0.27, ISW P1.1, 32K P1.2 */
12 isw-gpios = <&gpio1 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
13 32k-gpios = <&gpio1 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
/Zephyr-latest/tests/drivers/counter/maxim_ds3231_api/boards/
Dparticle_xenon.overlay4 * SPDX-License-Identifier: Apache-2.0
7 &i2c0 { /* SDA P0.26, SCL P0.27, ISW P1.1, 32K P1.2 */
12 isw-gpios = <&gpio1 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
13 32k-gpios = <&gpio1 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
/Zephyr-latest/dts/bindings/rtc/
Dmaxim,ds3231.yaml4 # SPDX-License-Identifier: Apache-2.0
11 include: i2c-device.yaml
17 32k-gpios:
18 type: phandle-array
21 32 KiHz open drain output
23 The DS3231 defaults to providing a 32 KiHz square wave on this
27 isw-gpios:
28 type: phandle-array
37 sub-second accuracy.
/Zephyr-latest/boards/shields/x_nucleo_eeprma2/
Dx_nucleo_eeprma2.overlay4 * SPDX-License-Identifier: Apache-2.0
12 eeprom-0 = &eeprom0_x_nucleo_eeprma2;
13 eeprom-1 = &eeprom4_x_nucleo_eeprma2;
19 clock-frequency = <I2C_BITRATE_FAST>;
22 /* M24C02-FMC6TG aka U1 (2 kbit eeprom in DFN8 package) */
27 address-width = <8>;
30 /* if solder-bridge closed: arduino A1 pin on CN8 can wp */
31 /* wp-gpios = <&arduino_header 1 GPIO_ACTIVE_LOW>; */
35 /* M24256-DFDW6TP aka U2 (256 kbit eeprom in TSSOP package) */
38 size = <DT_SIZE_K(32)>;
[all …]
/Zephyr-latest/boards/ezurio/mg100/
Dmg100.dts5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
10 #include "mg100-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
19 zephyr,shell-uart = &uart0;
20 zephyr,uart-mcumgr = &uart0;
21 zephyr,bt-mon-uart = &uart0;
24 zephyr,code-partition = &slot0_partition;
29 compatible = "gpio-leds";
31 gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
[all …]
/Zephyr-latest/boards/st/nucleo_f767zi/
Dnucleo_f767zi.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/f7/stm32f767zitx-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
21 model = "STMicroelectronics STM32F767ZI-NUCLEO board";
22 compatible = "st,stm32f767zi-nucleo";
26 zephyr,shell-uart = &usart3;
29 zephyr,code-partition = &slot0_partition;
35 compatible = "gpio-leds";
37 gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>;
[all …]
/Zephyr-latest/boards/ezurio/pinnacle_100_dvk/
Dpinnacle_100_dvk.dts5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
10 #include "pinnacle_100_dvk-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 compatible = "ezurio,pinnacle-100-dvk";
19 zephyr,shell-uart = &uart0;
20 zephyr,uart-mcumgr = &uart0;
21 zephyr,bt-mon-uart = &uart0;
24 zephyr,code-partition = &slot0_partition;
29 compatible = "gpio-leds";
[all …]
/Zephyr-latest/boards/ezurio/bt610/
Dbt610.dts5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
10 #include "bt610-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
19 zephyr,shell-uart = &uart0;
20 zephyr,uart-mcumgr = &uart0;
21 zephyr,bt-mon-uart = &uart0;
22 zephyr,bt-c2h-uart = &uart0;
25 zephyr,code-partition = &slot0_partition;
30 compatible = "gpio-leds";
[all …]
/Zephyr-latest/boards/ezurio/bl5340_dvk/
Dbl5340_dvk_nrf5340_cpuapp_common.dtsi2 * Copyright (c) 2019-2023 Nordic Semiconductor ASA
3 * Copyright (c) 2021-2023 Laird Connectivity
5 * SPDX-License-Identifier: Apache-2.0
7 #include "bl5340_dvk_nrf5340_cpuapp_common-pinctrl.dtsi"
8 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 zephyr,shell-uart = &uart0;
14 zephyr,uart-mcumgr = &uart0;
15 zephyr,bt-mon-uart = &uart0;
16 zephyr,bt-c2h-uart = &uart0;
18 zephyr,bt-hci = &bt_hci_ipc0;
[all …]
/Zephyr-latest/boards/seagate/legend/
Dlegend.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/f0/stm32f070cbtx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/led/led.h>
11 #include <zephyr/dt-bindings/led/seagate_legend_b1414.h>
12 #include <zephyr/dt-bindings/input/input-event-codes.h>
17 zephyr,shell-uart = &usart1;
24 led-strip = &led_strip_spi;
27 board_id: brd-id {
28 compatible = "gpio-keys";
[all …]
/Zephyr-latest/boards/st/nucleo_f429zi/
Dnucleo_f429zi.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/f4/stm32f429zitx-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 model = "STMicroelectronics STM32F429ZI-NUCLEO board";
15 compatible = "st,stm32f429zi-nucleo";
19 zephyr,shell-uart = &usart3;
23 zephyr,code-partition = &slot0_partition;
27 compatible = "gpio-leds";
29 gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>;
[all …]
/Zephyr-latest/boards/st/stm32l1_disco/doc/
Dindex.rst7 an integrated ST-LINK/V2 debugger and programmer. The boards have a
8 24-segment LCD and a touch slider, along with two user LEDs and a user button.
16 - STM32LDISCOVERY targets STM32L152RBT6, with 128K flash, 16K RAM, 4K EEPROM
17 - STM32L152CDISCOVERY targets STM32L152RCT6, with 256K flash, 32K RAM, 8K EEPROM
31 - On-board ST-LINK/V2 with selection mode switch to use the kit as a standalone
32 ST-LINK/V2 (with SWD connector for programming and debugging)
33 - Board power supply: through USB bus or from an external 5 V supply voltage
34 - External application power supply: 3 V and 5 V
35 - Four LEDs:
37 - LD1 (red) for 3.3 V power on
[all …]
/Zephyr-latest/boards/st/nucleo_f207zg/
Dnucleo_f207zg.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/f2/stm32f207z(c-e-f-g)tx-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 model = "STMicroelectronics STM32F207ZG-NUCLEO board";
15 compatible = "st,stm32f207zg-nucleo";
19 zephyr,shell-uart = &usart3;
25 compatible = "gpio-leds";
27 gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>;
31 gpios = <&gpiob 7 GPIO_ACTIVE_HIGH>;
[all …]
/Zephyr-latest/dts/arm/nxp/
Dnxp_lpc55S6x_common.dtsi5 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h>
14 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
15 #include <arm/armv8-m.dtsi>
16 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
24 zephyr,flash-controller = &iap;
[all …]
/Zephyr-latest/boards/st/stm32wb5mm_dk/
Dstm32wb5mm_dk.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/wb/stm32wb55vgyx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
11 #include <zephyr/dt-bindings/led/led.h>
12 #include <zephyr/dt-bindings/sensor/ism330dhcx.h>
16 compatible = "st,stm32wb5mm-dk";
20 zephyr,shell-uart = &usart1;
21 zephyr,bt-mon-uart = &lpuart1;
22 zephyr,bt-c2h-uart = &lpuart1;
[all …]
/Zephyr-latest/boards/st/nucleo_wb55rg/
Dnucleo_wb55rg.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/wb/stm32wb55rgvx-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 model = "STMicroelectronics STM32WB55RG-NUCLEO board";
15 compatible = "st,stm32wb55rg-nucleo";
19 zephyr,shell-uart = &usart1;
20 zephyr,bt-mon-uart = &lpuart1;
21 zephyr,bt-c2h-uart = &lpuart1;
24 zephyr,code-partition = &slot0_partition;
[all …]
/Zephyr-latest/boards/nxp/mr_canhubk3/
Dmr_canhubk3.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include <dt-bindings/pwm/pwm.h>
13 #include "mr_canhubk3-pinctrl.dtsi"
14 #include <zephyr/dt-bindings/sensor/qdec_nxp_s32.h>
17 model = "NXP MR-CANHUBK3";
25 zephyr,code-partition = &code_partition;
27 zephyr,shell-uart = &lpuart2;
[all …]
/Zephyr-latest/boards/seeed/lora_e5_mini/doc/
Dindex.rst6 LoRa-E5 mini is a compacted-sized development board suitable for the rapid
7 testing and building of small-sized LoRa device, exposing all capabilities of
8 Seeed Studio LoRa-E5 STM32WLE5JC module.
13 The boards' LoRa-E5 Module packages a STM32WLE5JC SOC, a 32MHz TCXO,
14 and a 32.768kHz crystal oscillator in a 28-pin SMD package.
15 This STM32WLEJC SOC is powered by ARM Cortex-M4 core and integrates Semtech
18 - LoRa-E5 STM32WLE5JC Module with STM32WLE5JC multiprotocol LPWAN single-core
19 32-bit microcontroller (Arm® Cortex®-M4 at 48 MHz) in 28-pin SMD package
22 - Ultra-low-power MCU
23 - RF transceiver (150 MHz to 960 MHz frequency range) supporting LoRa®,
[all …]
/Zephyr-latest/dts/arm/st/wl/
Dstm32wl.dtsi2 * Copyright (c) 2020-2024 STMicroelectronics
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/clock/stm32wl_clock.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/lora/sx126x.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/adc/adc.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
[all …]
/Zephyr-latest/dts/arm/st/wb/
Dstm32wb.dtsi6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32wb_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/adc/adc.h>
15 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
16 #include <zephyr/dt-bindings/dma/stm32_dma.h>
17 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
[all …]
/Zephyr-latest/boards/adi/max32672evkit/doc/
Dindex.rst6 of the MAX32672 microcontroller, which is a small, high-reliability, ultra-low power,
7 32-bit microcontroller. The MAX32672 is a secure and cost-effective solution
8 for motion/motor control, industrial sensors, and battery-powered medical devices and offers legacy
9 designs an easy, cost-optimal upgrade path from 8-bit or 16-bit microcontrollers.
16 - MAX32672 MCU:
18 - High-Efficiency Microcontroller for Low-Power High-Reliability Devices
20 - Arm Cortex-M4 Processor with FPU up to 100MHz
21 - 1MB Dual-Bank Flash with Error Correction
22 - 200KB SRAM (160KB with ECC Enabled), Optionally Preserved in Lowest Power Modes
23 - EEPROM Emulation on Flash
[all …]
/Zephyr-latest/boards/seeed/lora_e5_dev_board/doc/
Dlora_e5_dev_board.rst6 The LoRa-E5 Dev Board is a compact board for the evaluation of the
7 Seeed Studio LoRa-E5 STM32WLE5JC module.
8 The LoRa-E5-HF STM32WLE5JC Module supports multiple LPWAN protocols on the
10 All GPIOs of the LoRa-E5 Module are laid out supporting
11 various data protocols and interfaces including RS-485 and Grove.
16 The boards LoRa-E5 Module packages a STM32WLE5JC SOC, a 32MHz TCXO,
17 and a 32.768kHz crystal oscillator in a 28-pin SMD package.
18 This STM32WLEJC SOC is powered by ARM Cortex-M4 core and integrates Semtech
21 - LoRa-E5 STM32WLE5JC Module with STM32WLE5JC multiprotocol LPWAN single-core
22 32-bit microcontroller (Arm® Cortex®-M4 at 48 MHz) in 28-pin SMD package
[all …]
/Zephyr-latest/dts/arm/st/u5/
Dstm32u5.dtsi7 * SPDX-License-Identifier: Apache-2.0
11 #include <arm/armv8-m.dtsi>
12 #include <zephyr/dt-bindings/adc/adc.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/clock/stm32u5_clock.h>
15 #include <zephyr/dt-bindings/gpio/gpio.h>
16 #include <zephyr/dt-bindings/i2c/i2c.h>
17 #include <zephyr/dt-bindings/flash_controller/ospi.h>
18 #include <zephyr/dt-bindings/reset/stm32u5_reset.h>
19 #include <zephyr/dt-bindings/dma/stm32_dma.h>
[all …]
/Zephyr-latest/doc/releases/
Drelease-notes-3.5.rst38 * CVE-2023-3725 `Zephyr project bug tracker GHSA-2g3m-p6c7-8rr3
39 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-2g3m-p6c7-8rr3>`_
41 * CVE-2023-4257 `Zephyr project bug tracker GHSA-853q-q69w-gf5j
42 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-853q-q69w-gf5j>`_
44 * CVE-2023-4258 `Zephyr project bug tracker GHSA-m34c-cp63-rwh7
45 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-m34c-cp63-rwh7>`_
47 * CVE-2023-4259 `Zephyr project bug tracker GHSA-gghm-c696-f4j4
48 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-gghm-c696-f4j4>`_
50 * CVE-2023-4260 `Zephyr project bug tracker GHSA-gj27-862r-55wh
51 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-gj27-862r-55wh>`_
[all …]
/Zephyr-latest/drivers/flash/
Dspi_nor.c2 * Copyright (c) 2018 Savoir-Faire Linux.
8 * SPDX-License-Identifier: Apache-2.0
36 * * Some devices support a Deep Power-Down mode which reduces current
41 * * PM_DEVICE_STATE_SUSPENDED corresponds to deep-power-down mode;
63 #define DEV_CFG(_dev_) ((const struct spi_nor_config * const) (_dev_)->config)
66 /* MXICY Low-power/high perf mode is second bit in configuration register 2 */
72 /* Build-time data associated with the device. */
92 /* Expected JEDEC ID, from jedec-id property */
96 /* Optional support for entering 32-bit address mode. */
101 /* Length of BFP structure, in 32-bit words. */
[all …]

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