1/*
2 * Copyright (c) 2019-2023 Nordic Semiconductor ASA
3 * Copyright (c) 2021-2023 Laird Connectivity
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7#include "bl5340_dvk_nrf5340_cpuapp_common-pinctrl.dtsi"
8#include <zephyr/dt-bindings/input/input-event-codes.h>
9
10/ {
11	chosen {
12		zephyr,console = &uart0;
13		zephyr,shell-uart = &uart0;
14		zephyr,uart-mcumgr = &uart0;
15		zephyr,bt-mon-uart = &uart0;
16		zephyr,bt-c2h-uart = &uart0;
17		zephyr,display = &ili9340;
18		zephyr,bt-hci = &bt_hci_ipc0;
19		zephyr,touch = &ft5336;
20	};
21
22	/* Main LEDs and buttons are on an I2C TCA9538 GPIO port expander */
23	/* Note TCA9538 does not have configurable internal pull ups/ downs */
24	buttons {
25		compatible = "gpio-keys";
26		boot_button0: boot_button {
27			gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
28			label = "Bootloader button (S4)";
29			zephyr,code = <INPUT_KEY_0>;
30		};
31
32		button1: button_1 {
33			gpios = <&gpio_exp0 0 GPIO_ACTIVE_LOW>;
34			label = "Push button switch 1 (S1)";
35			zephyr,code = <INPUT_KEY_1>;
36		};
37
38		button2: button_2 {
39			gpios = <&gpio_exp0 1 GPIO_ACTIVE_LOW>;
40			label = "Push button switch 2 (S2)";
41			zephyr,code = <INPUT_KEY_2>;
42		};
43
44		button3: button_3 {
45			gpios = <&gpio_exp0 2 GPIO_ACTIVE_LOW>;
46			label = "Push button switch 3 (S9)";
47			zephyr,code = <INPUT_KEY_3>;
48		};
49
50		button4: button_4 {
51			gpios = <&gpio_exp0 3 GPIO_ACTIVE_LOW>;
52			label = "Push button switch 4 (S10)";
53			zephyr,code = <INPUT_KEY_4>;
54		};
55	};
56
57	leds {
58		compatible = "gpio-leds";
59		led1: led_1 {
60			gpios = <&gpio_exp0 4 GPIO_ACTIVE_LOW>;
61			label = "Blue LED 1";
62		};
63		led2: led_2 {
64			gpios = <&gpio_exp0 5 GPIO_ACTIVE_LOW>;
65			label = "Blue LED 2";
66		};
67		led3: led_3 {
68			gpios = <&gpio_exp0 6 GPIO_ACTIVE_LOW>;
69			label = "Blue LED 3";
70		};
71		led4: led_4 {
72			gpios = <&gpio_exp0 7 GPIO_ACTIVE_LOW>;
73			label = "Blue LED 4";
74		};
75	};
76
77	lvgl_pointer {
78		compatible = "zephyr,lvgl-pointer-input";
79		input = <&ft5336>;
80		swap-xy;
81		invert-x;
82		invert-y;
83	};
84
85	gpio_fwd: nrf-gpio-forwarder {
86		compatible = "nordic,nrf-gpio-forwarder";
87		status = "okay";
88		uart {
89			gpios = <&gpio1 8 0>, <&gpio1 10 0>, <&gpio1 7 0>, <&gpio1 9 0>;
90		};
91	};
92
93	/* These aliases are provided for compatibility with samples */
94	aliases {
95		led0 = &led1;
96		led1 = &led2;
97		led2 = &led3;
98		led3 = &led4;
99		sw0 = &button1;
100		sw1 = &button2;
101		sw2 = &button3;
102		sw3 = &button4;
103		mcuboot-button0 = &button1;
104		mcuboot-led0 = &led1;
105		sdhc0 = &sdhc0;
106		watchdog0 = &wdt0;
107		accel0 = &lis3dh;
108		bbram0 = &extrtc0;
109	};
110
111	mipi_dbi {
112		compatible = "zephyr,mipi-dbi-spi";
113		reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
114		dc-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
115		spi-dev = <&spi4>;
116		write-only;
117		#address-cells = <1>;
118		#size-cells = <0>;
119
120		ili9340: ili9340@0 {
121			compatible = "ilitek,ili9340";
122			reg = <0>;
123			mipi-max-frequency = <32000000>;
124			rotation = <270>;
125			width = <320>;
126			height = <240>;
127		};
128	};
129};
130
131&vregmain {
132	regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
133};
134
135&vregradio {
136	regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
137};
138
139&vregh {
140	status = "okay";
141};
142
143&lfxo {
144	load-capacitors = "internal";
145	load-capacitance-picofarad = <7>;
146};
147
148&hfxo {
149	load-capacitors = "internal";
150	load-capacitance-femtofarad = <13500>;
151};
152
153&adc {
154	status = "okay";
155};
156
157&gpiote {
158	status = "okay";
159};
160
161&gpio0 {
162	status = "okay";
163};
164
165&gpio1 {
166	status = "okay";
167};
168
169&i2c1 {
170	compatible = "nordic,nrf-twim";
171	status = "okay";
172
173	pinctrl-0 = <&i2c1_default>;
174	pinctrl-1 = <&i2c1_sleep>;
175	pinctrl-names = "default", "sleep";
176	at24c256@50 {
177		compatible = "atmel,at24c256", "atmel,at24";
178		reg = <0x50>;
179		size = <32768>;
180		pagesize = <64>;
181		address-width = <16>;
182		timeout = <10>;
183	};
184
185	lis3dh: lis3dh@18 {
186		compatible = "st,lis2dh";
187		reg = <0x18>;
188		irq-gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>, <&gpio0 24 GPIO_ACTIVE_HIGH>;
189	};
190
191	ft5336: ft5336@38 {
192		compatible = "focaltech,ft5336";
193		reg = <0x38>;
194		int-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
195	};
196
197	bme680@76 {
198		compatible = "bosch,bme680";
199		reg = <0x76>;
200	};
201
202	dac0: mcp4725@60 {
203		compatible = "microchip,mcp4725";
204		reg = <0x60>;
205		#io-channel-cells = <1>;
206	};
207
208	extrtc0: mcp7940n@6f {
209		compatible = "microchip,mcp7940n";
210		reg = <0x6f>;
211		status = "okay";
212	};
213
214	gpio_exp0: tca9538@70 {
215		compatible = "ti,tca9538";
216		reg = <0x70>;
217		gpio-controller;
218		#gpio-cells = <2>;
219		ngpios = <8>;
220		nint-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
221	};
222};
223
224&spi2 {
225	compatible = "nordic,nrf-spim";
226	status = "okay";
227	cs-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
228
229	pinctrl-0 = <&spi2_default>;
230	pinctrl-1 = <&spi2_sleep>;
231	pinctrl-names = "default", "sleep";
232	enc424j600@0 {
233		compatible = "microchip,enc424j600";
234		reg = <0>;
235		spi-max-frequency = <8000000>;
236		int-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
237	};
238};
239
240&spi3 {
241	compatible = "nordic,nrf-spim";
242	status = "okay";
243	cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
244
245	pinctrl-0 = <&spi3_default>;
246	pinctrl-1 = <&spi3_sleep>;
247	pinctrl-names = "default", "sleep";
248	sdhc0: sdhc@0 {
249		reg = <0>;
250		compatible = "zephyr,sdhc-spi-slot";
251		status = "okay";
252		spi-max-frequency = <8000000>;
253		mmc {
254			compatible = "zephyr,sdmmc-disk";
255			disk-name = "SD";
256			status = "okay";
257		};
258	};
259};
260
261&spi4 {
262	compatible = "nordic,nrf-spim";
263	status = "okay";
264	cs-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
265
266	pinctrl-0 = <&spi4_default>;
267	pinctrl-1 = <&spi4_sleep>;
268	pinctrl-names = "default", "sleep";
269};
270
271&uart0 {
272	status = "okay";
273	current-speed = <115200>;
274	pinctrl-0 = <&uart0_default>;
275	pinctrl-1 = <&uart0_sleep>;
276	pinctrl-names = "default", "sleep";
277};
278
279&uart1 {
280	current-speed = <115200>;
281	pinctrl-0 = <&uart1_default>;
282	pinctrl-1 = <&uart1_sleep>;
283	pinctrl-names = "default", "sleep";
284};
285
286&pwm0 {
287	status = "okay";
288	pinctrl-0 = <&pwm0_default>;
289	pinctrl-1 = <&pwm0_sleep>;
290	pinctrl-names = "default", "sleep";
291};
292
293&qspi {
294	status = "okay";
295	pinctrl-0 = <&qspi_default>;
296	pinctrl-1 = <&qspi_sleep>;
297	pinctrl-names = "default", "sleep";
298	mx25r64: mx25r6435f@0 {
299		compatible = "nordic,qspi-nor";
300		reg = <0>;
301		/* MX25R64 supports only pp and pp4io */
302		writeoc = "pp4io";
303		/* MX25R64 supports all readoc options */
304		readoc = "read4io";
305		sck-frequency = <8000000>;
306		jedec-id = [c2 28 17];
307		sfdp-bfp = [
308			e5 20 f1 ff  ff ff ff 03  44 eb 08 6b  08 3b 04 bb
309			ee ff ff ff  ff ff 00 ff  ff ff 00 ff  0c 20 0f 52
310			10 d8 00 ff  23 72 f5 00  82 ed 04 cc  44 83 68 44
311			30 b0 30 b0  f7 c4 d5 5c  00 be 29 ff  f0 d0 ff ff
312		];
313		size = <67108864>;
314		has-dpd;
315		t-enter-dpd = <10000>;
316		t-exit-dpd = <35000>;
317	};
318};
319
320&flash0 {
321	partitions {
322		compatible = "fixed-partitions";
323		#address-cells = <1>;
324		#size-cells = <1>;
325
326		/* 64K */
327		boot_partition: partition@0 {
328			label = "mcuboot";
329			reg = <0x00000000 0x00010000>;
330		};
331		/* 640K */
332		slot0_partition: partition@10000 {
333			label = "image-0";
334		};
335		/* 256K */
336		slot0_ns_partition: partition@b0000 {
337			label = "image-0-nonsecure";
338		};
339
340		/*
341		 * The flash starting at 0x000f8000 and ending at
342		 * 0x000fffff is reserved for use by the application.
343		 */
344
345		/*
346		 * Storage partition will be used by FCB/NVS
347		 * if enabled. 32K
348		 */
349		storage_partition: partition@f8000 {
350			label = "storage";
351			reg = <0x000f8000 0x00008000>;
352		};
353	};
354};
355
356&mx25r64 {
357	partitions {
358		compatible = "fixed-partitions";
359		#address-cells = <1>;
360		#size-cells = <1>;
361
362		/* 640K */
363		slot1_partition: partition@0 {
364			label = "image-1";
365		};
366		/* 256K */
367		slot1_ns_partition: partition@A0000 {
368			label = "image-1-nonsecure";
369		};
370		/* 128K */
371		scratch_partition: partition@e0000 {
372			label = "image-scratch";
373			reg = <0x000e0000 0x00020000>;
374		};
375		/* 7MB */
376		lfs_partition: partition@100000 {
377			label = "lfs_storage";
378			reg = <0x00100000 0x00700000>;
379		};
380	};
381};
382
383/ {
384	reserved-memory {
385		#address-cells = <1>;
386		#size-cells = <1>;
387		ranges;
388
389		sram0_image: image@20000000 {
390			/* Zephyr image(s) memory */
391		};
392
393		sram0_s: image_s@20000000 {
394			/* Secure image memory */
395		};
396
397		sram0_ns: image_ns@20040000 {
398			/* Non-Secure image memory */
399		};
400	};
401};
402
403/* Include partition configuration file */
404#include "bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi"
405