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/Zephyr-latest/drivers/i2c/
Di2c_dw_registers.h1 /* i2c_dw_registers.h - array access for I2C Design Ware registers */
6 * SPDX-License-Identifier: Apache-2.0
33 #define IC_DATA_CMD_CMD BIT(8)
34 #define IC_DATA_CMD_STOP BIT(9)
35 #define IC_DATA_CMD_RESTART BIT(10)
38 #define DW_INTR_STAT_RX_UNDER BIT(0)
39 #define DW_INTR_STAT_RX_OVER BIT(1)
40 #define DW_INTR_STAT_RX_FULL BIT(2)
41 #define DW_INTR_STAT_TX_OVER BIT(3)
42 #define DW_INTR_STAT_TX_EMPTY BIT(4)
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/Zephyr-latest/include/zephyr/bluetooth/
Dbyteorder.h8 * SPDX-License-Identifier: Apache-2.0
26 /** @brief Encode 16-bit value into array values in little-endian format.
28 * Helper macro to encode 16-bit values into comma separated values.
32 * @param _v 16-bit integer in host endianness.
34 * @return The comma separated values for the 16-bit value.
40 /** @brief Encode 24-bit value into array values in little-endian format.
42 * Helper macro to encode 24-bit values into comma separated values.
46 * @param _v 24-bit integer in host endianness.
48 * @return The comma separated values for the 24-bit value.
54 /** @brief Encode 32-bit value into array values in little-endian format.
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/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_vbat.h4 * SPDX-License-Identifier: Apache-2.0
16 /* Offset 0x00 Power-Fail and Reset Status */
26 #define MCHP_VBATR_PFRS_SYS_RST BIT(2)
27 #define MCHP_VBATR_PFRS_JTAG BIT(3)
28 #define MCHP_VBATR_PFRS_RESETI BIT(4)
29 #define MCHP_VBATR_PFRS_WDT BIT(5)
30 #define MCHP_VBATR_PFRS_SYSRESETREQ BIT(6)
31 #define MCHP_VBATR_PFRS_VBAT_RST BIT(7)
33 /* Offset 0x08 32K Clock Source register */
44 /* Enable and start internal 32KHz Silicon Oscillator */
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Dmec172x_pcr.h4 * SPDX-License-Identifier: Apache-2.0
53 * CLK_REQ bits are read-only. The peripheral sets its CLK_REQ if it requires
56 * SLP_EN bit = 1 instructs HW to gate off clock tree to peripheral only if
57 * peripherals PCR CLK_REQ bit is 0.
58 * RST_EN bit = 1 will reset the peripheral at any time. The RST_EN registers
67 * SLEEP_ALL bit = 1.
68 * Execute Cortex-M4 WFI sequence. DSB(), ISB(), WFI(), NOP()
69 * Cortex-M4 will assert sleep signal to PCR block.
76 * Write bit patterns to one or more of PCR RST_EN[0, 4] registers
84 #define MCHP_PCR_SLP(bitpos) BIT(bitpos)
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/Zephyr-latest/lib/hash/
DKconfig.hash_func3 # SPDX-License-Identifier: Apache-2.0
21 prompt "Default system-wide 32-bit hash function"
24 The default system-wide 32-bit hash function is sys_hash32().
27 bool "Default 32-bit hash is djb2"
31 bool "Default 32-bit hash is Murmur3"
35 bool "Default 32-bit hash is the identity"
/Zephyr-latest/include/zephyr/sys/
Dbyteorder.h6 * Copyright (c) 2015-2016, Intel Corporation.
8 * SPDX-License-Identifier: Apache-2.0
27 #define BSWAP_40(x) ((uint64_t) ((((x) >> 32) & 0xff) | \
31 (((x) & 0xff) << 32)))
48 * @brief Convert 16-bit integer from little-endian to host endianness.
50 * @param val 16-bit integer in little-endian format.
52 * @return 16-bit integer in host endianness.
56 * @brief Convert 16-bit integer from host endianness to little-endian.
58 * @param val 16-bit integer in host endianness.
60 * @return 16-bit integer in little-endian format.
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Dsys_io.h6 * SPDX-License-Identifier: Apache-2.0
69 * @brief Output 32 bits to an I/O port
71 * This function writes 32 bits to the given port.
73 * @param data the 32 bits to write
74 * @param port the port address where to write the 32 bits
79 * @brief Input 32 bits from an I/O port
81 * This function reads 32 bits from the port.
83 * @param port the port address from where to read the 32 bits
85 * @return the 32 bits read
89 * @fn static inline void sys_io_set_bit(io_port_t port, unsigned int bit)
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Dtime_units.h4 * SPDX-License-Identifier: Apache-2.0
26 /** @brief System-wide macro to denote "forever" in milliseconds
33 #define SYS_FOREVER_MS (-1)
35 /** @brief System-wide macro to denote "forever" in microseconds
39 #define SYS_FOREVER_US (-1)
41 /** @brief System-wide macro to convert milliseconds to kernel timeouts
99 * reduces to 32 bit only if a ratio conversion is available and the
100 * result is 32 bits.
103 * appropriately in a user-facing API. The boolean arguments are:
105 * const_hz - The hz arguments are known to be compile-time
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/Zephyr-latest/drivers/misc/timeaware_gpio/
Dtimeaware_gpio_intel.c4 * SPDX-License-Identifier: Apache-2.0
18 #define ART_L 0x00 /* ART lower 32 bit reg */
19 #define ART_H 0x04 /* ART higher 32 bit reg */
21 #define COMPV31_0 0x20 /* Comparator lower 32 bit reg */
22 #define COMPV63_32 0x24 /* Comparator higher 32 bit reg */
23 #define PIV31_0 0x28 /* Periodic Interval lower 32 bit reg */
24 #define PIV63_32 0x2c /* Periodic Interval higher 32 bit reg */
25 #define TCV31_0 0x30 /* Time Capture lower 32 bit reg */
26 #define TCV63_32 0x34 /* Time Capture higher 32 bit reg */
27 #define ECCV31_0 0x38 /* Event Counter Capture lower 32 bit reg */
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/Zephyr-latest/dts/bindings/sensor/
Dbosch,bmp388.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: sensor-device.yaml
9 int-gpios:
10 type: phandle-array
16 200 - 200 - 5ms (default; chip reset value)
17 100 - 100 - 10ms
18 50 - 50 - 20ms
19 25 - 25 - 40ms
20 12.5 - 25/2 - 80ms
21 6.25 - 25/4 - 160ms
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Dbosch,bmp390.yaml3 # SPDX-License-Identifier: Apache-2.0
7 include: sensor-device.yaml
10 int-gpios:
11 type: phandle-array
17 200 - 200 - 5ms (default; chip reset value)
18 100 - 100 - 10ms
19 50 - 50 - 20ms
20 25 - 25 - 40ms
21 12.5 - 25/2 - 80ms
22 6.25 - 25/4 - 160ms
[all …]
Dti,ina219.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [sensor-device.yaml, i2c-device.yaml]
11 lsb-microamp:
17 example: 100 -> ~3A
18 shunt-milliohm:
29 1 = 32 V FSR
31 The default of 32V is the power-on reset value of the device.
35 - 0
36 - 1
42 0 = 1 -> ±40 mV
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/Zephyr-latest/soc/atmel/sam/common/
Dsoc_pmc.c3 * SPDX-License-Identifier: Apache-2.0
23 if (id < 32) { in soc_pmc_peripheral_enable()
24 PMC->PMC_PCER0 = BIT(id); in soc_pmc_peripheral_enable()
25 #if ID_PERIPH_COUNT > 32 in soc_pmc_peripheral_enable()
27 PMC->PMC_PCER1 = BIT(id & 0x1F); in soc_pmc_peripheral_enable()
40 if (id < 32) { in soc_pmc_peripheral_disable()
41 PMC->PMC_PCDR0 = BIT(id); in soc_pmc_peripheral_disable()
42 #if ID_PERIPH_COUNT > 32 in soc_pmc_peripheral_disable()
44 PMC->PMC_PCDR1 = BIT(id & 0x1F); in soc_pmc_peripheral_disable()
57 if (id < 32) { in soc_pmc_peripheral_is_enabled()
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/Zephyr-latest/include/zephyr/arch/arc/asm-compat/
Dassembler.h1 /* SPDX-License-Identifier: Apache-2.0 */
7 * Top level include file providing ISA pseudo-mnemonics for use in assembler
10 * - Helps code reuse across ARC64/ARC32/ARCv2
11 * e.g. "LDR" maps to 'LD' on 32-bit ISA, 'LDL' on 64-bit ARCv2/ARC64
13 * - Provides emulation with multiple instructions if the case be
16 * - Looks more complex than it really is: mainly because Kconfig defines
34 #include "asm-macro-64-bit-mwdt.h"
36 #include "asm-macro-64-bit-gnu.h"
45 #include "asm-macro-32-bit-mwdt.h"
47 #include "asm-macro-32-bit-gnu.h"
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/Zephyr-latest/drivers/clock_control/
Dclock_control_mchp_xec.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
30 * 32KHz period counter minimum for pass/fail: 16-bit
31 * 32KHz period counter maximum for pass/fail: 16-bit
32 * 32KHz duty cycle variation max for pass/fail: 16-bit
33 * 32KHz valid count minimum: 8-bit
37 * One 32KHz clock pulse = 1464.84 48 MHz counts.
47 #define CLK32K_FLAG_CRYSTAL_SE BIT(0)
48 #define CLK32K_FLAG_PIN_FB_CRYSTAL BIT(1)
99 uint32_t RSVD4[(0x00c0 - 0x0094) / 4];
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/Zephyr-latest/drivers/edac/
Dibecc.h4 * SPDX-License-Identifier: Apache-2.0
35 #define NMI_STS_SRC_SERR BIT(7)
43 #define NMI_STS_SERR_EN BIT(2)
48 * In-Band Error Correction Code (IBECC) protects data at a cache line
51 * - CMI (Converged Memory Interface) Address
52 * - Syndrome
53 * - Error Type (Correctable, Uncorrectable)
60 /* Top of Upper Usable DRAM, offset 0xa8, 64 bit */
64 /* Top of Low Usable DRAM, offset 0xbc, 32 bit */
68 /* Total amount of physical memory, offset 0xa0, 64 bit */
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/Zephyr-latest/include/zephyr/dt-bindings/reset/
Dstm32-common.h4 * SPDX-License-Identifier: Apache-2.0
11 * Pack RCC register offset and bit in one 32-bit value.
13 * 5 LSBs are used to keep bit number in 32-bit RCC register.
18 * @param bit Reset bit
20 #define STM32_RESET(bus, bit) (((STM32_RESET_BUS_##bus) << 5U) | (bit)) argument
/Zephyr-latest/include/zephyr/arch/common/
Dffs.h5 * SPDX-License-Identifier: Apache-2.0
21 * @brief find most significant bit set in a 32-bit word
23 * This routine finds the first bit set starting from the most significant bit
24 * in the argument passed in and returns the index of that bit. Bits are
25 * numbered starting at 1 from the least significant bit. A return value of
28 * @return most significant bit set, 0 if @a op is 0
37 return 32 - __builtin_clz(op); in find_msb_set()
43 * @brief find least significant bit set in a 32-bit word
45 * This routine finds the first bit set starting from the least significant bit
46 * in the argument passed in and returns the index of that bit. Bits are
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/Zephyr-latest/dts/bindings/dma/
Dgd,gd32-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
9 config: A 32bit mask specifying the DMA channel configuration
10 - bit 6-7: Direction (see dma.h)
11 - 0x0: MEMORY to MEMORY
12 - 0x1: MEMORY to PERIPH
13 - 0x2: PERIPH to MEMORY
14 - 0x3: reserved for PERIPH to PERIPH
16 - bit 9: Peripheral address increase
17 - 0x0: no address increment between transfers
18 - 0x1: increment address between transfers
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Dgd,gd32-dma-v1.yaml2 # SPDX-License-Identifier: Apache-2.0
11 config: A 32bit mask specifying the DMA channel configuration
12 - bit 6-7: Direction (see dma.h)
13 - 0x0: MEMORY to MEMORY
14 - 0x1: MEMORY to PERIPH
15 - 0x2: PERIPH to MEMORY
16 - 0x3: reserved for PERIPH to PERIPH
18 - bit 9: Peripheral address increase
19 - 0x0: no address increment between transfers
20 - 0x1: increment address between transfers
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/Zephyr-latest/include/zephyr/arch/x86/intel64/
Dthread.h3 * SPDX-License-Identifier: Apache-2.0
12 * GDT selectors - these must agree with the GDT layout in locore.S.
15 #define X86_KERNEL_CS_32 0x08 /* 32-bit kernel code */
16 #define X86_KERNEL_DS_32 0x10 /* 32-bit kernel data */
17 #define X86_KERNEL_CS 0x18 /* 64-bit kernel code */
18 #define X86_KERNEL_DS 0x20 /* 64-bit kernel data */
19 #define X86_USER_CS_32 0x28 /* 32-bit user data (unused) */
20 #define X86_USER_DS 0x30 /* 64-bit user mode data */
21 #define X86_USER_CS 0x38 /* 64-bit user mode code */
23 /* Value programmed into bits 63:32 of STAR MSR with proper segment
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/Zephyr-latest/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/
Ddebug.h2 * Copyright (c) 2016-2020 Nordic Semiconductor ASA
5 * SPDX-License-Identifier: Apache-2.0
22 #define DEBUG_PIN0 BIT(DEBUG_PIN_IDX0)
23 #define DEBUG_PIN1 BIT(DEBUG_PIN_IDX1)
24 #define DEBUG_PIN2 BIT(DEBUG_PIN_IDX2)
25 #define DEBUG_PIN3 BIT(DEBUG_PIN_IDX3)
26 #define DEBUG_PIN4 BIT(DEBUG_PIN_IDX4)
27 #define DEBUG_PIN5 BIT(DEBUG_PIN_IDX5)
28 #define DEBUG_PIN6 BIT(DEBUG_PIN_IDX6)
29 #define DEBUG_PIN7 BIT(DEBUG_PIN_IDX7)
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/Zephyr-latest/boards/native/nrf_bsim/common/cmsis/
Dcmsis_instr.h4 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
6 * SPDX-License-Identifier: Apache-2.0
11 * ARM Cortex-M CMSIS intrinsics.
17 /* Implement the following ARM intrinsics as no-op:
18 * - ARM Data Synchronization Barrier
19 * - ARM Data Memory Synchronization Barrier
20 * - ARM Instruction Synchronization Barrier
21 * - ARM No Operation
44 * Implement the following ARM intrinsics as non-exclusive accesses
46 * - STR Exclusive(8,16 & 32bit) (__STREX{B,H,W})
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/Zephyr-latest/include/zephyr/arch/x86/
Dmsr.h3 * SPDX-License-Identifier: Apache-2.0
16 #define X86_SPEC_CTRL_MSR_IBRS BIT(0)
17 #define X86_SPEC_CTRL_MSR_SSBD BIT(2)
20 #define X86_APIC_BASE_MSR_X2APIC BIT(10)
23 #define X86_MTRR_DEF_TYPE_MSR_ENABLE BIT(11)
28 #define X86_EFER_MSR_SCE BIT(0)
29 #define X86_EFER_MSR_LME BIT(8)
30 #define X86_EFER_MSR_NXE BIT(11)
33 * 47:32 Kernel CS (SS = CS+8)
41 /* Low 32 bits in this MSR are the SYSCALL mask applied to EFLAGS */
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/Zephyr-latest/arch/posix/
DLinux.aarch64.cmake1 # SPDX-License-Identifier: Apache-2.0
4 # distributions. Userspace is (generally) either 32-bit or 64-bit but not
18 if (${WORDSIZE} STREQUAL "32")
20 "CONFIG_64BIT=y but this Aarch64 machine has a 32-bit userspace.\n"
25 zephyr_compile_options(-fPIC)
29 "CONFIG_64BIT=n but this Aarch64 machine has a 64-bit userspace.\n"

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