Lines Matching +full:32 +full:- +full:bit

4  * SPDX-License-Identifier: Apache-2.0
16 /* Offset 0x00 Power-Fail and Reset Status */
26 #define MCHP_VBATR_PFRS_SYS_RST		BIT(2)
27 #define MCHP_VBATR_PFRS_JTAG		BIT(3)
28 #define MCHP_VBATR_PFRS_RESETI		BIT(4)
29 #define MCHP_VBATR_PFRS_WDT		BIT(5)
30 #define MCHP_VBATR_PFRS_SYSRESETREQ	BIT(6)
31 #define MCHP_VBATR_PFRS_VBAT_RST	BIT(7)
33 /* Offset 0x08 32K Clock Source register */
44 /* Enable and start internal 32KHz Silicon Oscillator */
45 #define MCHP_VBATR_CS_SO_EN		BIT(0)
47 #define MCHP_VBATR_CS_XTAL_EN		BIT(8)
49 #define MCHP_VBATR_CS_XTAL_SE		BIT(9)
51 #define MCHP_VBATR_CS_XTAL_DHC		BIT(10)
57 /* Select source of peripheral 32KHz clock */
64 /* 32K silicon OSC when chip powered by VBAT or VTR */
66 /* 32K external crystal when chip powered by VBAT or VTR */
68 /* 32K input pin on VTR. Switch to Silicon OSC on VBAT */
70 /* 32K input pin on VTR. Switch to crystal on VBAT */
72 /* Disable internal 32K VBAT clock source when VTR is off */
74 #define MCHP_VBATR_CS_DI32_VTR_OFF		BIT(18)
77  * Monotonic Counter least significant word (32-bit), read-only.
82 /* Monotonic Counter most significant word (32-bit). Read-Write */
90 #define MCHP_VBATR_EMBRD_EN		BIT(0)