Lines Matching +full:32 +full:- +full:bit
3 * SPDX-License-Identifier: Apache-2.0
12 * GDT selectors - these must agree with the GDT layout in locore.S.
15 #define X86_KERNEL_CS_32 0x08 /* 32-bit kernel code */
16 #define X86_KERNEL_DS_32 0x10 /* 32-bit kernel data */
17 #define X86_KERNEL_CS 0x18 /* 64-bit kernel code */
18 #define X86_KERNEL_DS 0x20 /* 64-bit kernel data */
19 #define X86_USER_CS_32 0x28 /* 32-bit user data (unused) */
20 #define X86_USER_DS 0x30 /* 64-bit user mode data */
21 #define X86_USER_CS 0x38 /* 64-bit user mode code */
23 /* Value programmed into bits 63:32 of STAR MSR with proper segment
28 #define X86_KERNEL_CPU0_TR 0x40 /* 64-bit task state segment */
29 #define X86_KERNEL_CPU1_TR 0x50 /* 64-bit task state segment */
30 #define X86_KERNEL_CPU2_TR 0x60 /* 64-bit task state segment */
31 #define X86_KERNEL_CPU3_TR 0x70 /* 64-bit task state segment */
34 * Some SSE definitions. Ideally these will ultimately be shared with 32-bit.
40 /* MXCSR Control and Status Register for SIMD floating-point operations.
41 * Set default value 1F80H according to the Intel(R) 64 and IA-32 Manual.
42 * Disable denormals-are-zeros mode.
52 * 64-bit Task State Segment. One defined per CPU.
57 * Architecturally-defined portion. It is somewhat tedious to
83 * Zephyr specific portion. Stash per-CPU data here for convenience.
129 * Un-set for supervisor threads.