Lines Matching +full:32 +full:- +full:bit

4  * SPDX-License-Identifier: Apache-2.0
35 #define NMI_STS_SRC_SERR	BIT(7)
43 #define NMI_STS_SERR_EN		BIT(2)
48  * In-Band Error Correction Code (IBECC) protects data at a cache line
51  *   - CMI (Converged Memory Interface) Address
52  *   - Syndrome
53  *   - Error Type (Correctable, Uncorrectable)
60 /* Top of Upper Usable DRAM, offset 0xa8, 64 bit */
64 /* Top of Low Usable DRAM, offset 0xbc, 32 bit */
68 /* Total amount of physical memory, offset 0xa0, 64 bit */
73  * offset 0x48, 64 bit
81 /* Capability register, offset 0xec, 32 bit */
83 #define CAPID0_C_IBECC_ENABLED	BIT(15)
85 /* Register controlling reporting error SERR, offset 0xc8, 16 bit */
87 #define ERRSTS_IBECC_COR	BIT(6) /* Correctable error */
88 #define ERRSTS_IBECC_UC		BIT(7) /* Uncorrectable error */
91  * offset 0xca, 16 bit
94  * ERRSTS_REG with 32 bit access and get this 16 bits
97 #define ERRCMD_IBECC_COR	BIT(6)	/* Correctable error */
98 #define ERRCMD_IBECC_UC		BIT(7)	/* Uncorrectable error */
120 /* ECC Error Log register, 64 bit (ECC_ERROR_LOG) */
122 /* Uncorrectable (Multiple-bit) Error Status (MERRSTS) */
142 /* Memory channel decoding register, 32 bit */
152 /* DRAM decode stage 2 registers, 32 bit */
157 /* DIMM channel characteristic 2 registers, 32 bit */
169 /* MC Channel Selection register, 32 bit */
172 /* MC Enhanced Channel Selection register, 32 bit */