Lines Matching +full:32 +full:- +full:bit
1 /* i2c_dw_registers.h - array access for I2C Design Ware registers */
6 * SPDX-License-Identifier: Apache-2.0
33 #define IC_DATA_CMD_CMD BIT(8)
34 #define IC_DATA_CMD_STOP BIT(9)
35 #define IC_DATA_CMD_RESTART BIT(10)
38 #define DW_INTR_STAT_RX_UNDER BIT(0)
39 #define DW_INTR_STAT_RX_OVER BIT(1)
40 #define DW_INTR_STAT_RX_FULL BIT(2)
41 #define DW_INTR_STAT_TX_OVER BIT(3)
42 #define DW_INTR_STAT_TX_EMPTY BIT(4)
43 #define DW_INTR_STAT_RD_REQ BIT(5)
44 #define DW_INTR_STAT_TX_ABRT BIT(6)
45 #define DW_INTR_STAT_RX_DONE BIT(7)
46 #define DW_INTR_STAT_ACTIVITY BIT(8)
47 #define DW_INTR_STAT_STOP_DET BIT(9)
48 #define DW_INTR_STAT_START_DET BIT(10)
49 #define DW_INTR_STAT_GEN_CALL BIT(11)
50 #define DW_INTR_STAT_RESTART_DET BIT(12)
51 #define DW_INTR_STAT_MST_ON_HOLD BIT(13)
53 #define DW_INTR_MASK_RX_UNDER BIT(0)
54 #define DW_INTR_MASK_RX_OVER BIT(1)
55 #define DW_INTR_MASK_RX_FULL BIT(2)
56 #define DW_INTR_MASK_TX_OVER BIT(3)
57 #define DW_INTR_MASK_TX_EMPTY BIT(4)
58 #define DW_INTR_MASK_RD_REQ BIT(5)
59 #define DW_INTR_MASK_TX_ABRT BIT(6)
60 #define DW_INTR_MASK_RX_DONE BIT(7)
61 #define DW_INTR_MASK_ACTIVITY BIT(8)
62 #define DW_INTR_MASK_STOP_DET BIT(9)
63 #define DW_INTR_MASK_START_DET BIT(10)
64 #define DW_INTR_MASK_GEN_CALL BIT(11)
65 #define DW_INTR_MASK_RESTART_DET BIT(12)
66 #define DW_INTR_MASK_MST_ON_HOLD BIT(13)
158 /* CON Bit */
162 #define DW_IC_DMA_RX_ENABLE BIT(0)
163 #define DW_IC_DMA_TX_ENABLE BIT(1)
164 #define DW_IC_DMA_ENABLE (BIT(0) | BIT(1))
167 DEFINE_MM_REG_WRITE(con, DW_IC_REG_CON, 32)
168 DEFINE_MM_REG_READ(con, DW_IC_REG_CON, 32)
170 DEFINE_MM_REG_WRITE(cmd_data, DW_IC_REG_DATA_CMD, 32)
171 DEFINE_MM_REG_READ(cmd_data, DW_IC_REG_DATA_CMD, 32)
173 DEFINE_MM_REG_WRITE(ss_scl_hcnt, DW_IC_REG_SS_SCL_HCNT, 32)
174 DEFINE_MM_REG_WRITE(ss_scl_lcnt, DW_IC_REG_SS_SCL_LCNT, 32)
176 DEFINE_MM_REG_WRITE(fs_scl_hcnt, DW_IC_REG_FS_SCL_HCNT, 32)
177 DEFINE_MM_REG_WRITE(fs_scl_lcnt, DW_IC_REG_FS_SCL_LCNT, 32)
179 DEFINE_MM_REG_WRITE(hs_scl_hcnt, DW_IC_REG_HS_SCL_HCNT, 32)
180 DEFINE_MM_REG_WRITE(hs_scl_lcnt, DW_IC_REG_HS_SCL_LCNT, 32)
182 DEFINE_MM_REG_READ(intr_stat, DW_IC_REG_INTR_STAT, 32)
186 DEFINE_MM_REG_WRITE(intr_mask, DW_IC_REG_INTR_MASK, 32)
191 DEFINE_MM_REG_WRITE(rx_tl, DW_IC_REG_RX_TL, 32)
192 DEFINE_MM_REG_WRITE(tx_tl, DW_IC_REG_TX_TL, 32)
194 DEFINE_MM_REG_READ(clr_intr, DW_IC_REG_CLR_INTR, 32)
195 DEFINE_MM_REG_READ(clr_stop_det, DW_IC_REG_CLR_STOP_DET, 32)
196 DEFINE_MM_REG_READ(clr_start_det, DW_IC_REG_CLR_START_DET, 32)
197 DEFINE_MM_REG_READ(clr_gen_call, DW_IC_REG_CLR_GEN_CALL, 32)
198 DEFINE_MM_REG_READ(clr_tx_abrt, DW_IC_REG_CLR_TX_ABRT, 32)
199 DEFINE_MM_REG_READ(clr_rx_under, DW_IC_REG_CLR_RX_UNDER, 32)
200 DEFINE_MM_REG_READ(clr_rx_over, DW_IC_REG_CLR_RX_OVER, 32)
201 DEFINE_MM_REG_READ(clr_tx_over, DW_IC_REG_CLR_TX_OVER, 32)
202 DEFINE_MM_REG_READ(clr_rx_done, DW_IC_REG_CLR_RX_DONE, 32)
203 DEFINE_MM_REG_READ(clr_rd_req, DW_IC_REG_CLR_RD_REQ, 32)
204 DEFINE_MM_REG_READ(clr_activity, DW_IC_REG_CLR_ACTIVITY, 32)
217 DEFINE_MM_REG_READ(txflr, DW_IC_REG_TXFLR, 32)
218 DEFINE_MM_REG_READ(rxflr, DW_IC_REG_RXFLR, 32)
220 DEFINE_MM_REG_READ(dma_cr, DW_IC_REG_DMA_CR, 32)
221 DEFINE_MM_REG_WRITE(dma_cr, DW_IC_REG_DMA_CR, 32)
223 DEFINE_MM_REG_READ(tdlr, DW_IC_REG_TDLR, 32)
224 DEFINE_MM_REG_WRITE(tdlr, DW_IC_REG_TDLR, 32)
225 DEFINE_MM_REG_READ(rdlr, DW_IC_REG_RDLR, 32)
226 DEFINE_MM_REG_WRITE(rdlr, DW_IC_REG_RDLR, 32)
228 DEFINE_MM_REG_READ(fs_spklen, DW_IC_REG_FS_SPKLEN, 32)
229 DEFINE_MM_REG_READ(hs_spklen, DW_IC_REG_HS_SPKLEN, 32)
231 DEFINE_MM_REG_READ(comp_param_1, DW_IC_REG_COMP_PARAM_1, 32)
232 DEFINE_MM_REG_READ(comp_type, DW_IC_REG_COMP_TYPE, 32)
233 DEFINE_MM_REG_READ(tar, DW_IC_REG_TAR, 32)
234 DEFINE_MM_REG_WRITE(tar, DW_IC_REG_TAR, 32)
235 DEFINE_MM_REG_WRITE(sar, DW_IC_REG_SAR, 32)