Lines Matching +full:32 +full:- +full:bit
4 * SPDX-License-Identifier: Apache-2.0
53 * CLK_REQ bits are read-only. The peripheral sets its CLK_REQ if it requires
56 * SLP_EN bit = 1 instructs HW to gate off clock tree to peripheral only if
57 * peripherals PCR CLK_REQ bit is 0.
58 * RST_EN bit = 1 will reset the peripheral at any time. The RST_EN registers
67 * SLEEP_ALL bit = 1.
68 * Execute Cortex-M4 WFI sequence. DSB(), ISB(), WFI(), NOP()
69 * Cortex-M4 will assert sleep signal to PCR block.
76 * Write bit patterns to one or more of PCR RST_EN[0, 4] registers
84 #define MCHP_PCR_SLP(bitpos) BIT(bitpos)
88 #define MCHP_PCR_SYS_SLP_CTRL_SLP_HEAVY BIT(0)
89 #define MCHP_PCR_SYS_SLP_CTRL_SLP_ALL BIT(3)
91 * bit[8] can be used to prevent entry to heavy sleep unless the
93 * bit[8]==0 (POR default) system will allow entry to light or heavy
95 * bit[8]==1 system will allow entry to heavy sleep before PLL is locked.
97 #define MCHP_PCR_SYS_SLP_CTRL_ALLOW_SLP_NO_PLL_LOCK BIT(8)
100 #define MCHP_PCR_SYS_SLP_LIGHT BIT(3)
101 #define MCHP_PCR_SYS_SLP_HEAVY (BIT(3) | BIT(0))
105 * Divides 96MHz clock to ARM Cortex-M4 core including
121 /* PCR Oscillator ID register (Read-Only) */
123 #define MCHP_PCR_OSC_ID_PLL_LOCK BIT(8)
128 #define MCHP_PCR_PRS_VCC_PWRGD_STATE_RO BIT(2)
129 #define MCHP_PCR_PRS_HOST_RESET_STATE_RO BIT(3)
130 #define MCHP_PCR_PRS_VTR_RST_RWC BIT(4)
131 #define MCHP_PCR_PRS_VBAT_RST_RWC BIT(5)
132 #define MCHP_PCR_PRS_RST_SYS_RWC BIT(6)
133 #define MCHP_PCR_PRS_JTAG_RST_RO BIT(7)
134 #define MCHP_PCR_PRS_WDT_EVENT_RWC BIT(8)
135 #define MCHP_PCR_PRS_32K_ACTIVE_RO BIT(10)
136 #define MCHP_PCR_PRS_LPC_ESPI_CLK_ACTIVE_RO BIT(11)
139 #define MCHP_PCR_PR_CTRL_MASK (BIT(8) | BIT(0))
140 #define MCHP_PCR_PR_CTRL_PWR_INV BIT(0)
142 #define MCHP_PCR_PR_CTRL_USE_PCI_RST BIT(8)
145 #define MCHP_PCR_SYS_RESET_MASK BIT(8)
146 #define MCHP_PCR_SYS_RESET_NOW BIT(8)
149 #define MCHP_PCR_TURBO_CLK_MASK BIT(2)
150 #define MCHP_PCR_TURBO_CLK_96M BIT(2)
244 #define MCHP_PCR3_CRYPTO_MASK BIT(MCHP_PCR3_CRYPTO_POS)
273 #define MCHP_PCR_VBSR_MASK BIT(0)
274 #define MCHP_PCR_VBSR_EN BIT(0) /* self clearing */
276 /* VTR Source 32 KHz Clock (Offset +8Ch) */
279 #define MCHP_PCR_VTR_32K_SRC_XTAL BIT(0)
280 #define MCHP_PCR_VTR_32K_SRC_PIN BIT(1)
281 #define MCHP_PCR_VTR_32K_SRC_NONE (BIT(0) | BIT(1))
284 * Clock monitor 32KHz period counter (Offset +C0h, RO)
285 * Clock monitor 32KHz high counter (Offset +C4h, RO)
286 * Clock monitor 32KHz period counter minimum (Offset +C8h, RW)
287 * Clock monitor 32KHz period counter maximum (Offset +CCh, RW)
288 * Clock monitor 32KHz Duty Cycle variation counter (Offset +D0h, RO)
289 * Clock monitor 32KHz Duty Cycle variation counter maximum (Offset +D4h, RW)
294 * Clock monitor 32KHz Valid Count (Offset +0xD8, RO)
295 * Clock monitor 32KHz Valid Count minimum (Offset +0xDC, RW)
300 #define MCHP_PCR_CLK32M_CTRL_MASK (BIT(24) | BIT(4) | GENMASK(2, 0))
301 #define MCHP_PCR_CLK32M_CTRL_PER_EN BIT(0)
302 #define MCHP_PCR_CLK32M_CTRL_DC_EN BIT(1)
303 #define MCHP_PCR_CLK32M_CTRL_VAL_EN BIT(2)
304 #define MCHP_PCR_CLK32M_CTRL_SRC_SO BIT(4)
305 #define MCHP_PCR_CLK32M_CTRL_CLR_CNT BIT(24)
309 #define MCHP_PCR_CLK32M_ISTS_PULSE_RDY BIT(0)
310 #define MCHP_PCR_CLK32M_ISTS_PASS_PER BIT(1)
311 #define MCHP_PCR_CLK32M_ISTS_PASS_DC BIT(2)
312 #define MCHP_PCR_CLK32M_ISTS_FAIL BIT(3)
313 #define MCHP_PCR_CLK32M_ISTS_STALL BIT(4)
314 #define MCHP_PCR_CLK32M_ISTS_VALID BIT(5)
315 #define MCHP_PCR_CLK32M_ISTS_UNWELL BIT(6)
319 #define MCHP_PCR_CLK32M_IEN_PULSE_RDY BIT(0)
320 #define MCHP_PCR_CLK32M_IEN_PASS_PER BIT(1)
321 #define MCHP_PCR_CLK32M_IEN_PASS_DC BIT(2)
322 #define MCHP_PCR_CLK32M_IEN_FAIL BIT(3)
323 #define MCHP_PCR_CLK32M_IEN_STALL BIT(4)
324 #define MCHP_PCR_CLK32M_IEN_VALID BIT(5)
325 #define MCHP_PCR_CLK32M_IEN_UNWELL BIT(6)
327 /* PCR 32KHz clock monitor uses 48 MHz for all counters */
350 uint32_t RSVD4[(0x00c0 - 0x0094) / 4];