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/Zephyr-latest/soc/espressif/esp32s3/
DKconfig24 If you use 16KB instruction cache rather than 32KB instruction cache,
25 then the other 16KB will be managed by heap allocator.
28 bool "16KB"
30 bool "32KB"
62 bool "16 Bytes"
70 default 16 if ESP32S3_INSTRUCTION_CACHE_LINE_16B
85 If you use 32KB data cache rather than 64KB data cache,
86 the other 32KB will be added to the heap.
89 bool "16KB"
91 bool "32KB"
[all …]
/Zephyr-latest/soc/espressif/esp32s2/
DKconfig24 bool "16 Bytes"
36 bool "8KB instruction cache size"
39 bool "16KB instruction cache size"
50 bool "0KB"
52 bool "8KB"
54 bool "16KB"
63 bool "16 Bytes"
/Zephyr-latest/samples/subsys/display/lvgl/boards/
Dmax32662evkit.overlay14 * Concatenate SRAM0(16KB), SRAM1(16KB) and SRAM2(16KB)
/Zephyr-latest/drivers/flash/
Dflash_gd32_v3.c25 {.pages_count = 4, .pages_size = KB(16)},
26 {.pages_count = 1, .pages_size = KB(64)},
27 {.pages_count = 3, .pages_size = KB(128)},
31 {.pages_count = 4, .pages_size = KB(16)},
32 {.pages_count = 1, .pages_size = KB(64)},
33 {.pages_count = 7, .pages_size = KB(128)},
37 {.pages_count = 4, .pages_size = KB(16)},
38 {.pages_count = 1, .pages_size = KB(64)},
39 {.pages_count = 7, .pages_size = KB(128)},
40 {.pages_count = 4, .pages_size = KB(16)},
[all …]
Dflash_stm32f4x.c104 * Disable the data cache to avoid the silicon errata ES0206 Rev 16 2.2.12: in write_value()
328 * sectors (16 KB) in the second bank occurring after the large ones
329 * (128 KB) in the first. We could consider supporting this as two
338 {.pages_count = 4, .pages_size = KB(16)},
339 {.pages_count = 1, .pages_size = KB(64)},
344 {.pages_count = 4, .pages_size = KB(16)},
345 {.pages_count = 1, .pages_size = KB(64)},
346 {.pages_count = 1, .pages_size = KB(128)},
355 {.pages_count = 4, .pages_size = KB(16)},
356 {.pages_count = 1, .pages_size = KB(64)},
[all …]
Dflash_stm32f7x.c229 {.pages_count = 2, .pages_size = KB(32)},
234 {.pages_count = 4, .pages_size = KB(16)},
240 {.pages_count = 4, .pages_size = KB(16)},
241 {.pages_count = 1, .pages_size = KB(64)},
242 {.pages_count = 3, .pages_size = KB(128)},
247 {.pages_count = 4, .pages_size = KB(32)},
248 {.pages_count = 1, .pages_size = KB(128)},
249 {.pages_count = 3, .pages_size = KB(256)},
255 {.pages_count = 4, .pages_size = KB(32)},
256 {.pages_count = 1, .pages_size = KB(128)},
[all …]
/Zephyr-latest/samples/drivers/flash_shell/boards/
Dgd32vf103c_starter.conf1 # This board only has 32KB SRAM, can not afford 16 KB memory pool, use 8KB instead.
Dgd32vf103v_eval.conf1 # This board only has 32KB SRAM, can not afford 16 KB memory pool, use 8KB instead.
/Zephyr-latest/dts/arm/st/f7/
Dstm32f722.dtsi10 /* 16KB ITCM @ 0x0, 64KB DTCM @ 0x20000000,
11 * 176KB SRAM1 @ 0x20010000, 16KB SRAM2 @ 0x2003C00
28 reg = <0x00000000 DT_SIZE_K(16)>;
/Zephyr-latest/soc/ite/ec/it8xxx2/
Dilm.c61 /* Bits 16..18 and 19 of address, plus the enable bit for the entire SCAR; SCARnH */
114 uint8_t scarh_value = ((uintptr_t)flash_addr & GENMASK(18, 16)) >> 16; in it8xxx2_configure_ilm_block()
162 /* SCAR0 SRAM 4KB */
180 * maximum ILM size are 60KB, the ILM size of other varients
184 /* SCAR15 SRAM 4KB */
186 /* SCAR16 SRAM 16KB */
187 SCAR_REG(16), SCAR_REG(16), SCAR_REG(16), SCAR_REG(16),
188 /* SCAR17 SRAM 16KB */
190 /* SCAR18 SRAM 16KB */
192 /* SCAR19 SRAM 16KB */
[all …]
/Zephyr-latest/tests/drivers/wifi/nrf_wifi/
Dprj.conf32 CONFIG_NET_BUF_RX_COUNT=16
33 CONFIG_NET_BUF_TX_COUNT=16
34 CONFIG_NRF70_RX_NUM_BUFS=16
36 # nRF70 is main consumer: (16 + 8) * 1600 = ~40KB + ~40KB control path (experimental)
84 CONFIG_NET_MGMT_EVENT_QUEUE_SIZE=16
/Zephyr-latest/dts/arm/gd/gd32l23x/
Dgd32l233rc.dtsi14 reg = <0x20004000 DT_SIZE_K(16)>;
17 /* Combine SRAM0(16K) and SRAM1(16K), since its address is continuous. */
38 * From other GD32 DataSheets, we can find 1KB page normally have a
41 * time to 4 times of 1KB page.
/Zephyr-latest/dts/common/nordic/
Dnrf5340_cpuapp_partition.dtsi14 * 0x0000_0000 BL2 - MCUBoot (64 KB)
15 * 0x0001_0000 Primary image area (448 KB):
16 * 0x0001_0000 Secure image primary (256 KB)
17 * 0x0005_0000 Non-secure image primary (192 KB)
18 * 0x0008_0000 Secondary image area (448 KB):
19 * 0x0008_0000 Secure image secondary (256 KB)
20 * 0x000c_0000 Non-secure image secondary (192 KB)
21 * 0x000f_0000 Protected Storage Area (16 KB)
22 * 0x000f_4000 Internal Trusted Storage Area (8 KB)
23 * 0x000f_6000 OTP / NV counters area (8 KB)
[all …]
Dnrf91xx_partition.dtsi14 * 0x0000_0000 BL2 - MCUBoot (64 KB)
15 * 0x0001_0000 Primary image area (448 KB):
16 * 0x0001_0000 Secure image primary (256 KB)
17 * 0x0005_0000 Non-secure image primary (192 KB)
18 * 0x0008_0000 Secondary image area (448 KB):
19 * 0x0008_0000 Secure image secondary (256 KB)
20 * 0x000c_0000 Non-secure image secondary (192 KB)
21 * 0x000f_0000 Protected Storage Area (16 KB)
22 * 0x000f_4000 Internal Trusted Storage Area (8 KB)
23 * 0x000f_6000 OTP / NV counters area (8 KB)
[all …]
Dnrf54l05.dtsi14 /* 72 + 24 = 96KB */
31 /* 470 + 30 = 500KB */
37 write-block-size = <16>;
Dnrf54l10.dtsi14 /* 144 + 48 = 192KB */
31 /* 960 + 62 = 1022KB */
37 write-block-size = <16>;
Dnrf54l15.dtsi14 /* 188 + 68 = 256KB */
31 /* 1428 + 96 = 1524KB */
37 write-block-size = <16>;
/Zephyr-latest/soc/espressif/esp32c2/
Dmemory.h7 /* SRAM0 (16kB) memory */
11 /* SRAM1 (256kB) memory */
16 /* ICache size is fixed to 16KB on ESP32-C2 */
/Zephyr-latest/boards/silabs/radio_boards/slwrb4161a/
Dslwrb4161a.dts26 /* Reserve 32 kB for the bootloader */
33 /* Reserve 220 kB for the application in slot 0 */
39 /* Reserve 220 kB for the application in slot 1 */
45 /* Reserve 32 kB for the scratch partition */
51 /* Set 8Kb of storage at the end of the 512KB of flash */
65 <GECKO_LOC(I2C_SDA, 16)>,
/Zephyr-latest/boards/seagate/legend/
Dlegend.dts103 * Total size : 256 KB
104 * Erase size : whole chip, 64 and 32 KB blocks, 4 KB sectors,
115 * Total size : 128 KB
116 * Erase size : whole chip, 64 and 32 KB blocks, 4 KB sectors
126 * Total size : 64 KB
127 * Erase size : whole chip, 64 and 32 KB blocks, 4 KB sectors
169 * counter_size = 2^16
174 * prescaler = 48 MHz * 0.25 / 2^16 + 1 = 182
/Zephyr-latest/boards/intel/ish/doc/
Dindex.rst17 - 16KB instruction cache and 16KB data cache.
18 - 640KB SRAM space for code and data - implemented as L2 SRAM.
19 - 8KB AON RF space for code resident during deep D0i2/3 PG states.
/Zephyr-latest/soc/espressif/esp32c3/
Dmemory.h7 /* SRAM0 (16kB) memory */
10 /* SRAM1 (384kB) memory */
14 /* ICache size is fixed to 16KB on ESP32-C3 */
/Zephyr-latest/boards/silabs/radio_boards/xg23_rb4210a/
Dxg23_rb4210a.dts170 /* Reserve 48 kB for the bootloader */
177 /* Reserve 208 kB for the application in slot 0 */
183 /* Reserve 208 kB for the application in slot 1 */
189 /* Reserve 32 kB for the scratch partition */
195 /* Set 16 kB of storage at the end of the 1536 kB of flash */
198 reg = <0x0007c000 DT_SIZE_K(16)>;
/Zephyr-latest/boards/silabs/radio_boards/xg24_rb4187c/
Dxg24_rb4187c.dts173 /* Reserve 48 kB for the bootloader */
180 /* Reserve 720 kB for the application in slot 0 */
186 /* Reserve 720 kB for the application in slot 1 */
192 /* Reserve 32 kB for the scratch partition */
198 /* Set 16 kB of storage at the end of the 1536 kB of flash */
201 reg = <0x0017c000 DT_SIZE_K(16)>;
/Zephyr-latest/soc/espressif/esp32c6/
Dmemory.h7 /* LP-SRAM (16kB) memory */
10 /* HP-SRAM (512kB) memory */
15 /* ICache size is fixed to 32KB on ESP32-C6 */

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