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/Zephyr-latest/include/zephyr/dt-bindings/ethernet/
Dxlnx_gem.h28 #define XLNX_GEM_MDC_DIVIDER_8 0 /* cpu_1x or IOU_SWITCH_CLK < 20 MHz */
29 #define XLNX_GEM_MDC_DIVIDER_16 1 /* cpu_1x or IOU_SWITCH_CLK 20 - 40 MHz */
30 #define XLNX_GEM_MDC_DIVIDER_32 2 /* cpu_1x or IOU_SWITCH_CLK 40 - 80 MHz */
31 #define XLNX_GEM_MDC_DIVIDER_48 3 /* cpu_1x or IOU_SWITCH_CLK 80 - 120 MHz */
32 #define XLNX_GEM_MDC_DIVIDER_64 4 /* cpu_1x or IOU_SWITCH_CLK 120 - 160 MHz */
33 #define XLNX_GEM_MDC_DIVIDER_96 5 /* cpu_1x or IOU_SWITCH_CLK 160 - 240 MHz */
34 #define XLNX_GEM_MDC_DIVIDER_128 6 /* cpu_1x or IOU_SWITCH_CLK 240 - 320 MHz */
35 #define XLNX_GEM_MDC_DIVIDER_224 7 /* cpu_1x or IOU_SWITCH_CLK 320 - 540 MHz */
/Zephyr-latest/soc/espressif/common/
DKconfig.esptool88 bool "120 MHz"
92 - Flash 120 MHz SDR mode is stable.
93 - Flash 120 MHz DDR mode is an experimental feature, it works when
102 bool "80 MHz"
104 bool "60 MHz"
106 bool "40 MHz"
108 bool "26 MHz"
111 bool "20 MHz"
119 This is an invisible item, used to define the targets that defaults to use 80MHz Flash SPI speed.
DKconfig.spiram87 bool "20MHz clock speed"
91 bool "26MHz clock speed"
95 bool "40MHz clock speed"
98 bool "80MHz clock speed"
102 bool "120MHz clock speed"
109 default 120 if SPIRAM_SPEED_120M
/Zephyr-latest/soc/sifive/sifive_freedom/fu500/
Dclock.c12 BUILD_ASSERT(MHZ(1000) == DT_PROP(DT_NODELABEL(coreclk), clock_frequency),
18 * Switch the clock source to 1GHz PLL from 33.333MHz oscillator on the HiFive
25 PLL_R(0) | /* input divider: Fin / (0 + 1) = 33.33MHz */ in soc_early_init_hook()
26 PLL_F(59) | /* VCO: 2 x (59 + 1) = 120 = 3999.6MHz */ in soc_early_init_hook()
27 PLL_Q(2) | /* output divider: VCO / 2^2 = 999.9MHz */ in soc_early_init_hook()
/Zephyr-latest/tests/benchmarks/latency_measure/boards/
Dfrdm_k64f.conf2 # allow for a tickless kernel given its 24-bit timer and its 120 MHz
/Zephyr-latest/soc/xlnx/zynq7000/xc7zxxxs/
DKconfig.soc20 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
27 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
28 55k logic cells, 2.5Mb block RAM, 120 DSP slices, up to 150 I/O pins,
35 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
/Zephyr-latest/soc/nxp/kinetis/k2x/
Dsoc.c83 * PLL Engaged External (PEE) mode and generate the maximum 120 MHz system
126 /* Initialize PLL/system clock to 120 MHz */ in soc_early_init_hook()
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/
Dpll_csi_240.overlay17 /* Test another couple of M-div N-mul to obtain 240MHz from the CSI */
20 mul-n = <120>;
/Zephyr-latest/soc/nuvoton/npcx/common/
Dsoc_clock.h63 * Maximum OFMCLK in npcx7/9 series is 100MHz,
64 * Maximum OFMCLK in npcx4 series is 120MHz,
109 #if (OFMCLK == MHZ(120)) /* MCLkD must between 40 mhz to 50 mhz*/
111 #elif (OFMCLK <= MHZ(100) && OFMCLK >= MHZ(80))
/Zephyr-latest/boards/st/nucleo_h745zi_q/
Dnucleo_h745zi_q_stm32h745xx_m7.dts58 clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
64 mul-n = <120>;
151 /* HSE will be used by default. Uncomment below to enable APB1.2 120MHz clock */
/Zephyr-latest/dts/bindings/clock/
Dnuvoton,npcx-pcc.yaml14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
35 120000000, 120 MHz
36 100000000, 100 MHz
37 96000000, 96 MHz
38 90000000, 90 MHz
39 80000000, 80 MHz
[all …]
/Zephyr-latest/boards/st/sensortile_box/doc/
Dindex.rst25 execution from Flash memory, frequency up to 120 MHz, MPU, 150
26 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
29 - 16 MHz crystal oscillator
96 driven by the PLL clock at 80MHz, driven by the 16MHz external oscillator.
97 The system clock can be boosted to 120MHz.
98 The internal AHB/APB1/APB2 AMBA buses are all clocked at 80MHz.
/Zephyr-latest/boards/renesas/ek_ra6m2/doc/
Dindex.rst18 - 120MHz Arm Cortex-M4 based RA6M2 MCU in 144 pins, LQFP package
22 providing precision 12.000 MHz and 32,768 Hz reference clock.
140 * Target Interface Speed: 4 MHz
156 …ntrollers-microprocessors/ra-cortex-m-mcus/ra6m2-32-bit-microcontrollers-120mhz-medium-size-memory…
/Zephyr-latest/boards/st/nucleo_l4r5zi/doc/
Dindex.rst34 and 100 uA/MHz run mode)
37 execution from Flash memory, frequency up to 120 MHz, MPU, 150
38 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
41 - 4 to 48 MHz crystal oscillator
43 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
45 - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
47 - Internal 48 MHz with clock recovery
100 - 8- to 14-bit camera interface up to 32 MHz (black and white) or 10 MHz (color)
199 driven by the PLL clock at 80MHz, driven by a 16MHz high speed
200 internal oscillator. The clock can be boosted to 120MHz if boost mode
/Zephyr-latest/boards/infineon/xmc45_relax_kit/doc/
Dindex.rst8 up to 120MHz.
25 * The on-board 12-MHz crystal allows the device to run at its maximum operating speed of 120MHz.
/Zephyr-latest/boards/renesas/ek_ra6m1/doc/
Dindex.rst22 - 120 MHz Arm® Cortex®-M4 core with Floating Point Unit (FPU)
37 - Main MCU oscillator crystals, providing precision 12.000 MHz and 32,768 Hz external reference
146 * Target Interface Speed: 4 MHz
162 …ntrollers-microprocessors/ra-cortex-m-mcus/ra6m1-32-bit-microcontrollers-120mhz-optimized-entry-po…
/Zephyr-latest/boards/renesas/ek_ra6m3/doc/
Dindex.rst18 - 120MHz Arm Cortex-M4 based RA6M3 MCU in 176 pins, LQFP package
22 providing precision 24.000 MHz and 32,768 Hz reference clock.
150 * Target Interface Speed: 4 MHz
166 …ntrollers-microprocessors/ra-cortex-m-mcus/ra6m3-32-bit-microcontrollers-120mhz-usb-high-speed-eth…
/Zephyr-latest/boards/seeed/wio_terminal/doc/
Dindex.rst14 - ATSAMD51P19 ARM Cortex-M4F processor at 120 MHz
104 on-chip PLL generating the 120 MHz system clock.
/Zephyr-latest/boards/adi/max32690fthr/doc/
Dindex.rst20 - 120MHz Arm Cortex-M4 Processor with FPU
21 - 7.3728MHz and 60MHz Low-Power Oscillators
22 - External Crystal Support (32MHz required for BLE)
26 - 85 μW/MHz ACTIVE mode at 1.1V
44 - Up To Five Quad SPI Master (60MHz)/Slave (48MHz)
46 - Up To Two 1MHz I2C Master/Slave
/Zephyr-latest/soc/nxp/kinetis/k6x/
Dsoc.c86 * PLL Engaged External (PEE) mode and generate the maximum 120 MHz system
162 /* Initialize PLL/system clock up to 180 MHz */ in soc_early_init_hook()
/Zephyr-latest/boards/adi/sdp_k1/doc/
Dindex.rst18 - VIN from 120-pin connector 5 V min. 300 mA
22 - Arduino UNO and 120-pin SDP connectors
33 - 180 MHz max CPU frequency
100 120-pin SDP connector
105 :alt: ADI SDP-K1 120-pin SDP connector pinout
/Zephyr-latest/boards/st/nucleo_h755zi_q/
Dnucleo_h755zi_q_stm32h755xx_m7.dts57 clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
63 mul-n = <120>;
/Zephyr-latest/dts/arm/nuvoton/npcx/
Dnpcx4.dtsi153 clock-frequency = <DT_FREQ_M(120)>; /* OFMCLK runs at 120MHz */
154 core-prescaler = <8>; /* CORE_CLK runs at 15MHz */
155 apb1-prescaler = <8>; /* APB1_CLK runs at 15MHz */
156 apb2-prescaler = <8>; /* APB2_CLK runs at 15MHz */
157 apb3-prescaler = <8>; /* APB3_CLK runs at 15MHz */
158 apb4-prescaler = <8>; /* APB4_CLK runs at 15MHz */
/Zephyr-latest/boards/adafruit/feather_m4_express/doc/
Dindex.rst14 - ATSAMD51J19A ARM Cortex-M4 processor at 120 MHz
17 - Internal trimmed 8 MHz oscillator
75 with the on-chip PLL generating the 120 MHz system clock.
/Zephyr-latest/boards/adafruit/itsybitsy_m4_express/doc/
Dindex.rst13 - ATSAMD51G19A ARM Cortex-M4 processor at 120 MHz
16 - Internal trimmed 8 MHz oscillator
76 with the on-chip PLL generating the 120 MHz system clock.

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