1/*
2 * Copyright (c) 2020 Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <st/h7/stm32h745Xi_m7.dtsi>
9#include "nucleo_h745zi_q.dtsi"
10
11/*
12 * WARNING:
13 * Possible pin conflicts: The pins PA2 and PB13 may conflict on selection of
14 * ETH_STM32_HAL, since they are used in ST Zio or ST morpho connectors. To
15 * avoid conflicting states the jumpers JP6 and JP7 must be in ON state.
16 */
17
18/ {
19	model = "STMicroelectronics STM32H745ZI-Q-NUCLEO board";
20	compatible = "st,stm32h745zi-q-nucleo";
21
22	/* HW resources belonging to CM7 */
23	chosen {
24		zephyr,console = &usart3;
25		zephyr,shell-uart = &usart3;
26		zephyr,dtcm = &dtcm;
27		zephyr,sram = &sram0;
28		zephyr,flash = &flash0;
29		zephyr,canbus = &fdcan1;
30	};
31
32	pwmleds {
33		compatible = "pwm-leds";
34
35		red_pwm_led: red_pwm_led {
36			pwms = <&pwm12 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
37			label = "User LD3 - PWM12";
38		};
39	};
40
41	aliases {
42		led0 = &green_led;
43		pwm-led0 = &red_pwm_led;
44		sw0 = &user_button;
45	};
46};
47
48&clk_lsi {
49	status = "okay";
50};
51
52&clk_hsi48 {
53	status = "okay";
54};
55
56&clk_hse {
57	hse-bypass;
58	clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
59	status = "okay";
60};
61
62&pll {
63	div-m = <1>;
64	mul-n = <120>;
65	div-p = <2>;
66	div-q = <8>;
67	div-r = <2>;
68	clocks = <&clk_hse>;
69	status = "okay";
70};
71
72&rcc {
73	clocks = <&pll>;
74	clock-frequency = <DT_FREQ_M(480)>;
75};
76
77&usart3 {
78	pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
79	pinctrl-names = "default";
80	current-speed = <115200>;
81	status = "okay";
82};
83
84&rtc {
85	clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>,
86		 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
87	status = "okay";
88};
89
90&i2c1 {
91	pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
92	pinctrl-names = "default";
93	status = "okay";
94	clock-frequency = <I2C_BITRATE_FAST>;
95};
96
97&timers12 {
98	st,prescaler = <10000>;
99	status = "okay";
100
101	pwm12: pwm {
102		status = "okay";
103		pinctrl-0 = <&tim12_ch1_pb14>;
104		pinctrl-names = "default";
105	};
106};
107
108&mac {
109	status = "okay";
110	pinctrl-0 = <&eth_ref_clk_pa1
111		     &eth_crs_dv_pa7
112		     &eth_rxd0_pc4
113		     &eth_rxd1_pc5
114		     &eth_tx_en_pg11
115		     &eth_txd0_pg13
116		     &eth_txd1_pb13>;
117	pinctrl-names = "default";
118	phy-connection-type = "rmii";
119};
120
121&mdio {
122	status = "okay";
123	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
124	pinctrl-names = "default";
125
126	ethernet-phy@0 {
127		compatible = "ethernet-phy";
128		reg = <0x00>;
129		status = "okay";
130	};
131};
132
133&rng {
134	status = "okay";
135};
136
137&spi1 {
138	pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pb5>;
139	pinctrl-names = "default";
140	cs-gpios = <&gpiod 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
141	status = "okay";
142};
143
144zephyr_udc0: &usbotg_fs {
145	pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
146	pinctrl-names = "default";
147	status = "okay";
148};
149
150&fdcan1 {
151	pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_pd1>;
152	/* HSE will be used by default. Uncomment below to enable APB1.2 120MHz clock */
153	/*
154	 * clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
155	 *	   <&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>;
156	 */
157	pinctrl-names = "default";
158	status = "okay";
159};
160