1/*
2 * Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <st/h7/stm32h755Xi_m7.dtsi>
9#include "nucleo_h755zi_q.dtsi"
10
11/*
12 * WARNING:
13 * Possible pin conflicts: The pins PA2 and PB13 may conflict on selection of
14 * ETH_STM32_HAL, since they are used in ST Zio or ST morpho connectors. To
15 * avoid conflicting states the jumpers JP6 and JP7 must be in ON state.
16 */
17
18/ {
19	model = "STMicroelectronics STM32H755ZI-Q-NUCLEO board";
20	compatible = "st,stm32h755zi-q-nucleo";
21
22	/* HW resources belonging to CM7 */
23	chosen {
24		zephyr,console = &usart3;
25		zephyr,shell-uart = &usart3;
26		zephyr,dtcm = &dtcm;
27		zephyr,sram = &sram0;
28		zephyr,flash = &flash0;
29	};
30
31	pwmleds {
32		compatible = "pwm-leds";
33
34		red_pwm_led: red_pwm_led {
35			pwms = <&pwm12 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
36			label = "User LD3 - PWM12";
37		};
38	};
39
40	aliases {
41		led0 = &green_led;
42		pwm-led0 = &red_pwm_led;
43		sw0 = &user_button;
44	};
45};
46
47&clk_lsi {
48	status = "okay";
49};
50
51&clk_hsi48 {
52	status = "okay";
53};
54
55&clk_hse {
56	hse-bypass;
57	clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
58	status = "okay";
59};
60
61&pll {
62	div-m = <1>;
63	mul-n = <120>;
64	div-p = <2>;
65	div-q = <8>;
66	div-r = <2>;
67	clocks = <&clk_hse>;
68	status = "okay";
69};
70
71&rcc {
72	clocks = <&pll>;
73	clock-frequency = <DT_FREQ_M(480)>;
74};
75
76&usart3 {
77	pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
78	pinctrl-names = "default";
79	current-speed = <115200>;
80	status = "okay";
81};
82
83&rtc {
84	clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>,
85		 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
86	status = "okay";
87};
88
89&i2c1 {
90	pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
91	pinctrl-names = "default";
92	status = "okay";
93	clock-frequency = <I2C_BITRATE_FAST>;
94};
95
96&timers12 {
97	st,prescaler = <10000>;
98	status = "okay";
99
100	pwm12: pwm {
101		status = "okay";
102		pinctrl-0 = <&tim12_ch1_pb14>;
103		pinctrl-names = "default";
104	};
105};
106
107&mac {
108	status = "okay";
109	pinctrl-0 = <&eth_ref_clk_pa1
110		     &eth_crs_dv_pa7
111		     &eth_rxd0_pc4
112		     &eth_rxd1_pc5
113		     &eth_tx_en_pg11
114		     &eth_txd0_pg13
115		     &eth_txd1_pb13>;
116	pinctrl-names = "default";
117	phy-connection-type = "rmii";
118};
119
120&mdio {
121	status = "okay";
122	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
123	pinctrl-names = "default";
124
125	ethernet-phy@0 {
126		compatible = "ethernet-phy";
127		reg = <0x00>;
128		status = "okay";
129	};
130};
131
132&rng {
133	status = "okay";
134};
135
136zephyr_udc0: &usbotg_fs {
137	pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
138	pinctrl-names = "default";
139	status = "okay";
140};
141