1 /*
2  * Copyright (c) 2014-2015 Wind River Systems, Inc.
3  * Copyright (c) 2016, Freescale Semiconductor, Inc.
4  * Copyright (c) 2018 Prevas A/S
5  * Copyright (c) 2019 Thomas Burdick <thomas.burdick@gmail.com>
6  *
7  * SPDX-License-Identifier: Apache-2.0
8  */
9 
10 /**
11  * @file
12  * @brief System/hardware module for fsl_frdm_k22f platform
13  *
14  * This module provides routines to initialize and support board-level
15  * hardware for the fsl_frdm_k22f platform.
16  */
17 
18 #include <zephyr/kernel.h>
19 #include <zephyr/device.h>
20 #include <zephyr/init.h>
21 #include <soc.h>
22 #include <zephyr/drivers/uart.h>
23 #include <fsl_common.h>
24 #include <fsl_clock.h>
25 #include <zephyr/arch/cpu.h>
26 #include <cmsis_core.h>
27 
28 #define TIMESRC_OSCERCLK        (2)
29 
30 #define CLOCK_NODEID(clk) \
31 	DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
32 
33 #define CLOCK_DIVIDER(clk) \
34 	DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
35 
36 static const osc_config_t oscConfig = {
37 	.freq = CONFIG_OSC_XTAL0_FREQ,
38 	.capLoad = 0,
39 
40 #if defined(CONFIG_OSC_EXTERNAL)
41 	.workMode = kOSC_ModeExt,
42 #elif defined(CONFIG_OSC_LOW_POWER)
43 	.workMode = kOSC_ModeOscLowPower,
44 #elif defined(CONFIG_OSC_HIGH_GAIN)
45 	.workMode = kOSC_ModeOscHighGain,
46 #else
47 #error "An oscillator mode must be defined"
48 #endif
49 
50 	.oscerConfig = {
51 		.enableMode = 0U, /* Disable external reference clock */
52 #if FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER
53 		.erclkDiv = 0U,
54 #endif
55 	},
56 };
57 
58 static const mcg_pll_config_t pll0Config = {
59 	.enableMode = 0U,
60 	.prdiv = CONFIG_MCG_PRDIV0,
61 	.vdiv = CONFIG_MCG_VDIV0,
62 };
63 
64 static const sim_clock_config_t simConfig = {
65 	.pllFllSel = DT_PROP(DT_INST(0, nxp_kinetis_sim), pllfll_select),
66 	.er32kSrc = DT_PROP(DT_INST(0, nxp_kinetis_sim), er32k_select),
67 	.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
68 		   SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |
69 		   SIM_CLKDIV1_OUTDIV3(CLOCK_DIVIDER(flexbus_clk)) |
70 		   SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
71 };
72 
73 /**
74  *
75  * @brief Initialize the system clock
76  *
77  * This routine will configure the multipurpose clock generator (MCG) to
78  * set up the system clock.
79  * The MCG has nine possible modes, including Stop mode.  This routine assumes
80  * that the current MCG mode is FLL Engaged Internal (FEI), as from reset.
81  * It transitions through the FLL Bypassed External (FBE) and
82  * PLL Bypassed External (PBE) modes to get to the desired
83  * PLL Engaged External (PEE) mode and generate the maximum 120 MHz system
84  * clock.
85  *
86  */
clock_init(void)87 static ALWAYS_INLINE void clock_init(void)
88 {
89 	CLOCK_SetSimSafeDivs();
90 
91 	CLOCK_InitOsc0(&oscConfig);
92 	CLOCK_SetXtal0Freq(CONFIG_OSC_XTAL0_FREQ);
93 
94 
95 	CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow,
96 				      CONFIG_MCG_FCRDIV);
97 
98 	/* Configure FLL external reference divider (FRDIV). */
99 	CLOCK_SetFllExtRefDiv(0);
100 
101 	CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
102 
103 	CLOCK_SetSimConfig(&simConfig);
104 
105 #if CONFIG_USB_KINETIS || CONFIG_UDC_KINETIS
106 	CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0,
107 				CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
108 #endif
109 }
110 
111 /**
112  *
113  * @brief Perform basic hardware initialization
114  *
115  * Initialize the interrupt controller device drivers.
116  * Also initialize the timer device driver, if required.
117  *
118  * @return 0
119  */
120 
soc_early_init_hook(void)121 void soc_early_init_hook(void)
122 {
123 	/* release I/O power hold to allow normal run state */
124 	PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
125 
126 	/* Initialize PLL/system clock to 120 MHz */
127 	clock_init();
128 }
129 
130 #ifdef CONFIG_SOC_RESET_HOOK
131 
soc_reset_hook(void)132 void soc_reset_hook(void)
133 {
134 	SystemInit();
135 }
136 
137 #endif /* CONFIG_SOC_RESET_HOOK */
138