Searched +full:0 +full:x30000 (Results 1 – 25 of 27) sorted by relevance
12
| /Zephyr-latest/samples/subsys/fs/fs_sample/boards/ |
| D | stm32f746g_disco_dma.overlay | 8 dmas = <&dma2 6 4 0x30000 0x00>, <&dma2 3 4 0x30000 0x00>;
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| /Zephyr-latest/tests/subsys/mgmt/mcumgr/img_mgmt_slot_info/boards/ |
| D | nrf52840dk_nrf52840_dual_slot.overlay | 17 boot_partition: partition@0 {
19 reg = <0x00000000 0x10000>;
22 label = "image-0";
23 reg = <0x00010000 0x40000>;
27 reg = <0x00050000 0x40000>;
31 reg = <0x00090000 0x30000>;
35 reg = <0x000c0000 0x30000>;
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| D | nrf5340dk_nrf5340_cpuapp_dual_slot.overlay | 19 boot_partition: partition@0 {
21 reg = <0x00000000 0x10000>;
24 label = "image-0";
25 reg = <0x00010000 0x40000>;
29 reg = <0x00050000 0x40000>;
33 reg = <0x00090000 0x30000>;
37 reg = <0x000c0000 0x30000>;
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| /Zephyr-latest/dts/common/nordic/ |
| D | nrf5340_cpuapp_partition.dtsi | 14 * 0x0000_0000 BL2 - MCUBoot (64 KB)
15 * 0x0001_0000 Primary image area (448 KB):
16 * 0x0001_0000 Secure image primary (256 KB)
17 * 0x0005_0000 Non-secure image primary (192 KB)
18 * 0x0008_0000 Secondary image area (448 KB):
19 * 0x0008_0000 Secure image secondary (256 KB)
20 * 0x000c_0000 Non-secure image secondary (192 KB)
21 * 0x000f_0000 Protected Storage Area (16 KB)
22 * 0x000f_4000 Internal Trusted Storage Area (8 KB)
23 * 0x000f_6000 OTP / NV counters area (8 KB)
[all …]
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| D | nrf91xx_partition.dtsi | 14 * 0x0000_0000 BL2 - MCUBoot (64 KB)
15 * 0x0001_0000 Primary image area (448 KB):
16 * 0x0001_0000 Secure image primary (256 KB)
17 * 0x0005_0000 Non-secure image primary (192 KB)
18 * 0x0008_0000 Secondary image area (448 KB):
19 * 0x0008_0000 Secure image secondary (256 KB)
20 * 0x000c_0000 Non-secure image secondary (192 KB)
21 * 0x000f_0000 Protected Storage Area (16 KB)
22 * 0x000f_4000 Internal Trusted Storage Area (8 KB)
23 * 0x000f_6000 OTP / NV counters area (8 KB)
[all …]
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| /Zephyr-latest/dts/bindings/mmc/ |
| D | st,stm32-sdmmc.yaml | 17 pinctrl-0:
44 default: 0
66 dmas = <&dma2 4 6 0x30000 0x00>, <&dma2 4 3 0x30000 0x00>;
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| /Zephyr-latest/boards/mikroe/mini_m4_for_stm32/support/ |
| D | openocd.cfg | 3 set WORKAREASIZE 0x30000
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| /Zephyr-latest/tests/drivers/flash/common/boards/ |
| D | max32662evkit.overlay | 13 code_partition: partition@0 {
14 reg = <0x0 DT_SIZE_K(192)>;
20 reg = <0x30000 DT_SIZE_K(64)>;
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| /Zephyr-latest/dts/arm/broadcom/ |
| D | valkyrie.dtsi | 12 #size-cells = <0>;
14 cpu@0 {
17 reg = <0>;
23 reg = <0xe000ed90 0x40>;
31 reg = <0x00400000 0x30000>;
36 reg = <0x40020000 0x400>;
45 reg = <0x48100000 0x400>;
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| /Zephyr-latest/boards/arduino/nicla_sense_me/ |
| D | arduino_nicla_sense_me.dts | 64 pinctrl-0 = <&uart0_default>;
73 pinctrl-0 = <&i2c0_default>;
79 reg = <0x53>;
95 pinctrl-0 = <&i2c1_default>;
105 pinctrl-0 = <&spi1_default>;
114 pinctrl-0 = <&spi2_default>;
119 mx25r1635f: mx25r1635f@0 {
121 reg = <0>;
134 logging_partition: partition@0 {
136 reg = <0x00000000 DT_SIZE_M(16)>;
[all …]
|
| /Zephyr-latest/boards/ezurio/bl5340_dvk/ |
| D | bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi | 26 reg = <0x00010000 0xa0000>;
30 reg = <0x000b0000 0x40000>;
34 reg = <0x00000000 0xa0000>;
38 reg = <0x000a0000 0x40000>;
49 reg = <0x20000000 DT_SIZE_K(448)>;
53 reg = <0x20000000 0x40000>;
57 reg = <0x20040000 0x30000>;
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| /Zephyr-latest/boards/infineon/cyw920829m2evk_02/ |
| D | cyw920829m2evk_02.dts | 39 pinctrl-0 = <&p3_3_scb2_uart_tx &p3_2_scb2_uart_rx &p3_1_scb2_uart_rts &p3_0_scb2_uart_cts>;
95 reg = <0x40890000 0x30000>;
101 reg = <0x08000000 DT_SIZE_K(512)>;
110 reg = <0x08000000 0x50>;
115 reg = <0x08000050 DT_SIZE_K(12)>;
119 reg = <0x08003050 0x6CFB0>; /* 435kb */
129 reg = <0x60000 DT_SIZE_K(64)>;
|
| /Zephyr-latest/drivers/ethernet/ |
| D | eth_w5500_priv.h | 18 #define W5500_COMMON_REGS 0x0000
19 #define W5500_MR 0x0000 /* Mode Register */
20 #define W5500_GW 0x0001
21 #define MR_RST 0x80 /* S/W reset */
22 #define MR_PB 0x10 /* Ping block */
23 #define MR_AI 0x02 /* Address Auto-Increment */
24 #define MR_IND 0x01 /* Indirect mode */
25 #define W5500_SHAR 0x0009 /* Source MAC address */
26 #define W5500_IR 0x0015 /* Interrupt Register */
27 #define W5500_COMMON_REGS_LEN 0x0040
[all …]
|
| /Zephyr-latest/dts/arm64/broadcom/ |
| D | bcm2712.dtsi | 13 #size-cells = <0>;
15 cpu@0 {
18 reg = <0>;
43 reg = <0x0 0x200000 0x80000>;
48 reg = <0x10 0x7fff9000 0x1000>,
49 <0x10 0x7fffa000 0x2000>;
57 reg = <0x10 0x7d517c00 0x40>;
60 #size-cells = <0>;
61 gio_aon: gpio@0 {
63 reg = <0>;
[all …]
|
| /Zephyr-latest/boards/panasonic/pan1781_evb/ |
| D | pan1781_evb.dts | 43 pwms = <&sw_pwm 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
64 gpio-map-mask = <0xffffffff 0xffffffc0>;
65 gpio-map-pass-thru = <0 0x3f>;
66 gpio-map = <0 0 &gpio0 2 0>, /* A0 */
67 <1 0 &gpio0 3 0>, /* A1 */
68 <2 0 &gpio0 4 0>, /* A2 */
69 <3 0 &gpio0 5 0>, /* A3 */
70 <6 0 &gpio0 6 0>, /* D0 */
71 <7 0 &gpio0 8 0>, /* D1 */
72 <8 0 &gpio0 14 0>, /* D2 */
[all …]
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| /Zephyr-latest/drivers/dai/intel/ssp/ |
| D | ssp.h | 10 #define SSP_IP_VER_1_0 0x10000 /* cAVS */
11 #define SSP_IP_VER_1_5 0x10500 /* ACE15 */
12 #define SSP_IP_VER_2_0 0x20000 /* ACE20 */
13 #define SSP_IP_VER_3_0 0x30000 /* ACE30 */
42 #define DAI_INTEL_SSP_IS_BIT_SET(reg, bit) (((reg >> bit) & (0x1)) != 0)
65 #define DAI_INTEL_SSP_CLOCK_XTAL_OSCILLATOR 0x0
66 #define DAI_INTEL_SSP_CLOCK_AUDIO_CARDINAL 0x1
67 #define DAI_INTEL_SSP_CLOCK_PLL_FIXED 0x2
92 MN_BCLK_SOURCE_NONE = 0, /**< port is not using any clock */
|
| /Zephyr-latest/boards/shields/mikroe_wifi_bt_click/doc/ |
| D | index.rst | 46 compatible with ESP32 AT Bin 2.0.0, after getting the binary from Espressif
60 0x10000 ota_data_initial.bin \
61 0x1000 bootloader/bootloader.bin \
62 0x20000 at_customize.bin \
63 0x21000 customized_partitions/ble_data.bin \
64 0x24000 customized_partitions/server_cert.bin \
65 0x26000 customized_partitions/server_key.bin \
66 0x28000 customized_partitions/server_ca.bin \
67 0x2a000 customized_partitions/client_cert.bin \
68 0x2c000 customized_partitions/client_key.bin \
[all …]
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| /Zephyr-latest/include/zephyr/arch/nios2/ |
| D | nios2.h | 69 __asm__("mov %0, et" : "=r" (et)); in _nios2_read_et()
82 __asm__("mov %0, sp" : "=r" (sp)); in _nios2_read_sp()
104 __asm__ volatile ("flushda (%0)" :: "r" (addr)); in _nios2_dcache_addr_flush()
109 __asm__ volatile ("flushd (%0)" :: "r" (offset)); in z_nios2_dcache_flush()
114 __asm__ volatile ("flushi %0" :: "r" (offset)); in z_nios2_icache_flush()
127 NIOS2_CR_STATUS = 0,
147 * we get errors "Control register number must be in range 0-31 for
201 #define NIOS2_STATUS_PIE_MSK (0x00000001)
202 #define NIOS2_STATUS_PIE_OFST (0)
203 #define NIOS2_STATUS_U_MSK (0x00000002)
[all …]
|
| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_mcxw71.dtsi | 27 #size-cells = <0>;
29 cpu0: cpu@0 {
31 reg = <0>;
37 reg = <0xe000ed90 0x40>;
44 ranges = <0x0 0x10000000 DT_SIZE_M(1)>;
48 reg = <0x50020000 0x1000>;
49 interrupts = <27 0>;
52 flash: flash@0 {
53 reg = <0x0 DT_SIZE_M(1)>;
61 ranges = <0x0 0x14000000 DT_SIZE_K(16)>;
[all …]
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| D | nxp_rt6xx_common.dtsi | 23 #size-cells = <0>;
25 cpu0: cpu@0 {
27 reg = <0>;
34 reg = <0xe000ed90 0x40>;
62 * Note that the sram code region starts at an offset of 0x1B000,
63 * as the boot ROM will not load code before 0x1C000. The first
64 * 0x1000 of the image will contain the boot header.
68 reg = <0x1b000 DT_SIZE_K(1428)>;
73 reg = <0x180000 DT_SIZE_K(3072)>;
78 reg = <0x40140000 DT_SIZE_K(16)>;
[all …]
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| D | nxp_rt5xx_common.dtsi | 25 #size-cells = <0>;
27 cpu0: cpu@0 {
29 reg = <0>;
36 reg = <0xe000ed90 0x40>;
45 min-residency-us = <0>;
46 exit-latency-us = <0>;
60 deep-sleep-config = <0xC800>,
61 <0x80000004>,
62 <0xFFFFFFFF>,
63 <0>;
[all …]
|
| /Zephyr-latest/boards/phytec/phyboard_nash/doc/ |
| D | index.rst | 118 …fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0xd0…
147 load mmc 1:1 0x80000000 zephyr.bin;cp.b 0x80000000 0x201e0000 0x30000;bootaux 0x1ffe0000 0
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| /Zephyr-latest/dts/riscv/openisa/ |
| D | rv32m1.dtsi | 22 #size-cells = <0>;
23 cpu@0 {
27 reg = <0>;
40 reg = <0x20000000 0x30000>;
45 reg = <0x09000000 0x20000>;
62 reg = <0x4002b000 0x200>;
68 reg = <0x41027000 0x200>;
74 #address-cells = <0>;
77 reg = <0xe0041000 0x88>;
82 #address-cells = <0>;
[all …]
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| /Zephyr-latest/dts/arm/nordic/ |
| D | nrf5340_cpuapp_peripherals.dtsi | 9 dcnf: dcnf@0 {
11 reg = <0x0 0x1000>;
17 reg = <0x4000 0x1000>;
21 #clock-cells = <0>;
27 #clock-cells = <0>;
34 reg = <0x4000 0x1000>;
41 reg = <0x4704 0x1>;
49 reg = <0x4904 0x1>;
57 reg = <0x4b00 0x44>;
65 reg = <0x5000 0x1000>;
[all …]
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| /Zephyr-latest/boards/nxp/imx93_evk/doc/ |
| D | index.rst | 168 "uboot_v2023.04-2.9.0" branch is U-Boot v2023.04 used in Real-Time Edge Software release
184 fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; cpu 1 release 0xd0000000
191 fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; go 0xd0000000
209 thread_a: Hello World from cpu 0 on imx93_evk!
210 thread_b: Hello World from cpu 0 on imx93_evk!
211 thread_a: Hello World from cpu 0 on imx93_evk!
212 thread_b: Hello World from cpu 0 on imx93_evk!
248 load mmc 1:1 0x80000000 zephyr.bin;cp.b 0x80000000 0x201e0000 0x30000;bootaux 0x1ffe0000 0
255 load mmc 1:1 0x84000000 zephyr.bin;dcache flush;bootaux 0x84000000 0
278 thread_a: Hello World from cpu 0 on imx93_evk!
[all …]
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