Lines Matching +full:0 +full:x30000

27 		#size-cells = <0>;
29 		cpu0: cpu@0 {
31 			reg = <0>;
37 				reg = <0xe000ed90 0x40>;
44 			ranges = <0x0 0x10000000 DT_SIZE_M(1)>;
48 			reg = <0x50020000 0x1000>;
49 			interrupts = <27 0>;
52 			flash: flash@0 {
53 				reg = <0x0 DT_SIZE_M(1)>;
61 			ranges = <0x0 0x14000000 DT_SIZE_K(16)>;
65 			ctcm0: code_memory@0 {
67 				reg = <0x0 DT_SIZE_K(16)>;
72 			ranges = <0x0 0x30000000 DT_SIZE_K(112)>;
76 			stcm0: system_memory@0 {
79 				reg = <0x0 DT_SIZE_K(104)>;
84 				reg = <0x1a000 DT_SIZE_K(8)>;
90 			ranges = <0x0 0x489c0000 DT_SIZE_K(40)>;
94 			ranges = <0x0 0x50000000 0x10000000>;
98 			pbridge2: pbridge2@0 {
100 				reg = <0x0 0x4b000>;
108 				ranges = <0x0 0x8000000 0x40000>;
114 				ranges = <0x0 0x8800000 0x210000>;
134 		reg = <0x8800 DT_SIZE_K(6)>;
146 		reg = <0x1e000 0x404>;
152 		reg = <0x42000 0xe0>;
153 		clocks = <&scg SCG_K4_SLOW_CLK 0x108>;
158 		reg = <0x43000 0xe0>;
159 		clocks = <&scg SCG_K4_SLOW_CLK 0x10c>;
164 		reg = <0x44000 0xe0>;
165 		clocks = <&scg SCG_K4_SLOW_CLK 0x110>;
170 		reg = <0x45000 0xe0>;
171 		clocks = <&scg SCG_K4_SLOW_CLK 0>;
176 		reg = <0x38000 0x34>;
177 		interrupts = <44 0>;
178 		clocks = <&scg SCG_K4_FIRC_CLK 0xe0>;
184 		reg = <0x39000 0x34>;
185 		interrupts = <45 0>;
186 		clocks = <&scg SCG_K4_FIRC_CLK 0xe4>;
194 		#size-cells = <0>;
195 		reg = <0x33000 0x200>;
196 		interrupts = <39 0>;
197 		clocks = <&scg SCG_K4_FIRC_CLK 0xe0>;
205 		#size-cells = <0>;
206 		reg = <0x34000 0x200>;
207 		interrupts = <40 0>;
208 		clocks = <&scg SCG_K4_FIRC_CLK 0xe4>;
214 		reg = <0x36000 0x800>;
215 		interrupts = <42 0>;
216 		clocks = <&scg SCG_K4_FIRC_CLK 0xd8>;
218 		#size-cells = <0>;
224 		reg = <0x37000 0x800>;
225 		interrupts = <43 0>;
226 		clocks = <&scg SCG_K4_FIRC_CLK 0xdc>;
228 		#size-cells = <0>;
238 		reg = <0x46000 0x128>;
239 		interrupts = <65 0>, <66 0>;
243 		reg = <0x2b000 0x400>;
244 		interrupts = <74 0>;
249 		reg = <0x31000 0x100>;
250 		interrupts = <37 0>;
251 		clocks = <&scg SCG_K4_FIRC_CLK 0xc4>;
259 		reg = <0x32000 0x100>;
260 		interrupts = <38 0>;
261 		clocks = <&scg SCG_K4_FIRC_CLK 0xc8>;
269 		reg = <0x1a000 16>;
270 		interrupts = <23 0>;
271 		clocks = <&scg SCG_K4_SYSOSC_CLK 0x68>;
279 		reg = <0x1b000 16>;
280 		interrupts = <24 0>;
281 		clocks = <&scg SCG_K4_SYSOSC_CLK 0x6c>;
289 		reg = <0x2d000 0x10>;
290 		interrupts = <34 0>;
300 		reg = <0x2e000 0x10>;
301 		interrupts = <35 0>;
321 		reg = <0x3b000 0x3080>;
322 		interrupts = <47 0>;
324 		clocks = <&scg SCG_K4_FIRC_CLK 0xec>;
331 		reg = <0x47000 0x1000>;
332 		interrupts = <71 0>;
333 		clocks = <&scg SCG_K4_FIRC_CLK 0x11c>;
336 		/* pwrlvl 0 is slow speed low power, 1 is opposite */
337 		power-level = <0>;
338 		offset-value-a = <0>;
339 		offset-value-b = <0>;
348 		reg = <0x4a000 0x20>;
366 		reg = <0x10000 0x128>;
367 		interrupts = <59 0>, <60 0>;
376 		reg = <0x20000 0x128>;
377 		interrupts = <61 0>, <62 0>;
386 		reg = <0x30000 0x128>;
387 		interrupts = <63 0>, <64 0>;