1 /* W5500 Stand-alone Ethernet Controller with SPI 2 * 3 * Copyright (c) 2020 Linumiz 4 * Author: Parthiban Nallathambi <parthiban@linumiz.com> 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9 #include <zephyr/drivers/gpio.h> 10 #include <zephyr/drivers/spi.h> 11 12 #ifndef _W5500_ 13 #define _W5500_ 14 15 /* 16 * W5500 common registers 17 */ 18 #define W5500_COMMON_REGS 0x0000 19 #define W5500_MR 0x0000 /* Mode Register */ 20 #define W5500_GW 0x0001 21 #define MR_RST 0x80 /* S/W reset */ 22 #define MR_PB 0x10 /* Ping block */ 23 #define MR_AI 0x02 /* Address Auto-Increment */ 24 #define MR_IND 0x01 /* Indirect mode */ 25 #define W5500_SHAR 0x0009 /* Source MAC address */ 26 #define W5500_IR 0x0015 /* Interrupt Register */ 27 #define W5500_COMMON_REGS_LEN 0x0040 28 #define W5500_PHYCFGR 0x002E /* PHY Configuration register */ 29 30 #define W5500_Sn_MR 0x0000 /* Sn Mode Register */ 31 #define W5500_Sn_CR 0x0001 /* Sn Command Register */ 32 #define W5500_Sn_IR 0x0002 /* Sn Interrupt Register */ 33 #define W5500_Sn_SR 0x0003 /* Sn Status Register */ 34 #define W5500_Sn_TX_FSR 0x0020 /* Sn Transmit free memory size */ 35 #define W5500_Sn_TX_RD 0x0022 /* Sn Transmit memory read pointer */ 36 #define W5500_Sn_TX_WR 0x0024 /* Sn Transmit memory write pointer */ 37 #define W5500_Sn_RX_RSR 0x0026 /* Sn Receive free memory size */ 38 #define W5500_Sn_RX_RD 0x0028 /* Sn Receive memory read pointer */ 39 40 #define W5500_S0_REGS 0x10000 41 42 #define W5500_S0_MR (W5500_S0_REGS + W5500_Sn_MR) 43 #define S0_MR_MACRAW 0x04 /* MAC RAW mode */ 44 #define S0_MR_MF 0x40 /* MAC Filter for W5500 */ 45 #define W5500_S0_CR (W5500_S0_REGS + W5500_Sn_CR) 46 #define S0_CR_OPEN 0x01 /* OPEN command */ 47 #define S0_CR_CLOSE 0x10 /* CLOSE command */ 48 #define S0_CR_SEND 0x20 /* SEND command */ 49 #define S0_CR_RECV 0x40 /* RECV command */ 50 #define W5500_S0_IR (W5500_S0_REGS + W5500_Sn_IR) 51 #define S0_IR_SENDOK 0x10 /* complete sending */ 52 #define S0_IR_RECV 0x04 /* receiving data */ 53 #define W5500_S0_SR (W5500_S0_REGS + W5500_Sn_SR) 54 #define S0_SR_MACRAW 0x42 /* mac raw mode */ 55 #define W5500_S0_TX_FSR (W5500_S0_REGS + W5500_Sn_TX_FSR) 56 #define W5500_S0_TX_RD (W5500_S0_REGS + W5500_Sn_TX_RD) 57 #define W5500_S0_TX_WR (W5500_S0_REGS + W5500_Sn_TX_WR) 58 #define W5500_S0_RX_RSR (W5500_S0_REGS + W5500_Sn_RX_RSR) 59 #define W5500_S0_RX_RD (W5500_S0_REGS + W5500_Sn_RX_RD) 60 #define W5500_S0_IMR (W5500_S0_REGS + W5500_Sn_IMR) 61 62 #define W5500_S0_MR_MF 7 /* MAC Filter for W5500 */ 63 #define W5500_Sn_REGS_LEN 0x0040 64 #define W5500_SIMR 0x0018 /* Socket Interrupt Mask Register */ 65 #define IR_S0 0x01 66 #define RTR_DEFAULT 2000 67 #define W5500_RTR 0x0019 /* Retry Time-value Register */ 68 69 70 #define W5500_Sn_RXMEM_SIZE(n) \ 71 (0x1001e + (n) * 0x40000) /* Sn RX Memory Size */ 72 #define W5500_Sn_TXMEM_SIZE(n) \ 73 (0x1001f + (n) * 0x40000) /* Sn TX Memory Size */ 74 75 #define W5500_Sn_TX_MEM_START 0x20000 76 #define W5500_TX_MEM_SIZE 0x04000 77 #define W5500_Sn_RX_MEM_START 0x30000 78 #define W5500_RX_MEM_SIZE 0x04000 79 80 /* Delay for PHY write/read operations (25.6 us) */ 81 #define W5500_PHY_ACCESS_DELAY 26U 82 struct w5500_config { 83 struct spi_dt_spec spi; 84 struct gpio_dt_spec interrupt; 85 struct gpio_dt_spec reset; 86 int32_t timeout; 87 }; 88 89 struct w5500_runtime { 90 struct net_if *iface; 91 92 K_KERNEL_STACK_MEMBER(thread_stack, 93 CONFIG_ETH_W5500_RX_THREAD_STACK_SIZE); 94 struct k_thread thread; 95 uint8_t mac_addr[6]; 96 struct gpio_callback gpio_cb; 97 struct k_sem tx_sem; 98 struct k_sem int_sem; 99 bool link_up; 100 uint8_t buf[NET_ETH_MAX_FRAME_SIZE]; 101 }; 102 103 #endif /*_W5500_*/ 104
