Lines Matching +full:0 +full:x30000
23 #size-cells = <0>;
25 cpu0: cpu@0 {
27 reg = <0>;
34 reg = <0xe000ed90 0x40>;
62 * Note that the sram code region starts at an offset of 0x1B000,
63 * as the boot ROM will not load code before 0x1C000. The first
64 * 0x1000 of the image will contain the boot header.
68 reg = <0x1b000 DT_SIZE_K(1428)>;
73 reg = <0x180000 DT_SIZE_K(3072)>;
78 reg = <0x40140000 DT_SIZE_K(16)>;
98 * addresses differ between non-secure (0x40000000) and secure
99 * modes (0x50000000).
103 reg = <0x134000 0x1000>, <0x18000000 DT_SIZE_M(128)>;
109 reg = <0x1000 0x1000>;
115 reg = <0x4000 0x1000>;
124 reg = <0x21000 0x1000>;
128 rstctl0: reset@0 {
130 reg = <0x0 0x80>;
136 reg = <0x20000 0x80>;
142 reg = <0x2f50 0x10>;
147 reg = <0x100000 0x2784>;
149 #size-cells = <0>;
151 gpio0: gpio@0 {
156 reg = <0>;
198 reg = <0x25000 0x1000>;
201 #address-cells = <0>;
210 reg = <0x106000 0x1000>;
211 interrupts = <14 0>;
213 resets = <&rstctl1 NXP_SYSCON_RESET(0, 8)>;
219 reg = <0x107000 0x1000>;
220 interrupts = <15 0>;
222 resets = <&rstctl1 NXP_SYSCON_RESET(0, 9)>;
228 reg = <0x108000 0x1000>;
229 interrupts = <16 0>;
231 resets = <&rstctl1 NXP_SYSCON_RESET(0, 10)>;
237 reg = <0x109000 0x1000>;
238 interrupts = <17 0>;
240 resets = <&rstctl1 NXP_SYSCON_RESET(0, 11)>;
246 reg = <0x122000 0x1000>;
247 interrupts = <18 0>;
249 resets = <&rstctl1 NXP_SYSCON_RESET(0, 12)>;
255 reg = <0x123000 0x1000>;
256 interrupts = <19 0>;
258 resets = <&rstctl1 NXP_SYSCON_RESET(0, 13)>;
264 reg = <0x124000 0x1000>;
265 interrupts = <43 0>;
267 resets = <&rstctl1 NXP_SYSCON_RESET(0, 14)>;
273 reg = <0x125000 0x1000>;
274 interrupts = <44 0>;
276 resets = <&rstctl1 NXP_SYSCON_RESET(0, 15)>;
282 reg = <0x127000 0x1000>;
283 interrupts = <21 0>;
285 resets = <&rstctl1 NXP_SYSCON_RESET(0, 23)>;
291 reg = <0x144000 0x1000>;
299 reg = <0x13b000 0x1000>;
311 reg = <0x126000 0x1000>;
312 interrupts = <20 0>;
314 resets = <&rstctl1 NXP_SYSCON_RESET(0, 22)>;
317 #size-cells = <0>;
322 reg = <0x104000 0x1000>;
323 interrupts = <1 0>;
331 reg = <0x105000 0x1000>;
332 interrupts = <54 0>;
340 #size-cells = <0>;
342 reg = <0x121000 0x1000>;
343 interrupts = <25 0>;
347 pdmc0: dmic-channel@0 {
349 reg = <0>;
406 reg = <0x113000 0x1000>;
407 interrupts = <41 0>;
413 reg = <0x30000 0x1000>;
414 interrupts = <32 0>;
424 reg = <0x138000 0x1000>;
426 interrupts = <31 0>;
431 reg = <0x146000 0x1000>;
432 interrupts = <12 0>;
441 reg = <0xe000 0x1000>;
442 interrupts = <0 0>;
449 reg = <0x2e000 0x1000>;
450 interrupts = <52 0>;
457 reg = <0x136000 0x1000>;
459 interrupts = <45 0>;
469 reg = <0x137000 0x1000>;
471 interrupts = <46 0>;
481 reg = <0x13a000 0x304>;
482 interrupts = <22 0>;
485 clk-source = <0>;
488 power-level = <0>;
497 reg = <0x28000 0x1000>;
498 interrupts = <10 0>;
502 mode = <0>;
503 input = <0>;
504 prescale = <0>;
509 reg = <0x29000 0x1000>;
510 interrupts = <11 0>;
514 mode = <0>;
515 input = <0>;
516 prescale = <0>;
521 reg = <0x2a000 0x1000>;
522 interrupts = <39 0>;
526 mode = <0>;
527 input = <0>;
528 prescale = <0>;
533 reg = <0x2b000 0x1000>;
534 interrupts = <13 0>;
538 mode = <0>;
539 input = <0>;
540 prescale = <0>;
545 reg = <0x2c000 0x1000>;
546 interrupts = <40 0>;
550 mode = <0>;
551 input = <0>;
552 prescale = <0>;
557 reg = <0x36000 0x1000>;
558 interrupts = <49 0>;
565 #size-cells = <0>;
570 reg = <0x2d000 0x100>;
571 interrupts = <9 0>;
577 #size-cells = <0>;
579 mrt_channel0: mrt_channel@0 {
581 reg = <0>;
604 interrupts = <42 0>;
606 #size-cells = <0>;