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/Zephyr-latest/doc/connectivity/networking/
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/Zephyr-latest/soc/nxp/s32/s32k3/
Dpmc.c13 #define PMC_LVSC 0x0
14 #define PMC_LVSC_HVDAF_MASK BIT(0)
15 #define PMC_LVSC_HVDAF(v) FIELD_PREP(PMC_LVSC_HVDAF_MASK, (v)) argument
17 #define PMC_LVSC_HVDBF(v) FIELD_PREP(PMC_LVSC_HVDBF_MASK, (v)) argument
19 #define PMC_LVSC_HVD25F(v) FIELD_PREP(PMC_LVSC_HVD25F_MASK, (v)) argument
21 #define PMC_LVSC_HVD11F(v) FIELD_PREP(PMC_LVSC_HVD11F_MASK, (v)) argument
23 #define PMC_LVSC_LVD5AF(v) FIELD_PREP(PMC_LVSC_LVD5AF_MASK, (v)) argument
25 #define PMC_LVSC_LVD15F(v) FIELD_PREP(PMC_LVSC_LVD15F_MASK, (v)) argument
27 #define PMC_LVSC_HVDAS(v) FIELD_PREP(PMC_LVSC_HVDAS_MASK, (v)) argument
29 #define PMC_LVSC_HVDBS(v) FIELD_PREP(PMC_LVSC_HVDBS_MASK, (v)) argument
[all …]
Dpinctrl_soc.h16 #define SIUL2_MSCR_SSS_MASK GENMASK(3, 0)
17 #define SIUL2_MSCR_SSS(v) FIELD_PREP(SIUL2_MSCR_SSS_MASK, (v)) argument
19 #define SIUL2_MSCR_SMC(v) FIELD_PREP(SIUL2_MSCR_SMC_MASK, (v)) argument
21 #define SIUL2_MSCR_IFE(v) FIELD_PREP(SIUL2_MSCR_IFE_MASK, (v)) argument
23 #define SIUL2_MSCR_DSE(v) FIELD_PREP(SIUL2_MSCR_DSE_MASK, (v)) argument
25 #define SIUL2_MSCR_PUS(v) FIELD_PREP(SIUL2_MSCR_PUS_MASK, (v)) argument
27 #define SIUL2_MSCR_PUE(v) FIELD_PREP(SIUL2_MSCR_PUE_MASK, (v)) argument
29 #define SIUL2_MSCR_SRC(v) FIELD_PREP(SIUL2_MSCR_SRC_MASK, (v)) argument
31 #define SIUL2_MSCR_PKE(v) FIELD_PREP(SIUL2_MSCR_PKE_MASK, (v)) argument
33 #define SIUL2_MSCR_INV(v) FIELD_PREP(SIUL2_MSCR_INV_MASK, (v)) argument
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/Zephyr-latest/boards/native/doc/
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/Zephyr-latest/samples/subsys/sip_svc/
DREADME.rst31 at address 0x00100000 and ATF BL31 at 0x00001000 from SD Card or QSPI Flash
39 Got response of transaction id 0x00 and voltage is 0.846878v
40 Got response of transaction id 0x01 and voltage is 0.858170v
41 Got response of transaction id 0x02 and voltage is 0.860168v
42 Got response of transaction id 0x03 and voltage is 0.846832v
43 Got response of transaction id 0x04 and voltage is 0.858337v
44 Got response of transaction id 0x05 and voltage is 0.871704v
45 Got response of transaction id 0x06 and voltage is 0.859421v
46 Got response of transaction id 0x07 and voltage is 0.857254v
47 Got response of transaction id 0x08 and voltage is 0.858429v
[all …]
/Zephyr-latest/soc/nxp/s32/common/
Dmc_me.c15 #define MC_ME_CTL_KEY 0x0
16 #define MC_ME_CTL_KEY_KEY_MASK GENMASK(15, 0)
17 #define MC_ME_CTL_KEY_KEY(v) FIELD_PREP(MC_ME_CTL_KEY_KEY_MASK, (v)) argument
19 #define MC_ME_MODE_CONF 0x4
20 #define MC_ME_MODE_CONF_DEST_RST_MASK BIT(0)
21 #define MC_ME_MODE_CONF_DEST_RST(v) FIELD_PREP(MC_ME_MODE_CONF_DEST_RST_MASK, (v)) argument
23 #define MC_ME_MODE_CONF_FUNC_RST(v) FIELD_PREP(MC_ME_MODE_CONF_FUNC_RST_MASK, (v)) argument
25 #define MC_ME_MODE_CONF_STANDBY(v) FIELD_PREP(MC_ME_MODE_CONF_STANDBY_MASK, (v)) argument
27 #define MC_ME_MODE_UPD 0x8
28 #define MC_ME_MODE_UPD_MODE_UPD_MASK BIT(0)
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Dmc_rgm.c13 #define MC_RGM_DES 0x0
14 #define MC_RGM_DES_F_POR_MASK BIT(0)
15 #define MC_RGM_DES_F_POR(v) FIELD_PREP(MC_RGM_DES_F_POR_MASK, (v)) argument
17 #define MC_RGM_FES 0x8
18 #define MC_RGM_FES_F_EXR_MASK BIT(0)
19 #define MC_RGM_FES_F_EXR(v) FIELD_PREP(MC_RGM_FES_F_EXR_MASK, (v)) argument
21 #define MC_RGM_FERD 0xc
23 #define MC_RGM_FBRE 0x10
25 #define MC_RGM_FREC 0x14
26 #define MC_RGM_FREC_FREC_MASK GENMASK(3, 0)
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/Zephyr-latest/drivers/sensor/tdk/icm42605/
Dicm42605_setup.c48 return 0; in icm42605_set_fs()
105 LOG_DBG("Write Accel ODR 0x%X", databuf); in icm42605_set_odr()
137 LOG_DBG("Write GYRO ODR 0x%X", databuf); in icm42605_set_odr()
150 int result = 0; in icm42605_sensor_init()
151 uint8_t v; in icm42605_sensor_init() local
153 result = inv_spi_read(&cfg->spi, REG_WHO_AM_I, &v, 1); in icm42605_sensor_init()
159 LOG_DBG("WHO AM I : 0x%X", v); in icm42605_sensor_init()
161 result = inv_spi_read(&cfg->spi, REG_DEVICE_CONFIG, &v, 1); in icm42605_sensor_init()
168 v |= BIT_SOFT_RESET; in icm42605_sensor_init()
170 result = inv_spi_single_write(&cfg->spi, REG_DEVICE_CONFIG, &v); in icm42605_sensor_init()
[all …]
/Zephyr-latest/include/zephyr/arch/arc/asm-compat/
Dasm-macro-64-bit-gnu.h17 .macro LDR\aa d, s, off=0
23 .macro STR\aa d, s, off=0
24 ; workaround assembler barfing for ST r, [@symb, 0]
25 .if \off == 0
33 .macro STR d, s, off=0
34 .if \off == 0
62 .macro ADDR\cc d, s, v
63 addl\cc \d, \s, \v
68 .macro ADD2R\cc d, s, v
69 add2l\cc \d, \s, \v
[all …]
Dasm-macro-32-bit-gnu.h17 .macro LDR\aa d, s, off=0
23 .macro STR\aa d, s, off=0
24 ; workaround assembler barfing for ST r, [@symb, 0]
25 .if \off == 0
50 .macro ADDR\cc d, s, v
51 add\cc \d, \s, \v
56 .macro ADD2R\cc d, s, v
57 add2\cc \d, \s, \v
61 .macro ADD3R d, s, v
62 add3 \d, \s, \v
[all …]
/Zephyr-latest/scripts/coccinelle/
Dsame_identifier.cocci16 identifier t, v;
19 struct t *v@p;
21 struct t v@p;
23 union t v@p;
28 v << common_case.v;
32 msg = "WARNING: Violation to rule 5.7 (Tag name should be unique) tag: {}".format(v)
33 if t == v:
34 coccilib.report.print_report(p[0], msg)
38 identifier v;
42 T v@p;
[all …]
Dreserved_names.cocci16 identifier t, v;
21 struct t *v@p;
23 struct t v@p;
25 union t v@p;
27 T v@p;
29 T *v@p;
31 struct t *v@p = E;
33 struct t v@p = E;
35 union t v@p = E;
37 T v@p = E;
[all …]
/Zephyr-latest/tests/crypto/mbedtls/src/
Dmbedtls.c81 if (ret < 0 || (size_t) ret >= n) { in test_snprintf()
85 if (strncmp(ref_buf, buf, sizeof(buf)) != 0 || in test_snprintf()
86 ref_ret != ret || memcmp(buf + n, ref + n, sizeof(buf) - n) != 0) { in test_snprintf()
90 return 0; in test_snprintf()
95 return (test_snprintf(0, "xxxxxxxxx", -1) != 0 || in run_test_snprintf()
96 test_snprintf(1, "", -1) != 0 || in run_test_snprintf()
97 test_snprintf(2, "1", -1) != 0 || in run_test_snprintf()
98 test_snprintf(3, "12", -1) != 0 || in run_test_snprintf()
99 test_snprintf(4, "123", 3) != 0 || in run_test_snprintf()
100 test_snprintf(5, "123", 3) != 0); in run_test_snprintf()
[all …]
/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,imx8m-pinctrl.yaml35 LVTLL=0,
36 HYS=0,
37 PUE=0,
38 ODE=0,
41 SION=0,
88 001 255_OHM — 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
89 010 105_OHM — 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
90 011 75_OHM — 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
91 100 85_OHM — 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
92 101 65_OHM — 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
[all …]
/Zephyr-latest/drivers/charger/
Dcharger_bq24190.c60 return 0; in bq24190_register_reset()
73 uint8_t v; in bq24190_charger_get_charge_type() local
78 ret = i2c_reg_read_byte_dt(&config->i2c, BQ24190_REG_POC, &v); in bq24190_charger_get_charge_type()
83 v = FIELD_GET(BQ24190_REG_POC_CHG_CONFIG_MASK, v); in bq24190_charger_get_charge_type()
85 if (!v) { in bq24190_charger_get_charge_type()
88 ret = i2c_reg_read_byte_dt(&config->i2c, BQ24190_REG_CCC, &v); in bq24190_charger_get_charge_type()
93 v = FIELD_GET(BQ24190_REG_CCC_FORCE_20PCT_MASK, v); in bq24190_charger_get_charge_type()
95 if (v) { in bq24190_charger_get_charge_type()
102 return 0; in bq24190_charger_get_charge_type()
108 uint8_t v; in bq24190_charger_get_health() local
[all …]
/Zephyr-latest/drivers/watchdog/
Dwdt_nxp_s32.c20 #define SWT_CR 0x0
21 #define SWT_CR_WEN_MASK BIT(0)
22 #define SWT_CR_WEN(v) FIELD_PREP(SWT_CR_WEN_MASK, (v)) argument
24 #define SWT_CR_FRZ(v) FIELD_PREP(SWT_CR_FRZ_MASK, (v)) argument
26 #define SWT_CR_STP(v) FIELD_PREP(SWT_CR_STP_MASK, (v)) argument
28 #define SWT_CR_SLK(v) FIELD_PREP(SWT_CR_SLK_MASK, (v)) argument
30 #define SWT_CR_HLK(v) FIELD_PREP(SWT_CR_HLK_MASK, (v)) argument
32 #define SWT_CR_ITR(v) FIELD_PREP(SWT_CR_ITR_MASK, (v)) argument
34 #define SWT_CR_WND(v) FIELD_PREP(SWT_CR_WND_MASK, (v)) argument
36 #define SWT_CR_RIA(v) FIELD_PREP(SWT_CR_RIA_MASK, (v)) argument
[all …]
/Zephyr-latest/drivers/edac/
Dibecc.h15 #define PCI_VENDOR_ID_INTEL 0x8086
18 #define PCI_DEVICE_ID_SKU5 0x4514
19 #define PCI_DEVICE_ID_SKU6 0x4528
20 #define PCI_DEVICE_ID_SKU7 0x452a
21 #define PCI_DEVICE_ID_SKU8 0x4516
22 #define PCI_DEVICE_ID_SKU9 0x452c
23 #define PCI_DEVICE_ID_SKU10 0x452e
24 #define PCI_DEVICE_ID_SKU11 0x4532
25 #define PCI_DEVICE_ID_SKU12 0x4518
26 #define PCI_DEVICE_ID_SKU13 0x451a
[all …]
/Zephyr-latest/include/zephyr/arch/xtensa/
Darch_inlines.h24 ({uint32_t v; \
25 __asm__ volatile ("rsr." sr " %0" : "=a"(v)); \
26 v; })
32 * @param v Value to be written to special register.
34 #define XTENSA_WSR(sr, v) \ argument
36 __asm__ volatile ("wsr." sr " %0" : : "r"(v)); \
47 ({uint32_t v; \
48 __asm__ volatile ("rur." ur " %0" : "=a"(v)); \
49 v; })
55 * @param v Value to be written to user register.
[all …]
/Zephyr-latest/subsys/logging/
Dlog_output_syst.c51 return 0; in out_func()
63 p->current = 0; in stp_write_putNibble()
73 stp_write_putNibble(systh, p, 0); in stp_write_flush()
78 struct stp_writer_data *p, mipi_syst_u8 v) in stp_write_d4() argument
80 stp_write_putNibble(systh, p, v); in stp_write_d4()
84 struct stp_writer_data *p, mipi_syst_u8 v) in stp_write_payload8() argument
86 stp_write_d4(systh, p, v); in stp_write_payload8()
87 stp_write_d4(systh, p, v>>4); in stp_write_payload8()
91 struct stp_writer_data *p, mipi_syst_u16 v) in stp_write_payload16() argument
93 stp_write_payload8(systh, p, (mipi_syst_u8)v); in stp_write_payload16()
[all …]
/Zephyr-latest/soc/altr/zephyr_nios2f/cpu/
Dghrd_10m50da.qsf21 # Version 16.0.0 Build 208 04/06/2016 SJ Standard Edition
42 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
44 set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Standard Edition"
85 set_location_assignment PIN_T20 -to user_led[0]
90 set_location_assignment PIN_L22 -to user_pb[0]
94 set_location_assignment PIN_H21 -to user_dipsw[0]
109 set_location_assignment PIN_N9 -to enet_rx_d[0]
116 set_location_assignment PIN_R5 -to enet_tx_d[0]
124 set_location_assignment PIN_C6 -to qspi_io[0]
142 set_location_assignment PIN_V20 -to mem_a[0]
[all …]

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