13 #define MC_RGM_DES                      0x0
14 #define MC_RGM_DES_F_POR_MASK           BIT(0)
15 #define MC_RGM_DES_F_POR(v)             FIELD_PREP(MC_RGM_DES_F_POR_MASK, (v))  argument
17 #define MC_RGM_FES                      0x8
18 #define MC_RGM_FES_F_EXR_MASK           BIT(0)
19 #define MC_RGM_FES_F_EXR(v)             FIELD_PREP(MC_RGM_FES_F_EXR_MASK, (v))  argument
21 #define MC_RGM_FERD                     0xc
23 #define MC_RGM_FBRE                     0x10
25 #define MC_RGM_FREC                     0x14
26 #define MC_RGM_FREC_FREC_MASK           GENMASK(3, 0)
27 #define MC_RGM_FREC_FREC(v)             FIELD_PREP(MC_RGM_FREC_FREC_MASK, (v))  argument
29 #define MC_RGM_FRET                     0x18
30 #define MC_RGM_FRET_FRET_MASK           GENMASK(3, 0)
31 #define MC_RGM_FRET_FRET(v)             FIELD_PREP(MC_RGM_FRET_FRET_MASK, (v))  argument
33 #define MC_RGM_DRET                     0x1c
34 #define MC_RGM_DRET_DRET_MASK           GENMASK(3, 0)
35 #define MC_RGM_DRET_DRET(v)             FIELD_PREP(MC_RGM_DRET_DRET_MASK, (v))  argument
37 #define MC_RGM_ERCTRL                   0x20
38 #define MC_RGM_ERCTRL_ERASSERT_MASK     BIT(0)
39 #define MC_RGM_ERCTRL_ERASSERT(v)       FIELD_PREP(MC_RGM_ERCTRL_ERASSERT_MASK, (v))  argument
41 #define MC_RGM_RDSS                     0x24
42 #define MC_RGM_RDSS_DES_RES_MASK        BIT(0)
43 #define MC_RGM_RDSS_DES_RES(v)          FIELD_PREP(MC_RGM_RDSS_DES_RES_MASK, (v))  argument
45 #define MC_RGM_RDSS_FES_RES(v)          FIELD_PREP(MC_RGM_RDSS_FES_RES_MASK, (v))  argument
47 #define MC_RGM_FRENTC                   0x28
48 #define MC_RGM_FRENTC_FRET_EN_MASK      BIT(0)
49 #define MC_RGM_FRENTC_FRET_EN(v)        FIELD_PREP(MC_RGM_FRENTC_FRET_EN_MASK, (v))  argument
51 #define MC_RGM_FRENTC_FRET_TIMEOUT(v)   FIELD_PREP(MC_RGM_FRENTC_FRET_TIMEOUT_MASK, (v))  argument
53 #define MC_RGM_LPDEBUG                  0x2c
54 #define MC_RGM_LPDEBUG_LP_DBG_EN_MASK   BIT(0)
55 #define MC_RGM_LPDEBUG_LP_DBG_EN(v)     FIELD_PREP(MC_RGM_LPDEBUG_LP_DBG_EN_MASK, (v))  argument
60 #define REG_READ(r)     sys_read32((mem_addr_t)(DT_INST_REG_ADDR(0) + (r)))
61 #define REG_WRITE(r, v) sys_write32((v), (mem_addr_t)(DT_INST_REG_ADDR(0) + (r)))  argument
71 	timeout = !WAIT_FOR(REG_READ(reg) == 0U, MC_RGM_TIMEOUT_US, REG_WRITE(reg, 0xffffffff));  in mc_rgm_clear_reset_status()
72 	return timeout ? -ETIMEDOUT : 0U;  in mc_rgm_clear_reset_status()
77 	int err = 0;  in mc_rgm_init()
87 	if (rst_status != 0U) {  in mc_rgm_init()
95 	REG_WRITE(MC_RGM_FERD, 0U);  in mc_rgm_init()
98 	if ((DT_INST_PROP(0, func_reset_threshold) != 0U) && (rst_status != 0U)) {  in mc_rgm_init()
100 		REG_WRITE(MC_RGM_FRET, MC_RGM_FRET_FRET(DT_INST_PROP(0, func_reset_threshold)));  in mc_rgm_init()
102 		REG_WRITE(MC_RGM_FRET, MC_RGM_FRET_FRET(0U));  in mc_rgm_init()
105 	if ((DT_INST_PROP(0, dest_reset_threshold) != 0U) &&  in mc_rgm_init()
106 	    (FIELD_GET(MC_RGM_DES_F_POR_MASK, rst_status) != 0U)) {  in mc_rgm_init()
108 		REG_WRITE(MC_RGM_DRET, MC_RGM_DRET_DRET(DT_INST_PROP(0, dest_reset_threshold)));  in mc_rgm_init()
110 		REG_WRITE(MC_RGM_DRET, MC_RGM_DRET_DRET(0U));  in mc_rgm_init()
122 DEVICE_DT_INST_DEFINE(0, mc_rgm_init, NULL, NULL, 0, PRE_KERNEL_1, 1, NULL);