Lines Matching +full:0 +full:v

24 	({uint32_t v; \
25 	 __asm__ volatile ("rsr." sr " %0" : "=a"(v)); \
26 	 v; })
32  * @param v Value to be written to special register.
34 #define XTENSA_WSR(sr, v) \  argument
36 		__asm__ volatile ("wsr." sr " %0" : : "r"(v)); \
47 	({uint32_t v; \
48 	 __asm__ volatile ("rur." ur " %0" : "=a"(v)); \
49 	 v; })
55  * @param v Value to be written to user register.
57 #define XTENSA_WUR(ur, v) \  argument
59 		__asm__ volatile ("wur." ur " %0" : : "r"(v)); \
77 	__asm__ volatile("rsr %0, PRID" : "=r"(prid));  in arch_proc_id()