Lines Matching +full:0 +full:v

15 #define PCI_VENDOR_ID_INTEL	0x8086
18 #define PCI_DEVICE_ID_SKU5 0x4514
19 #define PCI_DEVICE_ID_SKU6 0x4528
20 #define PCI_DEVICE_ID_SKU7 0x452a
21 #define PCI_DEVICE_ID_SKU8 0x4516
22 #define PCI_DEVICE_ID_SKU9 0x452c
23 #define PCI_DEVICE_ID_SKU10 0x452e
24 #define PCI_DEVICE_ID_SKU11 0x4532
25 #define PCI_DEVICE_ID_SKU12 0x4518
26 #define PCI_DEVICE_ID_SKU13 0x451a
27 #define PCI_DEVICE_ID_SKU14 0x4534
28 #define PCI_DEVICE_ID_SKU15 0x4536
33 #define NMI_STS_CNT_REG 0x61
40 * Writing 1 SERR NMI are disabled and cleared, writing 0
45 #define NMI_STS_MASK_EN GENMASK(3, 0)
60 /* Top of Upper Usable DRAM, offset 0xa8, 64 bit */
61 #define TOUUD_REG 0x2a
64 /* Top of Low Usable DRAM, offset 0xbc, 32 bit */
65 #define TOLUD_REG 0x2f
68 /* Total amount of physical memory, offset 0xa0, 64 bit */
69 #define TOM_REG 0x28
73 * offset 0x48, 64 bit
75 #define MCHBAR_REG 0x12
77 #define MCHBAR_ENABLE BIT64(0)
79 #define MCH_SIZE 0x10000
81 /* Capability register, offset 0xec, 32 bit */
82 #define CAPID0_C_REG 0x3b
85 /* Register controlling reporting error SERR, offset 0xc8, 16 bit */
86 #define ERRSTS_REG 0x32
91 * offset 0xca, 16 bit
96 #define ERRCMD_REG 0x32
104 #define CHANNEL_HASH 0x5024
108 #define IBECC_INJ_ADDR_BASE 0xdd88
111 #define IBECC_INJ_ADDR_MASK 0xdd80
114 #define IBECC_INJ_ADDR_CTRL 0xdd98
115 #define INJ_CTRL_COR 0x1
116 #define INJ_CTRL_UC 0x5
121 #define IBECC_ECC_ERROR_LOG 0xdd70
133 #define IBECC_PARITY_ERROR_LOG 0xdd78
143 #define MAD_INTER_CHAN 0x5000
144 #define INTER_CHAN_DDR_TYPE(v) BITFIELD(v, 2, 0) argument
146 #define INTER_CHAN_ECHM(v) BITFIELD(v, 3, 3) argument
148 #define INTER_CHAN_CH_L_MAP(v) BITFIELD(v, 4, 4) argument
150 #define INTER_CHAN_CH_S_SIZE BITFIELD(v, 19, 12)
153 #define MAD_INTRA_CH(index) (0x5004 + index * sizeof(uint32_t))
155 #define DIMM_L_MAP(v) BITFIELD(v, 0, 0) argument
158 #define MAD_DIMM_CH(index) (0x500c + index * sizeof(uint32_t))
160 #define DIMM_L_SIZE(v) (BITFIELD(v, 6, 0) << 29) argument
162 #define DIMM_L_WIDTH(v) BITFIELD(v, 8, 7) argument
164 #define DIMM_S_SIZE(v) (BITFIELD(v, 22, 16) << 29) argument
166 #define DIMM_S_WIDTH(v) BITFIELD(v, 25, 24) argument
170 #define CHANNEL_HASH 0x5024
173 #define CHANNEL_EHASH 0x5028
181 #define PCI_HOST_BRIDGE PCIE_BDF(0, 0, 0)