| /Zephyr-latest/drivers/i2c/ |
| D | i2c_dw_registers.h | 1 /* i2c_dw_registers.h - array access for I2C Design Ware registers */
6 * SPDX-License-Identifier: Apache-2.0
32 #define IC_DATA_CMD_DAT_MASK 0xFF
38 #define DW_INTR_STAT_RX_UNDER BIT(0)
53 #define DW_INTR_MASK_RX_UNDER BIT(0)
67 #define DW_INTR_MASK_RESET 0x000008ff
118 #define DW_IC_REG_CON (0x00)
119 #define DW_IC_REG_TAR (0x04)
120 #define DW_IC_REG_SAR (0x08)
121 #define DW_IC_REG_DATA_CMD (0x10)
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| /Zephyr-latest/drivers/spi/ |
| D | spi_dw_regs.h | 1 /* spi_dw_regs.h - Designware SPI driver private definitions */
7 * SPDX-License-Identifier: Apache-2.0
17 #define DW_SPI_REG_CTRLR0 (0x00)
18 #define DW_SPI_REG_CTRLR1 (0x04)
19 #define DW_SPI_REG_SSIENR (0x08)
20 #define DW_SPI_REG_MWCR (0x0c)
21 #define DW_SPI_REG_SER (0x10)
22 #define DW_SPI_REG_BAUDR (0x14)
23 #define DW_SPI_REG_TXFTLR (0x18)
24 #define DW_SPI_REG_RXFTLR (0x1c)
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| /Zephyr-latest/samples/drivers/clock_control_xec/src/ |
| D | main.c | 4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
12 #include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
23 struct pcr_regs *pcr = ((struct pcr_regs *)DT_REG_ADDR_BY_IDX(DT_NODELABEL(pcr), 0)); in pcr_clock_regs()
24 uint32_t r = pcr->PWR_RST_STS; in pcr_clock_regs()
28 LOG_INF("PCR Power Reset Status register(bit[10] is 32K_ACTIVE) = 0x%x", r); in pcr_clock_regs()
30 r = pcr->OSC_ID; in pcr_clock_regs()
31 LOG_INF("PCR Oscillator ID register(bit[8]=PLL Lock) = 0x%x", r); in pcr_clock_regs()
33 r = pcr->PROC_CLK_CTRL; in pcr_clock_regs()
34 LOG_INF("PCR Processor Clock Control register = 0x%x", r); in pcr_clock_regs()
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| /Zephyr-latest/boards/snps/nsim/arc_classic/support/ |
| D | nsim_em.props | 3 arcver=0x3
5 nsim_isa_rgf_banked_regs=32
6 nsim_isa_rgf_num_regs=32
8 nsim_isa_big_endian=0
9 nsim_isa_lpc_size=32
10 nsim_isa_pc_size=32
11 nsim_isa_addr_size=32
34 nsim_isa_xy_y_base=0xe0000000
38 nsim_isa_fpu_fast_mpy_option=0
39 nsim_isa_fpu_fast_div_option=0
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| D | nsim_em11d.props | 3 arcver=0x3
5 nsim_isa_rgf_banked_regs=32
6 nsim_isa_rgf_num_regs=32
8 nsim_isa_big_endian=0
9 nsim_isa_lpc_size=32
10 nsim_isa_pc_size=32
11 nsim_isa_addr_size=32
34 nsim_isa_xy_x_base=0xc0000000
35 nsim_isa_xy_y_base=0xe0000000
39 nsim_isa_fpu_fast_mpy_option=0
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| D | nsim_hs_mpuv6.props | 3 arcver=0x52
5 nsim_isa_rgf_banked_regs=32
6 nsim_isa_rgf_num_regs=32
8 nsim_isa_big_endian=0
9 nsim_isa_lpc_size=32
10 nsim_isa_pc_size=32
11 nsim_isa_addr_size=32
21 mpu_regions=32
28 nsim_isa_timer_1_int_level=0
36 nsim_isa_intvbase_preset=0x0
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| D | nsim_em7d_v22.props | 3 arcver=0x42
5 nsim_isa_rgf_num_regs=32
7 nsim_isa_big_endian=0
8 nsim_isa_lpc_size=32
9 nsim_isa_pc_size=32
10 nsim_isa_addr_size=32
25 nsim_isa_fpu_fast_mpy_option=0
26 nsim_isa_fpu_fast_div_option=0
30 nsim_isa_timer_1_int_level=0
41 nsim_isa_intvbase_preset=0x0
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| D | nsim_hs5x.props | 2 nsim_isa_core=0
3 arcver=0x60
5 nsim_isa_uarch_rev_major=0
6 nsim_isa_uarch_rev_minor=0
8 nsim_isa_rgf_num_regs=32
10 nsim_isa_big_endian=0
11 nsim_isa_lpc_size=0
12 nsim_isa_pc_size=32
13 nsim_isa_addr_size=32
19 nsim_isa_shift_option=0
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| D | nsim_sem_mpu_stack_guard.props | 3 arcver=0x43
5 nsim_isa_rgf_num_regs=32
7 nsim_isa_big_endian=0
8 nsim_isa_lpc_size=32
9 nsim_isa_pc_size=32
10 nsim_isa_addr_size=32
25 nsim_isa_fpu_fast_mpy_option=0
26 nsim_isa_fpu_fast_div_option=0
30 nsim_isa_timer_1_int_level=0
42 nsim_isa_intvbase_preset=0x0
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| D | nsim_sem.props | 3 arcver=0x43
5 nsim_isa_rgf_num_regs=32
7 nsim_isa_big_endian=0
8 nsim_isa_lpc_size=32
9 nsim_isa_pc_size=32
10 nsim_isa_addr_size=32
25 nsim_isa_fpu_fast_mpy_option=0
26 nsim_isa_fpu_fast_div_option=0
30 nsim_isa_timer_1_int_level=0
42 nsim_isa_intvbase_preset=0x0
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| D | nsim_vpx5.props | 3 arcver=0x54
8 nsim_isa_rgf_num_regs=32
10 nsim_isa_big_endian=0
11 nsim_isa_lpc_size=32
12 nsim_isa_pc_size=32
13 nsim_isa_addr_size=32
23 nsim_isa_timer_0_int_level=0
25 nsim_isa_timer_1_int_level=0
36 nsim_isa_volatile_limit=0
37 nsim_isa_volatile_disable=0
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| D | nsim_hs.props | 3 arcver=0x52
5 nsim_isa_rgf_banked_regs=32
6 nsim_isa_rgf_num_regs=32
8 nsim_isa_big_endian=0
9 nsim_isa_lpc_size=32
10 nsim_isa_pc_size=32
11 nsim_isa_addr_size=32
26 nsim_isa_timer_1_int_level=0
34 nsim_isa_intvbase_preset=0x0
41 dccm_size=0x100000
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| D | nsim_hs_flash_xip.props | 3 arcver=0x52
5 nsim_isa_rgf_banked_regs=32
6 nsim_isa_rgf_num_regs=32
8 nsim_isa_big_endian=0
9 nsim_isa_lpc_size=32
10 nsim_isa_pc_size=32
11 nsim_isa_addr_size=32
26 nsim_isa_timer_1_int_level=0
34 nsim_isa_intvbase_preset=0x0
41 nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
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| D | nsim_hs_sram.props | 3 arcver=0x52
5 nsim_isa_rgf_banked_regs=32
6 nsim_isa_rgf_num_regs=32
8 nsim_isa_big_endian=0
9 nsim_isa_lpc_size=32
10 nsim_isa_pc_size=32
11 nsim_isa_addr_size=32
26 nsim_isa_timer_1_int_level=0
34 nsim_isa_intvbase_preset=0x0
41 nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
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| /Zephyr-latest/tests/kernel/timer/timer_api/src/ |
| D | timer_convert.c | 4 * SPDX-License-Identifier: Apache-2.0
26 int precision; /* 32 or 64 */
50 TESTFUNC(ms, cyc, floor, 32)
52 TESTFUNC(ms, cyc, near, 32)
54 TESTFUNC(ms, cyc, ceil, 32)
56 TESTFUNC(ms, ticks, floor, 32)
58 TESTFUNC(ms, ticks, near, 32)
60 TESTFUNC(ms, ticks, ceil, 32)
62 TESTFUNC(us, cyc, floor, 32)
64 TESTFUNC(us, cyc, near, 32)
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| /Zephyr-latest/tests/unit/pot/ |
| D | log2ceil.cpp | 4 * SPDX-License-Identifier: Apache-2.0
10 static constexpr uint8_t val = LOG2CEIL(32);
11 static constexpr uint8_t val64 = LOG2CEIL(42 + BIT64(32));
20 zassert_equal(0, LOG2CEIL(LLONG_MIN)); in ZTEST()
21 zassert_equal(0, LOG2CEIL(LONG_MIN)); in ZTEST()
22 zassert_equal(0, LOG2CEIL(INT_MIN)); in ZTEST()
23 zassert_equal(0, LOG2CEIL(-1)); in ZTEST()
24 zassert_equal(0, LOG2CEIL(0)); in ZTEST()
25 zassert_equal(0, LOG2CEIL(1)); in ZTEST()
31 zassert_equal(32, LOG2CEIL(BIT(31) + 1)); in ZTEST()
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| D | log2ceil.c | 4 * SPDX-License-Identifier: Apache-2.0
11 static const uint8_t val64 = LOG2CEIL(42 + BIT64(32));
15 zassert_equal(0, LOG2CEIL(LLONG_MIN)); in ZTEST()
16 zassert_equal(0, LOG2CEIL(LONG_MIN)); in ZTEST()
17 zassert_equal(0, LOG2CEIL(INT_MIN)); in ZTEST()
18 zassert_equal(0, LOG2CEIL(-1)); in ZTEST()
19 zassert_equal(0, LOG2CEIL(0)); in ZTEST()
20 zassert_equal(0, LOG2CEIL(1)); in ZTEST()
26 zassert_equal(32, LOG2CEIL(BIT(31) + 1)); in ZTEST()
27 zassert_equal(32, LOG2CEIL(UINT32_MAX)); in ZTEST()
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| /Zephyr-latest/soc/microchip/mec/mec172x/reg/ |
| D | mec172x_vbat.h | 4 * SPDX-License-Identifier: Apache-2.0
16 /* Offset 0x00 Power-Fail and Reset Status */
17 #define MCHP_VBATR_PFRS_OFS 0u
18 #define MCHP_VBATR_PFRS_MASK 0x7cu
33 /* Offset 0x08 32K Clock Source register */
34 #define MCHP_VBATR_CS_OFS 0x08u
35 #define MCHP_VBATR_CS_MASK 0x71f1u
36 #define MCHP_VBATR_CS_SO_EN_POS 0
44 /* Enable and start internal 32KHz Silicon Oscillator */
45 #define MCHP_VBATR_CS_SO_EN BIT(0)
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| /Zephyr-latest/dts/xtensa/intel/ |
| D | intel_adsp_cavs.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
12 compatible = "intel,adsp-gpdma";
13 #dma-cells = <1>;
14 reg = <0x0007c000 0x1000>;
15 shim = <0x00078400 0x100>;
16 interrupts = <0x10 0 0>;
17 interrupt-parent = <&cavs_intc3>;
18 dma-buf-size-alignment = <4>;
19 dma-copy-alignment = <4>;
25 compatible = "intel,adsp-gpdma";
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| /Zephyr-latest/include/zephyr/drivers/interrupt_controller/ |
| D | intc_vim.h | 4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/interrupt-controller/ti-vim.h>
16 #define VIM_BASE_ADDR DT_REG_ADDR(DT_INST(0, ti_vim))
18 #define VIM_MAX_IRQ_PER_GROUP (32)
26 #define VIM_PID (VIM_BASE_ADDR + 0x0000)
27 #define VIM_INFO (VIM_BASE_ADDR + 0x0004)
28 #define VIM_PRIIRQ (VIM_BASE_ADDR + 0x0008)
29 #define VIM_PRIFIQ (VIM_BASE_ADDR + 0x000C)
30 #define VIM_IRQGSTS (VIM_BASE_ADDR + 0x0010)
31 #define VIM_FIQGSTS (VIM_BASE_ADDR + 0x0014)
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| /Zephyr-latest/samples/boards/espressif/flash_memory_mapped/src/ |
| D | main.c | 4 * SPDX-License-Identifier: Apache-2.0
21 uint8_t buffer[32]; in main()
30 printk("%s: device not ready.\n", flash_device->name); in main()
31 return 0; in main()
36 LOG_INF("memory-mapped pointer address: %p", mem_ptr); in main()
40 LOG_HEXDUMP_INF(mem_ptr, 32, "flash read using memory-mapped pointer"); in main()
42 LOG_INF("writing 32-bytes data using flash API"); in main()
43 memset(buffer, 0, sizeof(buffer)); in main()
44 for (int k = 0; k < 32; k++) { in main()
47 flash_write(flash_device, address, buffer, 32); in main()
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| /Zephyr-latest/tests/drivers/gpio/gpio_reserved_ranges/src/ |
| D | main.c | 4 * SPDX-License-Identifier: Apache-2.0
45 zassert_equal(GPIO_DT_RESERVED_RANGES_NGPIOS(TEST_GPIO_1, 32), in ZTEST()
46 0xdeadbeef, ""); in ZTEST()
47 zassert_equal(GPIO_DT_RESERVED_RANGES_NGPIOS(TEST_GPIO_2, 32), in ZTEST()
48 0x7fffbeff, ""); in ZTEST()
50 0xfffc0418, ""); in ZTEST()
52 0xfffffff0, ""); in ZTEST()
53 zassert_equal(GPIO_DT_RESERVED_RANGES_NGPIOS(TEST_GPIO_5, 0), in ZTEST()
54 0xffffffff, ""); in ZTEST()
55 zassert_equal(GPIO_DT_RESERVED_RANGES_NGPIOS(TEST_GPIO_6, 32), in ZTEST()
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| /Zephyr-latest/include/zephyr/toolchain/ |
| D | xcc_missing_defs.h | 4 * SPDX-License-Identifier: Apache-2.0
29 #define __INT_WIDTH__ 32
36 #define __LONG_WIDTH__ 32
52 #define __UINTMAX_MAX__ 0xffffffffffffffffULL
64 #define __INTPTR_MAX__ 0x7fffffffL
66 #define __INTPTR_WIDTH__ 32
69 #define __PTRDIFF_MAX__ 0x7fffffffL
70 #define __PTRDIFF_WIDTH__ 32
73 #define __UINTPTR_MAX__ 0xffffffffLU
81 #define __SIZE_MAX__ 0xffffffffU
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_mchp_xec.c | 4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
30 * 32KHz period counter minimum for pass/fail: 16-bit
31 * 32KHz period counter maximum for pass/fail: 16-bit
32 * 32KHz duty cycle variation max for pass/fail: 16-bit
33 * 32KHz valid count minimum: 8-bit
37 * One 32KHz clock pulse = 1464.84 48 MHz counts.
44 #define DEST_PLL 0
47 #define CLK32K_FLAG_CRYSTAL_SE BIT(0)
73 enum clk32k_dest { CLK32K_DEST_PLL = 0, CLK32K_DEST_PERIPH, CLK32K_DEST_MAX };
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| /Zephyr-latest/drivers/misc/timeaware_gpio/ |
| D | timeaware_gpio_intel.c | 4 * SPDX-License-Identifier: Apache-2.0
18 #define ART_L 0x00 /* ART lower 32 bit reg */
19 #define ART_H 0x04 /* ART higher 32 bit reg */
20 #define CTL 0x10 /* TGPIO control reg */
21 #define COMPV31_0 0x20 /* Comparator lower 32 bit reg */
22 #define COMPV63_32 0x24 /* Comparator higher 32 bit reg */
23 #define PIV31_0 0x28 /* Periodic Interval lower 32 bit reg */
24 #define PIV63_32 0x2c /* Periodic Interval higher 32 bit reg */
25 #define TCV31_0 0x30 /* Time Capture lower 32 bit reg */
26 #define TCV63_32 0x34 /* Time Capture higher 32 bit reg */
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