Lines Matching +full:0 +full:- +full:32
1 /* i2c_dw_registers.h - array access for I2C Design Ware registers */
6 * SPDX-License-Identifier: Apache-2.0
32 #define IC_DATA_CMD_DAT_MASK 0xFF
38 #define DW_INTR_STAT_RX_UNDER BIT(0)
53 #define DW_INTR_MASK_RX_UNDER BIT(0)
67 #define DW_INTR_MASK_RESET 0x000008ff
118 #define DW_IC_REG_CON (0x00)
119 #define DW_IC_REG_TAR (0x04)
120 #define DW_IC_REG_SAR (0x08)
121 #define DW_IC_REG_DATA_CMD (0x10)
122 #define DW_IC_REG_SS_SCL_HCNT (0x14)
123 #define DW_IC_REG_SS_SCL_LCNT (0x18)
124 #define DW_IC_REG_FS_SCL_HCNT (0x1C)
125 #define DW_IC_REG_FS_SCL_LCNT (0x20)
126 #define DW_IC_REG_HS_SCL_HCNT (0x24)
127 #define DW_IC_REG_HS_SCL_LCNT (0x28)
128 #define DW_IC_REG_INTR_STAT (0x2C)
129 #define DW_IC_REG_INTR_MASK (0x30)
130 #define DW_IC_REG_RX_TL (0x38)
131 #define DW_IC_REG_TX_TL (0x3C)
132 #define DW_IC_REG_CLR_INTR (0x40)
133 #define DW_IC_REG_CLR_RX_UNDER (0x44)
134 #define DW_IC_REG_CLR_RX_OVER (0x48)
135 #define DW_IC_REG_CLR_TX_OVER (0x4c)
136 #define DW_IC_REG_CLR_RD_REQ (0x50)
137 #define DW_IC_REG_CLR_TX_ABRT (0x54)
138 #define DW_IC_REG_CLR_RX_DONE (0x58)
139 #define DW_IC_REG_CLR_ACTIVITY (0x5c)
140 #define DW_IC_REG_CLR_STOP_DET (0x60)
141 #define DW_IC_REG_CLR_START_DET (0x64)
142 #define DW_IC_REG_CLR_GEN_CALL (0x68)
143 #define DW_IC_REG_ENABLE (0x6C)
144 #define DW_IC_REG_STATUS (0x70)
145 #define DW_IC_REG_TXFLR (0x74)
146 #define DW_IC_REG_RXFLR (0x78)
147 #define DW_IC_REG_DMA_CR (0x88)
148 #define DW_IC_REG_TDLR (0x8C)
149 #define DW_IC_REG_RDLR (0x90)
150 #define DW_IC_REG_FS_SPKLEN (0xA0)
151 #define DW_IC_REG_HS_SPKLEN (0xA4)
152 #define DW_IC_REG_COMP_PARAM_1 (0xF4)
153 #define DW_IC_REG_COMP_TYPE (0xFC)
155 #define IDMA_REG_INTR_STS 0xAE8
156 #define IDMA_TX_RX_CHAN_MASK 0x3
159 #define DW_IC_CON_MASTER_MODE_BIT (0)
162 #define DW_IC_DMA_RX_ENABLE BIT(0)
164 #define DW_IC_DMA_ENABLE (BIT(0) | BIT(1))
167 DEFINE_MM_REG_WRITE(con, DW_IC_REG_CON, 32)
168 DEFINE_MM_REG_READ(con, DW_IC_REG_CON, 32)
170 DEFINE_MM_REG_WRITE(cmd_data, DW_IC_REG_DATA_CMD, 32)
171 DEFINE_MM_REG_READ(cmd_data, DW_IC_REG_DATA_CMD, 32)
173 DEFINE_MM_REG_WRITE(ss_scl_hcnt, DW_IC_REG_SS_SCL_HCNT, 32)
174 DEFINE_MM_REG_WRITE(ss_scl_lcnt, DW_IC_REG_SS_SCL_LCNT, 32)
176 DEFINE_MM_REG_WRITE(fs_scl_hcnt, DW_IC_REG_FS_SCL_HCNT, 32)
177 DEFINE_MM_REG_WRITE(fs_scl_lcnt, DW_IC_REG_FS_SCL_LCNT, 32)
179 DEFINE_MM_REG_WRITE(hs_scl_hcnt, DW_IC_REG_HS_SCL_HCNT, 32)
180 DEFINE_MM_REG_WRITE(hs_scl_lcnt, DW_IC_REG_HS_SCL_LCNT, 32)
182 DEFINE_MM_REG_READ(intr_stat, DW_IC_REG_INTR_STAT, 32)
186 DEFINE_MM_REG_WRITE(intr_mask, DW_IC_REG_INTR_MASK, 32)
191 DEFINE_MM_REG_WRITE(rx_tl, DW_IC_REG_RX_TL, 32)
192 DEFINE_MM_REG_WRITE(tx_tl, DW_IC_REG_TX_TL, 32)
194 DEFINE_MM_REG_READ(clr_intr, DW_IC_REG_CLR_INTR, 32)
195 DEFINE_MM_REG_READ(clr_stop_det, DW_IC_REG_CLR_STOP_DET, 32)
196 DEFINE_MM_REG_READ(clr_start_det, DW_IC_REG_CLR_START_DET, 32)
197 DEFINE_MM_REG_READ(clr_gen_call, DW_IC_REG_CLR_GEN_CALL, 32)
198 DEFINE_MM_REG_READ(clr_tx_abrt, DW_IC_REG_CLR_TX_ABRT, 32)
199 DEFINE_MM_REG_READ(clr_rx_under, DW_IC_REG_CLR_RX_UNDER, 32)
200 DEFINE_MM_REG_READ(clr_rx_over, DW_IC_REG_CLR_RX_OVER, 32)
201 DEFINE_MM_REG_READ(clr_tx_over, DW_IC_REG_CLR_TX_OVER, 32)
202 DEFINE_MM_REG_READ(clr_rx_done, DW_IC_REG_CLR_RX_DONE, 32)
203 DEFINE_MM_REG_READ(clr_rd_req, DW_IC_REG_CLR_RD_REQ, 32)
204 DEFINE_MM_REG_READ(clr_activity, DW_IC_REG_CLR_ACTIVITY, 32)
206 #define DW_IC_ENABLE_EN_BIT (0)
210 #define DW_IC_STATUS_ACTIVITY_BIT (0)
217 DEFINE_MM_REG_READ(txflr, DW_IC_REG_TXFLR, 32)
218 DEFINE_MM_REG_READ(rxflr, DW_IC_REG_RXFLR, 32)
220 DEFINE_MM_REG_READ(dma_cr, DW_IC_REG_DMA_CR, 32)
221 DEFINE_MM_REG_WRITE(dma_cr, DW_IC_REG_DMA_CR, 32)
223 DEFINE_MM_REG_READ(tdlr, DW_IC_REG_TDLR, 32)
224 DEFINE_MM_REG_WRITE(tdlr, DW_IC_REG_TDLR, 32)
225 DEFINE_MM_REG_READ(rdlr, DW_IC_REG_RDLR, 32)
226 DEFINE_MM_REG_WRITE(rdlr, DW_IC_REG_RDLR, 32)
228 DEFINE_MM_REG_READ(fs_spklen, DW_IC_REG_FS_SPKLEN, 32)
229 DEFINE_MM_REG_READ(hs_spklen, DW_IC_REG_HS_SPKLEN, 32)
231 DEFINE_MM_REG_READ(comp_param_1, DW_IC_REG_COMP_PARAM_1, 32)
232 DEFINE_MM_REG_READ(comp_type, DW_IC_REG_COMP_TYPE, 32)
233 DEFINE_MM_REG_READ(tar, DW_IC_REG_TAR, 32)
234 DEFINE_MM_REG_WRITE(tar, DW_IC_REG_TAR, 32)
235 DEFINE_MM_REG_WRITE(sar, DW_IC_REG_SAR, 32)