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4  * SPDX-License-Identifier: Apache-2.0
16 /* Offset 0x00 Power-Fail and Reset Status */
17 #define MCHP_VBATR_PFRS_OFS		0u
18 #define MCHP_VBATR_PFRS_MASK		0x7cu
33 /* Offset 0x08 32K Clock Source register */
34 #define MCHP_VBATR_CS_OFS		0x08u
35 #define MCHP_VBATR_CS_MASK		0x71f1u
36 #define MCHP_VBATR_CS_SO_EN_POS 0
44 /* Enable and start internal 32KHz Silicon Oscillator */
45 #define MCHP_VBATR_CS_SO_EN		BIT(0)
53 #define MCHP_VBATR_CS_XTAL_CNTR_MSK	0x1800u
54 #define MCHP_VBATR_CS_XTAL_CNTR_DG	0x0800u
55 #define MCHP_VBATR_CS_XTAL_CNTR_RG	0x1000u
56 #define MCHP_VBATR_CS_XTAL_CNTR_MG	0x1800u
57 /* Select source of peripheral 32KHz clock */
59 #define MCHP_VBATR_CS_PCS_MSK			0x30000u
60 #define MCHP_VBATR_CS_PCR_VTR_VBAT_SO_VAL	0
64 /* 32K silicon OSC when chip powered by VBAT or VTR */
65 #define MCHP_VBATR_CS_PCS_VTR_VBAT_SO		0u
66 /* 32K external crystal when chip powered by VBAT or VTR */
67 #define MCHP_VBATR_CS_PCS_VTR_VBAT_XTAL		0x10000u
68 /* 32K input pin on VTR. Switch to Silicon OSC on VBAT */
69 #define MCHP_VBATR_CS_PCS_VTR_PIN_SO		0x20000u
70 /* 32K input pin on VTR. Switch to crystal on VBAT */
71 #define MCHP_VBATR_CS_PCS_VTR_PIN_XTAL		0x30000u
72 /* Disable internal 32K VBAT clock source when VTR is off */
77  * Monotonic Counter least significant word (32-bit), read-only.
80 #define MCHP_VBATR_MCNT_LSW_OFS		0x20u
82 /* Monotonic Counter most significant word (32-bit). Read-Write */
83 #define MCHP_VBATR_MCNT_MSW_OFS		0x24u
86 #define MCHP_VBATR_ROM_FEAT_OFS		0x28u
89 #define MCHP_VBATR_EMBRD_EN_OFS		0x34u
90 #define MCHP_VBATR_EMBRD_EN		BIT(0)