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Searched refs:clk_base (Results 1 – 22 of 22) sorted by relevance

/Linux-v5.4/drivers/clk/tegra/
Dclk-tegra210.c288 static void __iomem *clk_base; variable
491 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_control_enable()
496 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_control_enable()
504 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_sequence_start()
506 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_sequence_start()
514 val = readl_relaxed(clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_control_enable()
518 writel_relaxed(val, clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_control_enable()
526 val = readl_relaxed(clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_sequence_start()
528 writel_relaxed(val, clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_sequence_start()
536 val = readl_relaxed(clk_base + SATA_PLL_CFG0); in tegra210_set_sata_pll_seq_sw()
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Dclk-tegra-super-gen4.c95 static void __init tegra_sclk_init(void __iomem *clk_base, in tegra_sclk_init() argument
109 clk_base + SCLK_BURST_POLICY, in tegra_sclk_init()
119 clk_base + SCLK_DIVIDER, 0, 8, in tegra_sclk_init()
132 clk_base + SCLK_BURST_POLICY, in tegra_sclk_init()
142 clk_base + SYSTEM_CLK_RATE, 4, 2, 0, in tegra_sclk_init()
146 clk_base + SYSTEM_CLK_RATE, in tegra_sclk_init()
157 clk_base + SYSTEM_CLK_RATE, 0, 2, 0, in tegra_sclk_init()
160 CLK_IS_CRITICAL, clk_base + SYSTEM_CLK_RATE, in tegra_sclk_init()
165 static void __init tegra_super_clk_init(void __iomem *clk_base, in tegra_super_clk_init() argument
182 clk_base + CCLKG_BURST_POLICY, in tegra_super_clk_init()
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Dclk-tegra20.c130 static void __iomem *clk_base; variable
574 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); in tegra20_clk_measure_input_freq()
608 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & in tegra20_get_pll_ref_div()
630 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
636 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
639 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, in tegra20_pll_init()
644 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, in tegra20_pll_init()
650 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
653 clk_base + PLLM_OUT, 1, 0, in tegra20_pll_init()
658 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
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Dclk-tegra30.c148 static void __iomem *clk_base; variable
821 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
827 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra30_pll_init()
830 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, in tegra30_pll_init()
835 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base, in tegra30_pll_init()
841 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra30_pll_init()
844 clk_base + PLLM_OUT, 1, 0, in tegra30_pll_init()
849 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
859 clk = tegra_clk_register_pllu("pll_u", "pll_ref", clk_base, 0, in tegra30_pll_init()
864 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
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Dclk.h314 void __iomem *clk_base; member
340 void __iomem *clk_base, void __iomem *pmc,
345 void __iomem *clk_base, void __iomem *pmc,
350 void __iomem *clk_base, void __iomem *pmc,
356 void __iomem *clk_base, void __iomem *pmc,
362 void __iomem *clk_base, void __iomem *pmc,
368 void __iomem *clk_base, void __iomem *pmc,
374 const char *parent_name, void __iomem *clk_base,
381 void __iomem *clk_base, unsigned long flags,
387 void __iomem *clk_base, unsigned long flags,
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Dclk-tegra114.c130 static void __iomem *clk_base; variable
896 static void __init tegra114_fixed_clk_init(void __iomem *clk_base) in tegra114_fixed_clk_init() argument
916 static void __init tegra114_pll_init(void __iomem *clk_base, in tegra114_pll_init() argument
922 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, in tegra114_pll_init()
928 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra114_pll_init()
931 clk_base + PLLC_OUT, 1, 0, in tegra114_pll_init()
936 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, in tegra114_pll_init()
941 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, in tegra114_pll_init()
946 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc, in tegra114_pll_init()
952 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra114_pll_init()
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Dclk-periph-gate.c20 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
22 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
24 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
27 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
29 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
76 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable()
77 writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable()
79 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable()
120 const char *parent_name, u8 gate_flags, void __iomem *clk_base, in tegra_clk_register_periph_gate() argument
145 gate->clk_base = clk_base; in tegra_clk_register_periph_gate()
Dclk-tegra-audio.c128 static void __init tegra_audio_sync_clk_init(void __iomem *clk_base, in tegra_audio_sync_clk_init() argument
148 clk_base + data->offset, 0, 3, 0, in tegra_audio_sync_clk_init()
157 0, clk_base + data->offset, 4, in tegra_audio_sync_clk_init()
163 void __init tegra_audio_clk_init(void __iomem *clk_base, in tegra_audio_clk_init() argument
184 clk_base, pmc_base, 0, info->pll_params, in tegra_audio_clk_init()
194 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra_audio_clk_init()
197 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | in tegra_audio_clk_init()
215 tegra_audio_sync_clk_init(clk_base, tegra_clks, audio_clks, in tegra_audio_clk_init()
221 writel_relaxed(1, clk_base + dmic_clks[i].offset); in tegra_audio_clk_init()
223 tegra_audio_sync_clk_init(clk_base, tegra_clks, dmic_clks, in tegra_audio_clk_init()
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Dclk-tegra124.c102 static void __iomem *clk_base; variable
992 static __init void tegra124_periph_clk_init(void __iomem *clk_base, in tegra124_periph_clk_init() argument
1002 clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base, in tegra124_periph_clk_init()
1007 clk_base + PLLD_MISC, 30, 0, &pll_d_lock); in tegra124_periph_clk_init()
1011 clk_base, 0, 48, in tegra124_periph_clk_init()
1016 clk_base, 0, 82, in tegra124_periph_clk_init()
1020 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, in tegra124_periph_clk_init()
1025 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra124_periph_clk_init()
1031 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra124_periph_clk_init()
1036 tegra_periph_clk_init(clk_base, pmc_base, tegra124_clks, &pll_p_params); in tegra124_periph_clk_init()
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Dclk-periph.c132 void __iomem *clk_base, u32 offset, in _tegra_clk_register_periph() argument
160 periph->mux.reg = clk_base + offset; in _tegra_clk_register_periph()
161 periph->divider.reg = div ? (clk_base + offset) : NULL; in _tegra_clk_register_periph()
162 periph->gate.clk_base = clk_base; in _tegra_clk_register_periph()
179 struct tegra_clk_periph *periph, void __iomem *clk_base, in tegra_clk_register_periph() argument
183 periph, clk_base, offset, flags); in tegra_clk_register_periph()
188 struct tegra_clk_periph *periph, void __iomem *clk_base, in tegra_clk_register_periph_nodiv() argument
193 periph, clk_base, offset, CLK_SET_RATE_PARENT); in tegra_clk_register_periph_nodiv()
196 struct clk *tegra_clk_register_periph_data(void __iomem *clk_base, in tegra_clk_register_periph_data() argument
201 clk_base, init->offset, init->flags); in tegra_clk_register_periph_data()
Dclk-pll.c230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
237 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
302 lock_addr = pll->clk_base; in clk_pll_wait_for_lock()
979 val = readl(pll->clk_base + PLLE_SS_CTRL); in clk_plle_enable()
982 writel(val, pll->clk_base + PLLE_SS_CTRL); in clk_plle_enable()
1116 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_enable()
1126 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_enable()
1128 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_enable()
1138 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_enable()
1222 void __iomem *clk_base, in _setup_dynamic_ramp() argument
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Dclk-tegra-periph.c868 static void __init periph_clk_init(void __iomem *clk_base, in periph_clk_init() argument
890 clk = tegra_clk_register_periph_data(clk_base, data); in periph_clk_init()
895 static void __init gate_clk_init(void __iomem *clk_base, in gate_clk_init() argument
913 clk_base, data->flags, in gate_clk_init()
920 static void __init div_clk_init(void __iomem *clk_base, in div_clk_init() argument
937 data->p.parent_name, clk_base + data->offset, in div_clk_init()
947 static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base, in init_pllp() argument
958 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, in init_pllp()
974 clk_base + data->offset, 0, data->div_flags, in init_pllp()
977 data->div_name, clk_base + data->offset, in init_pllp()
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Dclk-sdmmc-mux.c209 void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags, in tegra_clk_register_sdmmc_mux_div() argument
233 sdmmc_mux->reg = clk_base + offset; in tegra_clk_register_sdmmc_mux_div()
235 sdmmc_mux->gate.clk_base = clk_base; in tegra_clk_register_sdmmc_mux_div()
Dclk-tegra-fixed.c21 int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, in tegra_osc_clk_init() argument
31 val = readl_relaxed(clk_base + OSC_CTRL); in tegra_osc_clk_init()
Dclk.c137 static void __iomem *clk_base; variable
153 clk_base + periph_regs[id / 32].rst_set_reg); in tegra_clk_rst_assert()
167 clk_base + periph_regs[id / 32].rst_clr_reg); in tegra_clk_rst_deassert()
204 clk_base = regs; in tegra_clk_init()
/Linux-v5.4/arch/arm/mach-prima2/
Dplatsmp.c22 static void __iomem *clk_base; variable
59 clk_base = of_iomap(np, 0); in sirfsoc_boot_secondary()
60 if (!clk_base) in sirfsoc_boot_secondary()
71 clk_base + SIRFSOC_CPU1_JUMPADDR_OFFSET); in sirfsoc_boot_secondary()
75 clk_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET); in sirfsoc_boot_secondary()
/Linux-v5.4/drivers/clk/
Dclk-npcm7xx.c544 void __iomem *clk_base; in npcm7xx_clk_init() local
557 clk_base = ioremap(res.start, resource_size(&res)); in npcm7xx_clk_init()
558 if (!clk_base) in npcm7xx_clk_init()
575 hw = npcm7xx_clk_register_pll(clk_base + pll_data->reg, in npcm7xx_clk_init()
608 mux_data->flags, clk_base + NPCM7XX_CLKSEL, in npcm7xx_clk_init()
628 clk_base + div_data->reg, in npcm7xx_clk_init()
652 iounmap(clk_base); in npcm7xx_clk_init()
/Linux-v5.4/drivers/pinctrl/samsung/
Dpinctrl-exynos-arm.c45 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; in s5pv210_retention_disable() local
48 tmp = __raw_readl(clk_base + S5P_OTHERS); in s5pv210_retention_disable()
51 __raw_writel(tmp, clk_base + S5P_OTHERS); in s5pv210_retention_disable()
60 void __iomem *clk_base; in s5pv210_retention_init() local
73 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
75 if (!clk_base) { in s5pv210_retention_init()
80 ctrl->priv = (void __force *)clk_base; in s5pv210_retention_init()
/Linux-v5.4/drivers/cpufreq/
Ds5pv210-cpufreq.c24 static void __iomem *clk_base; variable
27 #define S5P_CLKREG(x) (clk_base + (x))
622 clk_base = of_iomap(np, 0); in s5pv210_cpufreq_probe()
624 if (!clk_base) { in s5pv210_cpufreq_probe()
670 iounmap(clk_base); in s5pv210_cpufreq_probe()
/Linux-v5.4/drivers/mmc/host/
Dsdhci-of-at91.c150 unsigned int clk_base, clk_mul; in sdhci_at91_set_clks_presets() local
162 clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; in sdhci_at91_set_clks_presets()
164 gck_rate = clk_base * 1000000 * (clk_mul + 1); in sdhci_at91_set_clks_presets()
179 clk_mul = real_gck_rate / (clk_base * 1000000) - 1; in sdhci_at91_set_clks_presets()
/Linux-v5.4/drivers/clk/nxp/
Dclk-lpc18xx-cgu.c638 static struct clk *clk_base[BASE_CLK_MAX]; variable
640 .clks = clk_base,
649 clk_base[i] = lpc18xx_register_base_clk(&lpc18xx_cgu_base_clks[i], in lpc18xx_cgu_register_base_clks()
651 if (IS_ERR(clk_base[i]) && PTR_ERR(clk_base[i]) != -ENOENT) in lpc18xx_cgu_register_base_clks()
/Linux-v5.4/drivers/clk/meson/
Dmeson8b.c3644 void __iomem *clk_base; in meson8b_clkc_init_common() local
3653 clk_base = of_iomap(np, 1); in meson8b_clkc_init_common()
3654 if (!clk_base) { in meson8b_clkc_init_common()
3659 map = regmap_init_mmio(NULL, clk_base, &clkc_regmap_config); in meson8b_clkc_init_common()