102 static void __iomem *clk_base;  variable
992 static __init void tegra124_periph_clk_init(void __iomem *clk_base,  in tegra124_periph_clk_init()  argument
1002 	clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base,  in tegra124_periph_clk_init()
1007 				clk_base + PLLD_MISC, 30, 0, &pll_d_lock);  in tegra124_periph_clk_init()
1011 					     clk_base, 0, 48,  in tegra124_periph_clk_init()
1016 					     clk_base, 0, 82,  in tegra124_periph_clk_init()
1020 	clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,  in tegra124_periph_clk_init()
1025 	clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,  in tegra124_periph_clk_init()
1031 	clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,  in tegra124_periph_clk_init()
1036 	tegra_periph_clk_init(clk_base, pmc_base, tegra124_clks, &pll_p_params);  in tegra124_periph_clk_init()
1039 static void __init tegra124_pll_init(void __iomem *clk_base,  in tegra124_pll_init()  argument
1045 	clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,  in tegra124_pll_init()
1052 			clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra124_pll_init()
1055 				clk_base + PLLC_OUT, 1, 0,  in tegra124_pll_init()
1067 	clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,  in tegra124_pll_init()
1073 	clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,  in tegra124_pll_init()
1079 	clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,  in tegra124_pll_init()
1086 				clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra124_pll_init()
1089 				clk_base + PLLM_OUT, 1, 0,  in tegra124_pll_init()
1101 	clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0,  in tegra124_pll_init()
1108 				CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,  in tegra124_pll_init()
1132 	clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,  in tegra124_pll_init()
1144 	clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,  in tegra124_pll_init()
1150 					 clk_base + PLLRE_BASE, 16, 4, 0,  in tegra124_pll_init()
1157 				      clk_base, 0, &pll_e_params, NULL);  in tegra124_pll_init()
1162 	clk = tegra_clk_register_pllss("pll_c4", "pll_ref", clk_base, 0,  in tegra124_pll_init()
1168 	clk = tegra_clk_register_pllss("pll_dp", "pll_ref", clk_base, 0,  in tegra124_pll_init()
1174 	clk = tegra_clk_register_pllss("pll_d2", "pll_ref", clk_base, 0,  in tegra124_pll_init()
1193 		reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);  in tegra124_wait_cpu_in_reset()
1208 				readl(clk_base + CLK_SOURCE_CSITE);  in tegra124_cpu_clock_suspend()
1209 	writel(3 << 30, clk_base + CLK_SOURCE_CSITE);  in tegra124_cpu_clock_suspend()
1212 				readl(clk_base + CCLKG_BURST_POLICY);  in tegra124_cpu_clock_suspend()
1214 				readl(clk_base + CCLKG_BURST_POLICY + 4);  in tegra124_cpu_clock_suspend()
1220 				clk_base + CLK_SOURCE_CSITE);  in tegra124_cpu_clock_resume()
1223 					clk_base + CCLKG_BURST_POLICY);  in tegra124_cpu_clock_resume()
1225 					clk_base + CCLKG_BURST_POLICY + 4);  in tegra124_cpu_clock_resume()
1335 	readl_relaxed(clk_base + RST_DFLL_DVCO);  in tegra124_car_barrier()
1347 	v = readl_relaxed(clk_base + RST_DFLL_DVCO);  in tegra124_clock_assert_dfll_dvco_reset()
1349 	writel_relaxed(v, clk_base + RST_DFLL_DVCO);  in tegra124_clock_assert_dfll_dvco_reset()
1363 	v = readl_relaxed(clk_base + RST_DFLL_DVCO);  in tegra124_clock_deassert_dfll_dvco_reset()
1365 	writel_relaxed(v, clk_base + RST_DFLL_DVCO);  in tegra124_clock_deassert_dfll_dvco_reset()
1418 	clk_base = of_iomap(np, 0);  in tegra124_132_clock_init_pre()
1419 	if (!clk_base) {  in tegra124_132_clock_init_pre()
1438 	clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX,  in tegra124_132_clock_init_pre()
1443 	if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq,  in tegra124_132_clock_init_pre()
1449 	tegra124_pll_init(clk_base, pmc_base);  in tegra124_132_clock_init_pre()
1450 	tegra124_periph_clk_init(clk_base, pmc_base);  in tegra124_132_clock_init_pre()
1451 	tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks,  in tegra124_132_clock_init_pre()
1457 	plld_base = readl(clk_base + PLLD_BASE);  in tegra124_132_clock_init_pre()
1459 	writel(plld_base, clk_base + PLLD_BASE);  in tegra124_132_clock_init_pre()
1474 	tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks,  in tegra124_132_clock_init_post()
1480 	clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np,  in tegra124_132_clock_init_post()