130 static void __iomem *clk_base;  variable
896 static void __init tegra114_fixed_clk_init(void __iomem *clk_base)  in tegra114_fixed_clk_init()  argument
916 static void __init tegra114_pll_init(void __iomem *clk_base,  in tegra114_pll_init()  argument
922 	clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,  in tegra114_pll_init()
928 			clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra114_pll_init()
931 				clk_base + PLLC_OUT, 1, 0,  in tegra114_pll_init()
936 	clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,  in tegra114_pll_init()
941 	clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,  in tegra114_pll_init()
946 	clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,  in tegra114_pll_init()
952 				clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra114_pll_init()
955 				clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |  in tegra114_pll_init()
964 	clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0,  in tegra114_pll_init()
970 				CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,  in tegra114_pll_init()
990 	clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,  in tegra114_pll_init()
1000 	clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0,  in tegra114_pll_init()
1010 	clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,  in tegra114_pll_init()
1015 					 clk_base + PLLRE_BASE, 16, 4, 0,  in tegra114_pll_init()
1021 				      clk_base, 0, &pll_e_params, NULL);  in tegra114_pll_init()
1031 static __init void tegra114_periph_clk_init(void __iomem *clk_base,  in tegra114_periph_clk_init()  argument
1047 			       clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);  in tegra114_periph_clk_init()
1054 			       clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);  in tegra114_periph_clk_init()
1057 	clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,  in tegra114_periph_clk_init()
1061 	clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,  in tegra114_periph_clk_init()
1069 			       clk_base + CLK_SOURCE_EMC,  in tegra114_periph_clk_init()
1072 	clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,  in tegra114_periph_clk_init()
1076 	clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base,  in tegra114_periph_clk_init()
1083 		clk = tegra_clk_register_periph_data(clk_base, data);  in tegra114_periph_clk_init()
1087 	tegra_periph_clk_init(clk_base, pmc_base, tegra114_clks,  in tegra114_periph_clk_init()
1097 		reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);  in tegra114_wait_cpu_in_reset()
1112 				readl(clk_base + CLK_SOURCE_CSITE);  in tegra114_cpu_clock_suspend()
1113 	writel(3 << 30, clk_base + CLK_SOURCE_CSITE);  in tegra114_cpu_clock_suspend()
1116 				readl(clk_base + CCLKG_BURST_POLICY);  in tegra114_cpu_clock_suspend()
1118 				readl(clk_base + CCLKG_BURST_POLICY + 4);  in tegra114_cpu_clock_suspend()
1124 					clk_base + CLK_SOURCE_CSITE);  in tegra114_cpu_clock_resume()
1127 					clk_base + CCLKG_BURST_POLICY);  in tegra114_cpu_clock_resume()
1129 					clk_base + CCLKG_BURST_POLICY + 4);  in tegra114_cpu_clock_resume()
1207 	readl_relaxed(clk_base + CPU_FINETRIM_SELECT);  in tegra114_car_barrier()
1225 	writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);  in tegra114_clock_tune_cpu_trimmers_high()
1252 	writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);  in tegra114_clock_tune_cpu_trimmers_low()
1274 	writel_relaxed(r, clk_base + CPU_FINETRIM_R);  in tegra114_clock_tune_cpu_trimmers_init()
1283 	writel_relaxed(dr, clk_base + CPU_FINETRIM_DR);  in tegra114_clock_tune_cpu_trimmers_init()
1298 	v = readl_relaxed(clk_base + RST_DFLL_DVCO);  in tegra114_clock_assert_dfll_dvco_reset()
1300 	writel_relaxed(v, clk_base + RST_DFLL_DVCO);  in tegra114_clock_assert_dfll_dvco_reset()
1315 	v = readl_relaxed(clk_base + RST_DFLL_DVCO);  in tegra114_clock_deassert_dfll_dvco_reset()
1317 	writel_relaxed(v, clk_base + RST_DFLL_DVCO);  in tegra114_clock_deassert_dfll_dvco_reset()
1326 	clk_base = of_iomap(np, 0);  in tegra114_clock_init()
1327 	if (!clk_base) {  in tegra114_clock_init()
1346 	clks = tegra_clk_init(clk_base, TEGRA114_CLK_CLK_MAX,  in tegra114_clock_init()
1351 	if (tegra_osc_clk_init(clk_base, tegra114_clks, tegra114_input_freq,  in tegra114_clock_init()
1356 	tegra114_fixed_clk_init(clk_base);  in tegra114_clock_init()
1357 	tegra114_pll_init(clk_base, pmc_base);  in tegra114_clock_init()
1358 	tegra114_periph_clk_init(clk_base, pmc_base);  in tegra114_clock_init()
1359 	tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,  in tegra114_clock_init()
1363 	tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,  in tegra114_clock_init()