Lines Matching refs:clk_base
288 static void __iomem *clk_base; variable
491 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_control_enable()
496 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_control_enable()
504 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_sequence_start()
506 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_sequence_start()
514 val = readl_relaxed(clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_control_enable()
518 writel_relaxed(val, clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_control_enable()
526 val = readl_relaxed(clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_sequence_start()
528 writel_relaxed(val, clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_sequence_start()
536 val = readl_relaxed(clk_base + SATA_PLL_CFG0); in tegra210_set_sata_pll_seq_sw()
548 writel_relaxed(val, clk_base + SATA_PLL_CFG0); in tegra210_set_sata_pll_seq_sw()
556 val = readl_relaxed(clk_base + mbist->lvl2_offset); in tegra210_generic_mbist_war()
557 writel_relaxed(val | mbist->lvl2_mask, clk_base + mbist->lvl2_offset); in tegra210_generic_mbist_war()
558 fence_udelay(1, clk_base); in tegra210_generic_mbist_war()
559 writel_relaxed(val, clk_base + mbist->lvl2_offset); in tegra210_generic_mbist_war()
560 fence_udelay(1, clk_base); in tegra210_generic_mbist_war()
570 csi_src = readl_relaxed(clk_base + PLLD_BASE); in tegra210_venc_mbist_war()
571 writel_relaxed(csi_src | PLLD_BASE_CSI_CLKSOURCE, clk_base + PLLD_BASE); in tegra210_venc_mbist_war()
572 fence_udelay(1, clk_base); in tegra210_venc_mbist_war()
574 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA); in tegra210_venc_mbist_war()
575 writel_relaxed(ovra | BIT(15), clk_base + LVL2_CLK_GATE_OVRA); in tegra210_venc_mbist_war()
576 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE); in tegra210_venc_mbist_war()
577 writel_relaxed(ovre | BIT(3), clk_base + LVL2_CLK_GATE_OVRE); in tegra210_venc_mbist_war()
578 fence_udelay(1, clk_base); in tegra210_venc_mbist_war()
580 writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA); in tegra210_venc_mbist_war()
581 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE); in tegra210_venc_mbist_war()
582 writel_relaxed(csi_src, clk_base + PLLD_BASE); in tegra210_venc_mbist_war()
583 fence_udelay(1, clk_base); in tegra210_venc_mbist_war()
592 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA); in tegra210_disp_mbist_war()
593 writel_relaxed(ovra | BIT(1), clk_base + LVL2_CLK_GATE_OVRA); in tegra210_disp_mbist_war()
594 fence_udelay(1, clk_base); in tegra210_disp_mbist_war()
602 writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA); in tegra210_disp_mbist_war()
603 fence_udelay(1, clk_base); in tegra210_disp_mbist_war()
610 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE); in tegra210_vic_mbist_war()
611 writel_relaxed(ovre | BIT(5), clk_base + LVL2_CLK_GATE_OVRE); in tegra210_vic_mbist_war()
612 fence_udelay(1, clk_base); in tegra210_vic_mbist_war()
622 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE); in tegra210_vic_mbist_war()
623 fence_udelay(1, clk_base); in tegra210_vic_mbist_war()
632 ovrc = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRC); in tegra210_ape_mbist_war()
633 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE); in tegra210_ape_mbist_war()
634 writel_relaxed(ovrc | BIT(1), clk_base + LVL2_CLK_GATE_OVRC); in tegra210_ape_mbist_war()
636 clk_base + LVL2_CLK_GATE_OVRE); in tegra210_ape_mbist_war()
637 fence_udelay(1, clk_base); in tegra210_ape_mbist_war()
656 writel_relaxed(ovrc, clk_base + LVL2_CLK_GATE_OVRC); in tegra210_ape_mbist_war()
657 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE); in tegra210_ape_mbist_war()
658 fence_udelay(1, clk_base); in tegra210_ape_mbist_war()
687 _pll_misc_chk_default(clk_base, params, 0, default_val, in pllcx_check_defaults()
691 _pll_misc_chk_default(clk_base, params, 1, default_val, in pllcx_check_defaults()
695 _pll_misc_chk_default(clk_base, params, 2, default_val, in pllcx_check_defaults()
699 _pll_misc_chk_default(clk_base, params, 3, default_val, in pllcx_check_defaults()
708 if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) { in tegra210_pllcx_set_defaults()
719 clk_base + pllcx->params->ext_misc_reg[0]); in tegra210_pllcx_set_defaults()
721 clk_base + pllcx->params->ext_misc_reg[1]); in tegra210_pllcx_set_defaults()
723 clk_base + pllcx->params->ext_misc_reg[2]); in tegra210_pllcx_set_defaults()
725 clk_base + pllcx->params->ext_misc_reg[3]); in tegra210_pllcx_set_defaults()
757 u32 val = readl_relaxed(clk_base + plla->params->base_reg); in tegra210_plla_set_defaults()
775 _pll_misc_chk_default(clk_base, plla->params, 0, val, in tegra210_plla_set_defaults()
779 _pll_misc_chk_default(clk_base, plla->params, 2, val, in tegra210_plla_set_defaults()
783 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
786 writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
794 writel_relaxed(val, clk_base + plla->params->base_reg); in tegra210_plla_set_defaults()
796 clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
798 clk_base + plla->params->ext_misc_reg[2]); in tegra210_plla_set_defaults()
813 if (readl_relaxed(clk_base + plld->params->base_reg) & in tegra210_plld_set_defaults()
821 _pll_misc_chk_default(clk_base, plld->params, 1, in tegra210_plld_set_defaults()
828 _pll_misc_chk_default(clk_base, plld->params, 0, val, in tegra210_plld_set_defaults()
836 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
839 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
845 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
849 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
850 writel_relaxed(PLLD_MISC1_DEFAULT_VALUE, clk_base + in tegra210_plld_set_defaults()
863 u32 val = readl_relaxed(clk_base + plldss->params->base_reg); in plldss_defaults()
880 _pll_misc_chk_default(clk_base, plldss->params, 0, default_val, in plldss_defaults()
891 _pll_misc_chk_default(clk_base, plldss->params, 1, in plldss_defaults()
894 _pll_misc_chk_default(clk_base, plldss->params, 2, in plldss_defaults()
897 _pll_misc_chk_default(clk_base, plldss->params, 3, in plldss_defaults()
901 _pll_misc_chk_default(clk_base, plldss->params, 1, in plldss_defaults()
913 writel_relaxed(val, clk_base + in plldss_defaults()
917 val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]); in plldss_defaults()
920 writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]); in plldss_defaults()
929 writel_relaxed(val, clk_base + plldss->params->base_reg); in plldss_defaults()
933 writel_relaxed(misc0_val, clk_base + in plldss_defaults()
939 writel_relaxed(misc0_val, clk_base + in plldss_defaults()
943 clk_base + plldss->params->ext_misc_reg[1]); in plldss_defaults()
944 writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]); in plldss_defaults()
945 writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]); in plldss_defaults()
982 u32 val = readl_relaxed(clk_base + pllre->params->base_reg); in tegra210_pllre_set_defaults()
1003 _pll_misc_chk_default(clk_base, pllre->params, 0, val, in tegra210_pllre_set_defaults()
1007 val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]); in tegra210_pllre_set_defaults()
1014 writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]); in tegra210_pllre_set_defaults()
1026 writel_relaxed(val, clk_base + pllre->params->base_reg); in tegra210_pllre_set_defaults()
1028 clk_base + pllre->params->ext_misc_reg[0]); in tegra210_pllre_set_defaults()
1072 _pll_misc_chk_default(clk_base, pll->params, 0, default_val, in pllx_check_defaults()
1076 _pll_misc_chk_default(clk_base, pll->params, 1, default_val, in pllx_check_defaults()
1081 _pll_misc_chk_default(clk_base, pll->params, 2, in pllx_check_defaults()
1085 _pll_misc_chk_default(clk_base, pll->params, 3, default_val, in pllx_check_defaults()
1089 _pll_misc_chk_default(clk_base, pll->params, 4, default_val, in pllx_check_defaults()
1093 _pll_misc_chk_default(clk_base, pll->params, 5, default_val, in pllx_check_defaults()
1111 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) { in tegra210_pllx_set_defaults()
1122 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_set_defaults()
1125 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]); in tegra210_pllx_set_defaults()
1128 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]); in tegra210_pllx_set_defaults()
1135 writel_relaxed(PLLX_MISC0_DEFAULT_VALUE, clk_base + in tegra210_pllx_set_defaults()
1139 writel_relaxed(PLLX_MISC1_DEFAULT_VALUE, clk_base + in tegra210_pllx_set_defaults()
1143 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_set_defaults()
1146 writel_relaxed(PLLX_MISC3_DEFAULT_VALUE, clk_base + in tegra210_pllx_set_defaults()
1150 writel_relaxed(PLLX_MISC4_DEFAULT_VALUE, clk_base + in tegra210_pllx_set_defaults()
1152 writel_relaxed(PLLX_MISC5_DEFAULT_VALUE, clk_base + in tegra210_pllx_set_defaults()
1160 u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg); in tegra210_pllmb_set_defaults()
1172 _pll_misc_chk_default(clk_base, pllmb->params, 0, val, in tegra210_pllmb_set_defaults()
1178 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]); in tegra210_pllmb_set_defaults()
1181 writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]); in tegra210_pllmb_set_defaults()
1189 clk_base + pllmb->params->ext_misc_reg[0]); in tegra210_pllmb_set_defaults()
1208 _pll_misc_chk_default(clk_base, pll->params, 0, val, in pllp_check_defaults()
1214 _pll_misc_chk_default(clk_base, pll->params, 1, val, in pllp_check_defaults()
1221 u32 val = readl_relaxed(clk_base + pllp->params->base_reg); in tegra210_pllp_set_defaults()
1236 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1240 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1248 clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1251 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]); in tegra210_pllp_set_defaults()
1255 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]); in tegra210_pllp_set_defaults()
1273 _pll_misc_chk_default(clk_base, params, 0, val, in pllu_check_defaults()
1278 _pll_misc_chk_default(clk_base, params, 1, val, in pllu_check_defaults()
1284 u32 val = readl_relaxed(clk_base + pllu->base_reg); in tegra210_pllu_set_defaults()
1299 val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]); in tegra210_pllu_set_defaults()
1302 writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]); in tegra210_pllu_set_defaults()
1304 val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]); in tegra210_pllu_set_defaults()
1307 writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]); in tegra210_pllu_set_defaults()
1315 clk_base + pllu->ext_misc_reg[0]); in tegra210_pllu_set_defaults()
1317 clk_base + pllu->ext_misc_reg[1]); in tegra210_pllu_set_defaults()
1344 val = readl_relaxed(clk_base + reg); in tegra210_wait_for_mask()
1361 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1364 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1367 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1369 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1375 base = readl_relaxed(clk_base + pllx->params->base_reg) & in tegra210_pllx_dyn_ramp()
1378 writel_relaxed(base, clk_base + pllx->params->base_reg); in tegra210_pllx_dyn_ramp()
1382 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
2710 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_in_iddq()
2718 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_in_iddq()
2726 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_out_iddq()
2728 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_out_iddq()
2748 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2750 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2754 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); in tegra210_utmi_param_configure()
2764 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); in tegra210_utmi_param_configure()
2767 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()
2778 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()
2781 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()
2784 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()
2789 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); in tegra210_utmi_param_configure()
2796 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); in tegra210_utmi_param_configure()
2799 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()
2802 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()
2804 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2807 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2811 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0); in tegra210_utmi_param_configure()
2813 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0); in tegra210_utmi_param_configure()
2818 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2820 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2841 reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]); in tegra210_enable_pllu()
2843 writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]); in tegra210_enable_pllu()
2846 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_enable_pllu()
2851 writel(reg, clk_base + PLLU_BASE); in tegra210_enable_pllu()
2854 writel(reg, clk_base + PLLU_BASE); in tegra210_enable_pllu()
2856 readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg, in tegra210_enable_pllu()
2873 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
2883 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
2885 writel(reg, clk_base + PLLU_BASE); in tegra210_init_pllu()
2887 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); in tegra210_init_pllu()
2893 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); in tegra210_init_pllu()
2895 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0); in tegra210_init_pllu()
2897 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0); in tegra210_init_pllu()
2900 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); in tegra210_init_pllu()
2902 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); in tegra210_init_pllu()
2905 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
2907 writel_relaxed(reg, clk_base + PLLU_BASE); in tegra210_init_pllu()
2911 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_init_pllu()
2949 static __init void tegra210_periph_clk_init(void __iomem *clk_base, in tegra210_periph_clk_init() argument
2960 clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base, in tegra210_periph_clk_init()
2964 clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base, in tegra210_periph_clk_init()
2968 clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base, in tegra210_periph_clk_init()
2974 clk_base + CLK_SOURCE_SOR1, 14, 0x3, in tegra210_periph_clk_init()
2980 clk_base + PLLD_MISC0, 21, 0, &pll_d_lock); in tegra210_periph_clk_init()
2985 clk_base, 0, 48, in tegra210_periph_clk_init()
2991 clk_base, 0, 82, in tegra210_periph_clk_init()
2997 ARRAY_SIZE(la_parents), &tegra210_la, clk_base, in tegra210_periph_clk_init()
3004 clk_base + CLK_SOURCE_EMC, in tegra210_periph_clk_init()
3007 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, in tegra210_periph_clk_init()
3012 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra210_periph_clk_init()
3018 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra210_periph_clk_init()
3024 ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0, in tegra210_periph_clk_init()
3028 clk = tegra_clk_register_sdmmc_mux_div("sdmmc2", clk_base, in tegra210_periph_clk_init()
3033 clk = tegra_clk_register_sdmmc_mux_div("sdmmc4", clk_base, in tegra210_periph_clk_init()
3048 clk = tegra_clk_register_periph_data(clk_base, init); in tegra210_periph_clk_init()
3052 tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params); in tegra210_periph_clk_init()
3055 static void __init tegra210_pll_init(void __iomem *clk_base, in tegra210_pll_init() argument
3061 clk = tegra_clk_register_pllc_tegra210("pll_c", "pll_ref", clk_base, in tegra210_pll_init()
3069 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra210_pll_init()
3072 clk_base + PLLC_OUT, 1, 0, in tegra210_pll_init()
3084 clk = tegra_clk_register_pllc_tegra210("pll_c2", "pll_ref", clk_base, in tegra210_pll_init()
3090 clk = tegra_clk_register_pllc_tegra210("pll_c3", "pll_ref", clk_base, in tegra210_pll_init()
3096 clk = tegra_clk_register_pllm("pll_m", "osc", clk_base, pmc, in tegra210_pll_init()
3102 clk = tegra_clk_register_pllmb("pll_mb", "osc", clk_base, pmc, in tegra210_pll_init()
3123 clk_base + PLLU_BASE, 16, 4, 0, in tegra210_pll_init()
3130 clk_base + PLLU_OUTA, 0, in tegra210_pll_init()
3134 clk_base + PLLU_OUTA, 1, 0, in tegra210_pll_init()
3141 clk_base + PLLU_OUTA, 0, in tegra210_pll_init()
3145 clk_base + PLLU_OUTA, 17, 16, in tegra210_pll_init()
3152 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra210_pll_init()
3159 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra210_pll_init()
3166 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra210_pll_init()
3172 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, in tegra210_pll_init()
3185 clk_base, pmc, 0, in tegra210_pll_init()
3192 clk_base + PLLRE_BASE, 16, 5, 0, in tegra210_pll_init()
3198 clk_base + PLLRE_OUT1, 0, in tegra210_pll_init()
3202 clk_base + PLLRE_OUT1, 1, 0, in tegra210_pll_init()
3208 clk_base, 0, &pll_e_params, NULL); in tegra210_pll_init()
3213 clk = tegra_clk_register_pllre("pll_c4_vco", "pll_ref", clk_base, pmc, in tegra210_pll_init()
3220 clk_base + PLLC4_BASE, 19, 4, 0, in tegra210_pll_init()
3239 clk_base + PLLC4_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra210_pll_init()
3242 clk_base + PLLC4_OUT, 1, 0, in tegra210_pll_init()
3248 clk = tegra_clk_register_pllss_tegra210("pll_dp", "pll_ref", clk_base, in tegra210_pll_init()
3254 clk = tegra_clk_register_pllss_tegra210("pll_d2", "pll_ref", clk_base, in tegra210_pll_init()
3279 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); in tegra210_wait_cpu_in_reset()
3294 readl(clk_base + CLK_SOURCE_CSITE); in tegra210_cpu_clock_suspend()
3295 writel(3 << 30, clk_base + CLK_SOURCE_CSITE); in tegra210_cpu_clock_suspend()
3301 clk_base + CLK_SOURCE_CSITE); in tegra210_cpu_clock_resume()
3400 readl_relaxed(clk_base + RST_DFLL_DVCO); in tegra210_car_barrier()
3412 v = readl_relaxed(clk_base + RST_DFLL_DVCO); in tegra210_clock_assert_dfll_dvco_reset()
3414 writel_relaxed(v, clk_base + RST_DFLL_DVCO); in tegra210_clock_assert_dfll_dvco_reset()
3428 v = readl_relaxed(clk_base + RST_DFLL_DVCO); in tegra210_clock_deassert_dfll_dvco_reset()
3430 writel_relaxed(v, clk_base + RST_DFLL_DVCO); in tegra210_clock_deassert_dfll_dvco_reset()
3440 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_SET); in tegra210_reset_assert()
3452 writel(BIT(21), clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR); in tegra210_reset_deassert()
3460 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR); in tegra210_reset_deassert()
3512 clk_base = of_iomap(np, 0); in tegra210_clock_init()
3513 if (!clk_base) { in tegra210_clock_init()
3550 clks = tegra_clk_init(clk_base, TEGRA210_CLK_CLK_MAX, in tegra210_clock_init()
3555 value = readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT; in tegra210_clock_init()
3558 if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq, in tegra210_clock_init()
3564 tegra210_pll_init(clk_base, pmc_base); in tegra210_clock_init()
3565 tegra210_periph_clk_init(clk_base, pmc_base); in tegra210_clock_init()
3566 tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks, in tegra210_clock_init()
3572 value = readl(clk_base + PLLD_BASE); in tegra210_clock_init()
3574 writel(value, clk_base + PLLD_BASE); in tegra210_clock_init()
3578 tegra_super_clk_gen5_init(clk_base, pmc_base, tegra210_clks, in tegra210_clock_init()