148 static void __iomem *clk_base;  variable
821 	clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,  in tegra30_pll_init()
827 				clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra30_pll_init()
830 				clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,  in tegra30_pll_init()
835 	clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,  in tegra30_pll_init()
841 				clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra30_pll_init()
844 				clk_base + PLLM_OUT, 1, 0,  in tegra30_pll_init()
849 	clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,  in tegra30_pll_init()
859 	clk = tegra_clk_register_pllu("pll_u", "pll_ref", clk_base, 0,  in tegra30_pll_init()
864 	clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,  in tegra30_pll_init()
874 	clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,  in tegra30_pll_init()
887 			       clk_base + PLLE_AUX, 2, 1, 0, NULL);  in tegra30_pll_init()
888 	clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,  in tegra30_pll_init()
913 				clk_base + SUPER_CCLKG_DIVIDER, 0,  in tegra30_super_clk_init()
922 				clk_base + SUPER_CCLKG_DIVIDER, 0,  in tegra30_super_clk_init()
931 				clk_base + SUPER_CCLKG_DIVIDER, 0,  in tegra30_super_clk_init()
939 				  clk_base + CCLKG_BURST_POLICY,  in tegra30_super_clk_init()
948 				clk_base + SUPER_CCLKLP_DIVIDER, 0,  in tegra30_super_clk_init()
957 				clk_base + SUPER_CCLKLP_DIVIDER, 0,  in tegra30_super_clk_init()
966 				clk_base + SUPER_CCLKLP_DIVIDER, 0,  in tegra30_super_clk_init()
974 				  clk_base + CCLKLP_BURST_POLICY,  in tegra30_super_clk_init()
983 				  clk_base + SCLK_BURST_POLICY,  in tegra30_super_clk_init()
992 	tegra_super_clk_gen4_init(clk_base, pmc_base, tegra30_clks, NULL);  in tegra30_super_clk_init()
1032 	clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,  in tegra30_periph_clk_init()
1037 	clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,  in tegra30_periph_clk_init()
1042 	clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,  in tegra30_periph_clk_init()
1050 			       clk_base + CLK_SOURCE_EMC,  in tegra30_periph_clk_init()
1053 	clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,  in tegra30_periph_clk_init()
1058 	clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,  in tegra30_periph_clk_init()
1063 	clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,  in tegra30_periph_clk_init()
1069 		clk = tegra_clk_register_periph_data(clk_base, data);  in tegra30_periph_clk_init()
1078 					clk_base, data->offset);  in tegra30_periph_clk_init()
1082 	tegra_periph_clk_init(clk_base, pmc_base, tegra30_clks, &pll_p_params);  in tegra30_periph_clk_init()
1091 		reg = readl(clk_base +  in tegra30_wait_cpu_in_reset()
1102 	       clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);  in tegra30_put_cpu_in_reset()
1109 	       clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);  in tegra30_cpu_out_of_reset()
1118 	       clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);  in tegra30_enable_cpu_clock()
1119 	reg = readl(clk_base +  in tegra30_enable_cpu_clock()
1127 	reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);  in tegra30_disable_cpu_clock()
1129 	       clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);  in tegra30_disable_cpu_clock()
1138 	cpu_rst_status = readl(clk_base +  in tegra30_cpu_rail_off_ready()
1154 				readl(clk_base + CLK_RESET_SOURCE_CSITE);  in tegra30_cpu_clock_suspend()
1155 	writel(3 << 30, clk_base + CLK_RESET_SOURCE_CSITE);  in tegra30_cpu_clock_suspend()
1158 				readl(clk_base + CLK_RESET_CCLK_BURST);  in tegra30_cpu_clock_suspend()
1160 				readl(clk_base + CLK_RESET_PLLX_BASE);  in tegra30_cpu_clock_suspend()
1162 				readl(clk_base + CLK_RESET_PLLX_MISC);  in tegra30_cpu_clock_suspend()
1164 				readl(clk_base + CLK_RESET_CCLK_DIVIDER);  in tegra30_cpu_clock_suspend()
1172 	reg = readl(clk_base + CLK_RESET_CCLK_BURST);  in tegra30_cpu_clock_resume()
1185 					clk_base + CLK_RESET_PLLX_MISC);  in tegra30_cpu_clock_resume()
1187 					clk_base + CLK_RESET_PLLX_BASE);  in tegra30_cpu_clock_resume()
1199 					clk_base + CLK_RESET_CCLK_DIVIDER);  in tegra30_cpu_clock_resume()
1201 					clk_base + CLK_RESET_CCLK_BURST);  in tegra30_cpu_clock_resume()
1204 					clk_base + CLK_RESET_SOURCE_CSITE);  in tegra30_cpu_clock_resume()
1309 	clk_base = of_iomap(np, 0);  in tegra30_clock_init()
1310 	if (!clk_base) {  in tegra30_clock_init()
1327 	clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX,  in tegra30_clock_init()
1332 	if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq,  in tegra30_clock_init()
1341 	tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,  in tegra30_clock_init()