Lines Matching refs:clk_base
130 static void __iomem *clk_base; variable
574 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); in tegra20_clk_measure_input_freq()
608 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & in tegra20_get_pll_ref_div()
630 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
636 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
639 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, in tegra20_pll_init()
644 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, in tegra20_pll_init()
650 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
653 clk_base + PLLM_OUT, 1, 0, in tegra20_pll_init()
658 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
663 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
668 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
678 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0, in tegra20_pll_init()
684 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
687 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | in tegra20_pll_init()
692 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, in tegra20_pll_init()
711 clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL); in tegra20_super_clk_init()
718 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL); in tegra20_super_clk_init()
738 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL); in tegra20_audio_clk_init()
740 clk_base + AUDIO_SYNC_CLK, 4, in tegra20_audio_clk_init()
748 TEGRA_PERIPH_NO_RESET, clk_base, in tegra20_audio_clk_init()
799 clk_base + CLK_SOURCE_EMC, in tegra20_emc_clk_init()
802 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, in tegra20_emc_clk_init()
807 emc_reg = readl_relaxed(clk_base + CLK_SOURCE_EMC); in tegra20_emc_clk_init()
820 clk_base + CLK_SOURCE_EMC, CLK_IS_CRITICAL, in tegra20_emc_clk_init()
834 clk_base, 0, 3, periph_clk_enb_refcnt); in tegra20_periph_clk_init()
841 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, in tegra20_periph_clk_init()
847 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70, in tegra20_periph_clk_init()
853 0, clk_base + MISC_CLK_ENB, 22, 2, in tegra20_periph_clk_init()
859 0, clk_base + MISC_CLK_ENB, 20, 2, in tegra20_periph_clk_init()
865 clk_base, 0, 94, periph_clk_enb_refcnt); in tegra20_periph_clk_init()
870 clk_base, 0, 93, periph_clk_enb_refcnt); in tegra20_periph_clk_init()
875 clk = tegra_clk_register_periph_data(clk_base, data); in tegra20_periph_clk_init()
884 clk_base, data->offset); in tegra20_periph_clk_init()
888 tegra_periph_clk_init(clk_base, pmc_base, tegra20_clks, &pll_p_params); in tegra20_periph_clk_init()
917 reg = readl(clk_base + in tegra20_wait_cpu_in_reset()
928 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); in tegra20_put_cpu_in_reset()
935 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); in tegra20_cpu_out_of_reset()
943 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); in tegra20_enable_cpu_clock()
945 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); in tegra20_enable_cpu_clock()
947 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); in tegra20_enable_cpu_clock()
954 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); in tegra20_disable_cpu_clock()
956 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); in tegra20_disable_cpu_clock()
964 cpu_rst_status = readl(clk_base + in tegra20_cpu_rail_off_ready()
974 readl(clk_base + CLK_SOURCE_CSITE); in tegra20_cpu_clock_suspend()
975 writel(3<<30, clk_base + CLK_SOURCE_CSITE); in tegra20_cpu_clock_suspend()
978 readl(clk_base + CCLK_BURST_POLICY); in tegra20_cpu_clock_suspend()
980 readl(clk_base + PLLX_BASE); in tegra20_cpu_clock_suspend()
982 readl(clk_base + PLLX_MISC); in tegra20_cpu_clock_suspend()
984 readl(clk_base + SUPER_CCLK_DIVIDER); in tegra20_cpu_clock_suspend()
992 reg = readl(clk_base + CCLK_BURST_POLICY); in tegra20_cpu_clock_resume()
1005 clk_base + PLLX_MISC); in tegra20_cpu_clock_resume()
1007 clk_base + PLLX_BASE); in tegra20_cpu_clock_resume()
1019 clk_base + SUPER_CCLK_DIVIDER); in tegra20_cpu_clock_resume()
1021 clk_base + CCLK_BURST_POLICY); in tegra20_cpu_clock_resume()
1024 clk_base + CLK_SOURCE_CSITE); in tegra20_cpu_clock_resume()
1141 clk_base = of_iomap(np, 0); in tegra20_clock_init()
1142 if (!clk_base) { in tegra20_clock_init()
1159 clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX, in tegra20_clock_init()
1168 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL); in tegra20_clock_init()