| /Linux-v5.10/drivers/clk/bcm/ |
| D | clk-iproc-asiu.c | 16 #include <linux/clk-provider.h>
23 #include "clk-iproc.h"
32 struct iproc_asiu_div div; member
48 struct iproc_asiu_clk *clk = to_asiu_clk(hw); in iproc_asiu_clk_enable() local
49 struct iproc_asiu *asiu = clk->asiu; in iproc_asiu_clk_enable()
53 if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET) in iproc_asiu_clk_enable()
56 val = readl(asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
57 val |= (1 << clk->gate.en_shift); in iproc_asiu_clk_enable()
58 writel(val, asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
65 struct iproc_asiu_clk *clk = to_asiu_clk(hw); in iproc_asiu_clk_disable() local
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| /Linux-v5.10/drivers/clk/meson/ |
| D | clk-regmap.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include "clk-regmap.h"
12 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_gate_endisable() local
13 struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk); in clk_regmap_gate_endisable()
14 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; in clk_regmap_gate_endisable()
18 return regmap_update_bits(clk->map, gate->offset, BIT(gate->bit_idx), in clk_regmap_gate_endisable()
19 set ? BIT(gate->bit_idx) : 0); in clk_regmap_gate_endisable()
34 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_gate_is_enabled() local
35 struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk); in clk_regmap_gate_is_enabled()
38 regmap_read(clk->map, gate->offset, &val); in clk_regmap_gate_is_enabled()
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| D | clk-cpu-dyndiv.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <linux/clk-provider.h>
10 #include "clk-regmap.h"
11 #include "clk-cpu-dyndiv.h"
14 meson_clk_cpu_dyndiv_data(struct clk_regmap *clk) in meson_clk_cpu_dyndiv_data() argument
16 return (struct meson_clk_cpu_dyndiv_data *)clk->data; in meson_clk_cpu_dyndiv_data()
22 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_cpu_dyndiv_recalc_rate() local
23 struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk); in meson_clk_cpu_dyndiv_recalc_rate()
26 meson_parm_read(clk->map, &data->div), in meson_clk_cpu_dyndiv_recalc_rate()
27 NULL, 0, data->div.width); in meson_clk_cpu_dyndiv_recalc_rate()
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| D | sclk-div.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
15 * hi = [0 - val]
19 #include <linux/clk-provider.h>
22 #include "clk-regmap.h"
23 #include "sclk-div.h"
26 meson_sclk_div_data(struct clk_regmap *clk) in meson_sclk_div_data() argument
28 return (struct meson_sclk_div_data *)clk->data; in meson_sclk_div_data()
33 return (1 << sclk->div.width) - 1; in sclk_div_maxval()
44 int div = DIV_ROUND_CLOSEST_ULL((u64)prate, rate); in sclk_div_getdiv() local
46 return clamp(div, 2, maxdiv); in sclk_div_getdiv()
[all …]
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| /Linux-v5.10/drivers/clk/spear/ |
| D | spear1340_clock.c | 2 * arch/arm/mach-spear13xx/spear1340_clock.c
19 #include "clk.h"
178 /* vco-pll4 rate configuration table, in ascending order of rates */
191 {.div = 0x073A8}, /* for vco1div2 = 600 MHz */
192 {.div = 0x06062}, /* for vco1div2 = 500 MHz */
193 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
194 {.div = 0x04000}, /* for vco1div2 = 332 MHz */
195 {.div = 0x03031}, /* for vco1div2 = 250 MHz */
196 {.div = 0x0268D}, /* for vco1div2 = 200 MHz */
208 * --------------------------------------------------------------------
[all …]
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| D | clk-frac-synth.c | 12 #define pr_fmt(fmt) "clk-frac-synth: " fmt
14 #include <linux/clk-provider.h>
18 #include "clk.h"
27 * Fout= Fin/2*div (division factor)
28 * div is 17 bits:-
29 * 0-13 (fractional part)
30 * 14-16 (integer part)
31 * div is (16-14 bits).(13-0 bits) (in binary)
33 * Fout = Fin/(2 * div)
34 * Fout = ((Fin / 10000)/(2 * div)) * 10000
[all …]
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| /Linux-v5.10/arch/c6x/platforms/ |
| D | plldata.c | 1 // SPDX-License-Identifier: GPL-2.0-only
27 struct clk clkin1 = {
127 struct clk c6x_core_clk = {
132 struct clk c6x_i2c_clk = {
136 struct clk c6x_watchdog_clk = {
140 struct clk c6x_mcbsp1_clk = {
144 struct clk c6x_mcbsp2_clk = {
148 struct clk c6x_mdio_clk = {
155 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
156 CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
[all …]
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| /Linux-v5.10/drivers/clk/mxs/ |
| D | clk-div.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
9 #include "clk.h"
12 * struct clk_div - mxs integer divider clock
38 struct clk_div *div = to_clk_div(hw); in clk_div_recalc_rate() local
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
46 struct clk_div *div = to_clk_div(hw); in clk_div_round_rate() local
48 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
54 struct clk_div *div = to_clk_div(hw); in clk_div_set_rate() local
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
[all …]
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| /Linux-v5.10/drivers/clk/sunxi/ |
| D | clk-sunxi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
35 u8 div; in sun4i_get_pll1_factors() local
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
[all …]
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| D | clk-sun9i-cpus.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
22 * sun9i_a80_cpus_clk_setup() - Setup function for a80 cpus composite clk
36 #define SUN9I_CPUS_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_DIV_MASK) | \ argument
37 (div << SUN9I_CPUS_DIV_SHIFT))
42 #define SUN9I_CPUS_PLL4_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_PLL4_DIV_MASK) | \ argument
43 (div << SUN9I_CPUS_PLL4_DIV_SHIFT))
[all …]
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| D | clk-sun6i-ar100.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
11 #include <linux/clk-provider.h>
17 #include "clk-factors.h"
20 * sun6i_get_ar100_factors - Calculates factors p, m for AR100
27 unsigned long div; in sun6i_get_ar100_factors() local
31 if (req->rate > req->parent_rate) in sun6i_get_ar100_factors()
32 req->rate = req->parent_rate; in sun6i_get_ar100_factors()
34 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun6i_get_ar100_factors()
36 if (div < 32) in sun6i_get_ar100_factors()
[all …]
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| D | clk-sun8i-mbus.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2014 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
28 const char *clk_name = node->name; in sun8i_a23_mbus_setup()
30 struct clk_divider *div; in sun8i_a23_mbus_setup() local
33 struct clk *clk; in sun8i_a23_mbus_setup() local
43 pr_err("Could not get registers for sun8i-mbus-clk\n"); in sun8i_a23_mbus_setup()
47 div = kzalloc(sizeof(*div), GFP_KERNEL); in sun8i_a23_mbus_setup()
[all …]
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| /Linux-v5.10/drivers/clk/rockchip/ |
| D | clk.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
11 * samsung/clk.c
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
25 #include "clk.h"
31 * src1 --|--\
32 * |M |--[GATE]-[DIV]-
33 * src2 --|--/
37 static struct clk *rockchip_clk_register_branch(const char *name, in rockchip_clk_register_branch()
[all …]
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| /Linux-v5.10/drivers/mmc/host/ |
| D | meson-mx-sdhc-clkc.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
13 #include "meson-mx-sdhc.h"
19 struct clk_divider div; member
34 { .div = 6, .val = 5, },
35 { .div = 8, .val = 7, },
36 { .div = 9, .val = 8, },
37 { .div = 10, .val = 9, },
38 { .div = 12, .val = 11, },
[all …]
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| /Linux-v5.10/drivers/clk/tegra/ |
| D | clk-divider.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
12 #include "clk.h"
14 #define pll_out_override(p) (BIT((p->shift - 6)))
15 #define div_mask(d) ((1 << (d->width)) - 1)
16 #define get_mul(d) (1 << d->frac_width)
24 int div; in get_div() local
26 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
27 divider->frac_width, divider->flags); in get_div()
29 if (div < 0) in get_div()
[all …]
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| D | clk-tegra20-emc.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Based on drivers/clk/tegra/clk-emc.c
7 * Copyright (C) 2019 GRATE-DRIVER project
10 #define pr_fmt(fmt) "tegra-emc-clk: " fmt
13 #include <linux/clk-provider.h>
14 #include <linux/clk/tegra.h>
20 #include "clk.h"
57 u32 val, div; in emc_recalc_rate() local
59 val = readl_relaxed(emc->reg); in emc_recalc_rate()
60 div = val & CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK; in emc_recalc_rate()
[all …]
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| D | clk-sdmmc-mux.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * based on clk-mux.c
9 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
13 #include <linux/clk-provider.h>
18 #include "clk.h"
50 val = readl_relaxed(sdmmc_mux->reg); in clk_sdmmc_mux_get_parent()
73 val = readl_relaxed(sdmmc_mux->reg); in clk_sdmmc_mux_set_parent()
82 writel(val, sdmmc_mux->reg); in clk_sdmmc_mux_set_parent()
92 int div; in clk_sdmmc_mux_recalc_rate() local
95 val = readl_relaxed(sdmmc_mux->reg); in clk_sdmmc_mux_recalc_rate()
[all …]
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| /Linux-v5.10/drivers/clk/ |
| D | clk-qoriq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
31 #define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
37 struct clk *clk; member
42 struct clockgen_pll_div div[MAX_PLL_DIV]; member
51 int div; /* PLL_DIVn */ member
80 int cmux_to_group[NUM_CMUX + 1]; /* array should be -1 terminated */
89 struct clk *sysclk, *coreclk;
91 struct clk *cmux[NUM_CMUX];
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| D | clk-fixed-factor.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
19 * parent - fixed parent. No clk_set_parent support
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
29 do_div(rate, fix->div); in clk_factor_recalc_rate()
41 best_parent = (rate / fix->mult) * fix->div; in clk_factor_round_rate()
45 return (*prate / fix->div) * fix->mult; in clk_factor_round_rate()
[all …]
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| /Linux-v5.10/drivers/clk/ti/ |
| D | divider.c | 6 * Tero Kristo <t-kristo@ti.com>
18 #include <linux/clk-provider.h>
23 #include <linux/clk/ti.h>
34 for (clkt = table; clkt->div; clkt++) in _get_table_div()
35 if (clkt->val == val) in _get_table_div()
36 return clkt->div; in _get_table_div()
46 if (divider->table) { in _setup_mask()
49 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
50 if (clkt->val > max_val) in _setup_mask()
51 max_val = clkt->val; in _setup_mask()
[all …]
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| /Linux-v5.10/drivers/clk/hisilicon/ |
| D | clkdivider-hi6220.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
17 #include "clk.h"
19 #define div_mask(width) ((1 << (width)) - 1)
22 * struct hi6220_clk_divider - divider clock for hi6220
24 * @hw: handle between common and hardware-specific interfaces
29 * @table: the div table that the divider supports
51 val = readl_relaxed(dclk->reg) >> dclk->shift; in hi6220_clkdiv_recalc_rate()
52 val &= div_mask(dclk->width); in hi6220_clkdiv_recalc_rate()
54 return divider_recalc_rate(hw, parent_rate, val, dclk->table, in hi6220_clkdiv_recalc_rate()
[all …]
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| /Linux-v5.10/drivers/clk/renesas/ |
| D | rcar-gen2-cpg.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen2 Clock Pulse Generator
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
18 #include "renesas-cpg-mssr.h"
19 #include "rcar-gen2-cpg.h"
39 * prepare - clk_prepare only ensures that parents are prepared
40 * enable - clk_enable only ensures that parents are enabled
41 * rate - rate is adjustable. clk->rate = parent->rate * mult / 32
42 * parent - fixed parent. No clk_set_parent support
[all …]
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| D | rcar-gen3-cpg.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-gen3-cpg.h"
63 csn->saved = readl(csn->reg); in cpg_simple_notifier_call()
67 writel(csn->saved, csn->reg); in cpg_simple_notifier_call()
[all …]
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| /Linux-v5.10/drivers/clk/mediatek/ |
| D | clk-mtk.c | 1 // SPDX-License-Identifier: GPL-2.0-only
17 #include "clk-mtk.h"
18 #include "clk-gate.h"
29 clk_data->clks = kcalloc(clk_num, sizeof(*clk_data->clks), GFP_KERNEL); in mtk_alloc_clk_data()
30 if (!clk_data->clks) in mtk_alloc_clk_data()
33 clk_data->clk_num = clk_num; in mtk_alloc_clk_data()
36 clk_data->clks[i] = ERR_PTR(-ENOENT); in mtk_alloc_clk_data()
49 struct clk *clk; in mtk_clk_register_fixed_clks() local
54 if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[rc->id])) in mtk_clk_register_fixed_clks()
57 clk = clk_register_fixed_rate(NULL, rc->name, rc->parent, 0, in mtk_clk_register_fixed_clks()
[all …]
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| /Linux-v5.10/drivers/clk/pistachio/ |
| D | clk.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
13 #include "clk.h"
24 p->clk_data.clks = kcalloc(num_clks, sizeof(struct clk *), GFP_KERNEL); in pistachio_clk_alloc_provider()
25 if (!p->clk_data.clks) in pistachio_clk_alloc_provider()
27 p->clk_data.clk_num = num_clks; in pistachio_clk_alloc_provider()
28 p->node = node; in pistachio_clk_alloc_provider()
29 p->base = of_iomap(node, 0); in pistachio_clk_alloc_provider()
30 if (!p->base) { in pistachio_clk_alloc_provider()
[all …]
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