1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
12 #include "clk.h"
14 #define pll_out_override(p) (BIT((p->shift - 6)))
15 #define div_mask(d) ((1 << (d->width)) - 1)
16 #define get_mul(d) (1 << d->frac_width)
24 	int div;  in get_div()  local
26 	div = div_frac_get(rate, parent_rate, divider->width,  in get_div()
27 			   divider->frac_width, divider->flags);  in get_div()
29 	if (div < 0)  in get_div()
32 	return div;  in get_div()
40 	int div, mul;  in clk_frac_div_recalc_rate()  local
43 	reg = readl_relaxed(divider->reg);  in clk_frac_div_recalc_rate()
45 	if ((divider->flags & TEGRA_DIVIDER_UART) &&  in clk_frac_div_recalc_rate()
49 	div = (reg >> divider->shift) & div_mask(divider);  in clk_frac_div_recalc_rate()
52 	div += mul;  in clk_frac_div_recalc_rate()
55 	rate += div - 1;  in clk_frac_div_recalc_rate()
56 	do_div(rate, div);  in clk_frac_div_recalc_rate()
65 	int div, mul;  in clk_frac_div_round_rate()  local
71 	div = get_div(divider, rate, output_rate);  in clk_frac_div_round_rate()
72 	if (div < 0)  in clk_frac_div_round_rate()
77 	return DIV_ROUND_UP(output_rate * mul, div + mul);  in clk_frac_div_round_rate()
84 	int div;  in clk_frac_div_set_rate()  local
88 	div = get_div(divider, rate, parent_rate);  in clk_frac_div_set_rate()
89 	if (div < 0)  in clk_frac_div_set_rate()
90 		return div;  in clk_frac_div_set_rate()
92 	if (divider->lock)  in clk_frac_div_set_rate()
93 		spin_lock_irqsave(divider->lock, flags);  in clk_frac_div_set_rate()
95 	val = readl_relaxed(divider->reg);  in clk_frac_div_set_rate()
96 	val &= ~(div_mask(divider) << divider->shift);  in clk_frac_div_set_rate()
97 	val |= div << divider->shift;  in clk_frac_div_set_rate()
99 	if (divider->flags & TEGRA_DIVIDER_UART) {  in clk_frac_div_set_rate()
100 		if (div)  in clk_frac_div_set_rate()
106 	if (divider->flags & TEGRA_DIVIDER_FIXED)  in clk_frac_div_set_rate()
109 	writel_relaxed(val, divider->reg);  in clk_frac_div_set_rate()
111 	if (divider->lock)  in clk_frac_div_set_rate()
112 		spin_unlock_irqrestore(divider->lock, flags);  in clk_frac_div_set_rate()
134 struct clk *tegra_clk_register_divider(const char *name,  in tegra_clk_register_divider()
140 	struct clk *clk;  in tegra_clk_register_divider()  local
145 		pr_err("%s: could not allocate fractional divider clk\n",  in tegra_clk_register_divider()
147 		return ERR_PTR(-ENOMEM);  in tegra_clk_register_divider()
156 	divider->reg = reg;  in tegra_clk_register_divider()
157 	divider->shift = shift;  in tegra_clk_register_divider()
158 	divider->width = width;  in tegra_clk_register_divider()
159 	divider->frac_width = frac_width;  in tegra_clk_register_divider()
160 	divider->lock = lock;  in tegra_clk_register_divider()
161 	divider->flags = clk_divider_flags;  in tegra_clk_register_divider()
164 	divider->hw.init = &init;  in tegra_clk_register_divider()
166 	clk = clk_register(NULL, &divider->hw);  in tegra_clk_register_divider()
167 	if (IS_ERR(clk))  in tegra_clk_register_divider()
170 	return clk;  in tegra_clk_register_divider()
174 	{ .val = 0, .div = 2 },
175 	{ .val = 1, .div = 1 },
176 	{ .val = 0, .div = 0 },
179 struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,  in tegra_clk_register_mc()