1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <linux/clk-provider.h>
10 #include "clk-regmap.h"
11 #include "clk-cpu-dyndiv.h"
14 meson_clk_cpu_dyndiv_data(struct clk_regmap *clk)  in meson_clk_cpu_dyndiv_data()  argument
16 	return (struct meson_clk_cpu_dyndiv_data *)clk->data;  in meson_clk_cpu_dyndiv_data()
22 	struct clk_regmap *clk = to_clk_regmap(hw);  in meson_clk_cpu_dyndiv_recalc_rate()  local
23 	struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);  in meson_clk_cpu_dyndiv_recalc_rate()
26 				   meson_parm_read(clk->map, &data->div),  in meson_clk_cpu_dyndiv_recalc_rate()
27 				   NULL, 0, data->div.width);  in meson_clk_cpu_dyndiv_recalc_rate()
34 	struct clk_regmap *clk = to_clk_regmap(hw);  in meson_clk_cpu_dyndiv_round_rate()  local
35 	struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);  in meson_clk_cpu_dyndiv_round_rate()
37 	return divider_round_rate(hw, rate, prate, NULL, data->div.width, 0);  in meson_clk_cpu_dyndiv_round_rate()
43 	struct clk_regmap *clk = to_clk_regmap(hw);  in meson_clk_cpu_dyndiv_set_rate()  local
44 	struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);  in meson_clk_cpu_dyndiv_set_rate()
48 	ret = divider_get_val(rate, parent_rate, NULL, data->div.width, 0);  in meson_clk_cpu_dyndiv_set_rate()
52 	val = (unsigned int)ret << data->div.shift;  in meson_clk_cpu_dyndiv_set_rate()
55 	meson_parm_write(clk->map, &data->dyn, 1);  in meson_clk_cpu_dyndiv_set_rate()
58 	return regmap_update_bits(clk->map, data->div.reg_off,  in meson_clk_cpu_dyndiv_set_rate()
59 				  SETPMASK(data->div.width, data->div.shift) |  in meson_clk_cpu_dyndiv_set_rate()
60 				  SETPMASK(data->dyn.width, data->dyn.shift),  in meson_clk_cpu_dyndiv_set_rate()