Lines Matching +full:clk +full:- +full:div
1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
35 u8 div; in sun4i_get_pll1_factors() local
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
45 if (req->rate >= 768000000 || req->rate == 42000000 || in sun4i_get_pll1_factors()
46 req->rate == 54000000) in sun4i_get_pll1_factors()
47 req->k = 1; in sun4i_get_pll1_factors()
49 req->k = 0; in sun4i_get_pll1_factors()
52 if (div < 10) in sun4i_get_pll1_factors()
53 req->p = 3; in sun4i_get_pll1_factors()
55 /* p will be 2 for divs between 10 - 20 and odd divs under 32 */ in sun4i_get_pll1_factors()
56 else if (div < 20 || (div < 32 && (div & 1))) in sun4i_get_pll1_factors()
57 req->p = 2; in sun4i_get_pll1_factors()
60 * of divs between 40-62 */ in sun4i_get_pll1_factors()
61 else if (div < 40 || (div < 64 && (div & 2))) in sun4i_get_pll1_factors()
62 req->p = 1; in sun4i_get_pll1_factors()
66 req->p = 0; in sun4i_get_pll1_factors()
69 div <<= req->p; in sun4i_get_pll1_factors()
70 div /= (req->k + 1); in sun4i_get_pll1_factors()
71 req->n = div / 4; in sun4i_get_pll1_factors()
75 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
86 u32 freq_mhz = req->rate / 1000000; in sun6i_a31_get_pll1_factors()
87 u32 parent_freq_mhz = req->parent_rate / 1000000; in sun6i_a31_get_pll1_factors()
101 req->rate = freq_mhz * 1000000; in sun6i_a31_get_pll1_factors()
105 req->k = 3; in sun6i_a31_get_pll1_factors()
108 req->k = 2; in sun6i_a31_get_pll1_factors()
111 req->k = 1; in sun6i_a31_get_pll1_factors()
114 req->k = 0; in sun6i_a31_get_pll1_factors()
125 req->m = 2; in sun6i_a31_get_pll1_factors()
131 req->m = 3; in sun6i_a31_get_pll1_factors()
134 req->m = 1; in sun6i_a31_get_pll1_factors()
137 req->n = freq_mhz * (req->m + 1) / ((req->k + 1) * parent_freq_mhz) in sun6i_a31_get_pll1_factors()
138 - 1; in sun6i_a31_get_pll1_factors()
144 if ((req->n + 1) > 31 && (req->m + 1) > 1) { in sun6i_a31_get_pll1_factors()
145 req->n = (req->n + 1) / 2 - 1; in sun6i_a31_get_pll1_factors()
146 req->m = (req->m + 1) / 2 - 1; in sun6i_a31_get_pll1_factors()
151 * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
159 u8 div; in sun8i_a23_get_pll1_factors() local
162 div = req->rate / 6000000; in sun8i_a23_get_pll1_factors()
163 req->rate = 6000000 * div; in sun8i_a23_get_pll1_factors()
166 req->m = 0; in sun8i_a23_get_pll1_factors()
169 if (req->rate >= 768000000 || req->rate == 42000000 || in sun8i_a23_get_pll1_factors()
170 req->rate == 54000000) in sun8i_a23_get_pll1_factors()
171 req->k = 1; in sun8i_a23_get_pll1_factors()
173 req->k = 0; in sun8i_a23_get_pll1_factors()
176 if (div < 20 || (div < 32 && (div & 1))) in sun8i_a23_get_pll1_factors()
177 req->p = 2; in sun8i_a23_get_pll1_factors()
180 * of divs between 40-62 */ in sun8i_a23_get_pll1_factors()
181 else if (div < 40 || (div < 64 && (div & 2))) in sun8i_a23_get_pll1_factors()
182 req->p = 1; in sun8i_a23_get_pll1_factors()
186 req->p = 0; in sun8i_a23_get_pll1_factors()
189 div <<= req->p; in sun8i_a23_get_pll1_factors()
190 div /= (req->k + 1); in sun8i_a23_get_pll1_factors()
191 req->n = div / 4 - 1; in sun8i_a23_get_pll1_factors()
195 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
203 u8 div; in sun4i_get_pll5_factors() local
206 div = req->rate / req->parent_rate; in sun4i_get_pll5_factors()
207 req->rate = req->parent_rate * div; in sun4i_get_pll5_factors()
209 if (div < 31) in sun4i_get_pll5_factors()
210 req->k = 0; in sun4i_get_pll5_factors()
211 else if (div / 2 < 31) in sun4i_get_pll5_factors()
212 req->k = 1; in sun4i_get_pll5_factors()
213 else if (div / 3 < 31) in sun4i_get_pll5_factors()
214 req->k = 2; in sun4i_get_pll5_factors()
216 req->k = 3; in sun4i_get_pll5_factors()
218 req->n = DIV_ROUND_UP(div, (req->k + 1)); in sun4i_get_pll5_factors()
222 * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2
230 u8 div; in sun6i_a31_get_pll6_factors() local
233 div = req->rate / req->parent_rate; in sun6i_a31_get_pll6_factors()
234 req->rate = req->parent_rate * div; in sun6i_a31_get_pll6_factors()
236 req->k = div / 32; in sun6i_a31_get_pll6_factors()
237 if (req->k > 3) in sun6i_a31_get_pll6_factors()
238 req->k = 3; in sun6i_a31_get_pll6_factors()
240 req->n = DIV_ROUND_UP(div, (req->k + 1)) - 1; in sun6i_a31_get_pll6_factors()
244 * sun5i_a13_get_ahb_factors() - calculates m, p factors for AHB
251 u32 div; in sun5i_a13_get_ahb_factors() local
254 if (req->parent_rate < req->rate) in sun5i_a13_get_ahb_factors()
255 req->rate = req->parent_rate; in sun5i_a13_get_ahb_factors()
261 if (req->rate < 8000) in sun5i_a13_get_ahb_factors()
262 req->rate = 8000; in sun5i_a13_get_ahb_factors()
263 if (req->rate > 300000000) in sun5i_a13_get_ahb_factors()
264 req->rate = 300000000; in sun5i_a13_get_ahb_factors()
266 div = order_base_2(DIV_ROUND_UP(req->parent_rate, req->rate)); in sun5i_a13_get_ahb_factors()
269 if (div > 3) in sun5i_a13_get_ahb_factors()
270 div = 3; in sun5i_a13_get_ahb_factors()
272 req->rate = req->parent_rate >> div; in sun5i_a13_get_ahb_factors()
274 req->p = div; in sun5i_a13_get_ahb_factors()
280 * sun6i_a31_get_ahb_factors() - calculates m, p factors for AHB
290 u8 div, calcp, calcm = 1; in sun6i_get_ahb1_factors() local
296 if (req->parent_rate && req->rate > req->parent_rate) in sun6i_get_ahb1_factors()
297 req->rate = req->parent_rate; in sun6i_get_ahb1_factors()
299 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun6i_get_ahb1_factors()
301 /* calculate pre-divider if parent is pll6 */ in sun6i_get_ahb1_factors()
302 if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) { in sun6i_get_ahb1_factors()
303 if (div < 4) in sun6i_get_ahb1_factors()
305 else if (div / 2 < 4) in sun6i_get_ahb1_factors()
307 else if (div / 4 < 4) in sun6i_get_ahb1_factors()
312 calcm = DIV_ROUND_UP(div, 1 << calcp); in sun6i_get_ahb1_factors()
314 calcp = __roundup_pow_of_two(div); in sun6i_get_ahb1_factors()
318 req->rate = (req->parent_rate / calcm) >> calcp; in sun6i_get_ahb1_factors()
319 req->p = calcp; in sun6i_get_ahb1_factors()
320 req->m = calcm - 1; in sun6i_get_ahb1_factors()
324 * sun6i_ahb1_recalc() - calculates AHB clock rate from m, p factors and
329 req->rate = req->parent_rate; in sun6i_ahb1_recalc()
331 /* apply pre-divider first if parent is pll6 */ in sun6i_ahb1_recalc()
332 if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) in sun6i_ahb1_recalc()
333 req->rate /= req->m + 1; in sun6i_ahb1_recalc()
335 /* clk divider */ in sun6i_ahb1_recalc()
336 req->rate >>= req->p; in sun6i_ahb1_recalc()
340 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
348 int div; in sun4i_get_apb1_factors() local
350 if (req->parent_rate < req->rate) in sun4i_get_apb1_factors()
351 req->rate = req->parent_rate; in sun4i_get_apb1_factors()
353 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun4i_get_apb1_factors()
356 if (div > 32) in sun4i_get_apb1_factors()
359 if (div <= 4) in sun4i_get_apb1_factors()
361 else if (div <= 8) in sun4i_get_apb1_factors()
363 else if (div <= 16) in sun4i_get_apb1_factors()
368 calcm = (div >> calcp) - 1; in sun4i_get_apb1_factors()
370 req->rate = (req->parent_rate >> calcp) / (calcm + 1); in sun4i_get_apb1_factors()
371 req->m = calcm; in sun4i_get_apb1_factors()
372 req->p = calcp; in sun4i_get_apb1_factors()
379 * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
386 u8 div, calcm, calcp; in sun7i_a20_get_out_factors() local
390 if (req->rate > req->parent_rate) in sun7i_a20_get_out_factors()
391 req->rate = req->parent_rate; in sun7i_a20_get_out_factors()
393 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun7i_a20_get_out_factors()
395 if (div < 32) in sun7i_a20_get_out_factors()
397 else if (div / 2 < 32) in sun7i_a20_get_out_factors()
399 else if (div / 4 < 32) in sun7i_a20_get_out_factors()
404 calcm = DIV_ROUND_UP(div, 1 << calcp); in sun7i_a20_get_out_factors()
406 req->rate = (req->parent_rate >> calcp) / calcm; in sun7i_a20_get_out_factors()
407 req->m = calcm - 1; in sun7i_a20_get_out_factors()
408 req->p = calcp; in sun7i_a20_get_out_factors()
412 * sunxi_factors_clk_setup() - Setup function for factor clocks
556 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node, in sunxi_factors_clk_setup()
563 pr_err("Could not get registers for factors-clk: %pOFn\n", in sunxi_factors_clk_setup()
575 CLK_OF_DECLARE(sun4i_pll1, "allwinner,sun4i-a10-pll1-clk",
582 CLK_OF_DECLARE(sun6i_pll1, "allwinner,sun6i-a31-pll1-clk",
589 CLK_OF_DECLARE(sun8i_pll1, "allwinner,sun8i-a23-pll1-clk",
596 CLK_OF_DECLARE(sun7i_pll4, "allwinner,sun7i-a20-pll4-clk",
603 CLK_OF_DECLARE(sun5i_ahb, "allwinner,sun5i-a13-ahb-clk",
610 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk",
617 CLK_OF_DECLARE(sun4i_apb1, "allwinner,sun4i-a10-apb1-clk",
624 CLK_OF_DECLARE(sun7i_out, "allwinner,sun7i-a20-out-clk",
629 * sunxi_mux_clk_setup() - Setup function for muxes
650 static struct clk * __init sunxi_mux_clk_setup(struct device_node *node, in sunxi_mux_clk_setup()
654 struct clk *clk; in sunxi_mux_clk_setup() local
655 const char *clk_name = node->name; in sunxi_mux_clk_setup()
662 pr_err("Could not map registers for mux-clk: %pOF\n", node); in sunxi_mux_clk_setup()
667 if (of_property_read_string(node, "clock-output-names", &clk_name)) { in sunxi_mux_clk_setup()
668 pr_err("%s: could not read clock-output-names from \"%pOF\"\n", in sunxi_mux_clk_setup()
673 clk = clk_register_mux(NULL, clk_name, parents, i, in sunxi_mux_clk_setup()
675 data->shift, SUNXI_MUX_GATE_WIDTH, in sunxi_mux_clk_setup()
678 if (IS_ERR(clk)) { in sunxi_mux_clk_setup()
680 clk_name, PTR_ERR(clk)); in sunxi_mux_clk_setup()
684 if (of_clk_add_provider(node, of_clk_src_simple_get, clk)) { in sunxi_mux_clk_setup()
687 clk_unregister_divider(clk); in sunxi_mux_clk_setup()
691 return clk; in sunxi_mux_clk_setup()
702 CLK_OF_DECLARE(sun4i_cpu, "allwinner,sun4i-a10-cpu-clk",
709 CLK_OF_DECLARE(sun6i_ahb1_mux, "allwinner,sun6i-a31-ahb1-mux-clk",
716 CLK_OF_DECLARE(sun8i_ahb2, "allwinner,sun8i-h3-ahb2-clk",
721 * sunxi_divider_clk_setup() - Setup function for simple divider clocks
738 { .val = 0, .div = 1 },
739 { .val = 1, .div = 2 },
740 { .val = 2, .div = 3 },
741 { .val = 3, .div = 4 },
742 { .val = 4, .div = 4 },
743 { .val = 5, .div = 4 },
744 { .val = 6, .div = 4 },
745 { .val = 7, .div = 4 },
761 { .val = 0, .div = 2 },
762 { .val = 1, .div = 2 },
763 { .val = 2, .div = 4 },
764 { .val = 3, .div = 8 },
778 struct clk *clk; in sunxi_divider_clk_setup() local
779 const char *clk_name = node->name; in sunxi_divider_clk_setup()
785 pr_err("Could not map registers for mux-clk: %pOF\n", node); in sunxi_divider_clk_setup()
791 if (of_property_read_string(node, "clock-output-names", &clk_name)) { in sunxi_divider_clk_setup()
792 pr_err("%s: could not read clock-output-names from \"%pOF\"\n", in sunxi_divider_clk_setup()
797 clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0, in sunxi_divider_clk_setup()
798 reg, data->shift, data->width, in sunxi_divider_clk_setup()
799 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0, in sunxi_divider_clk_setup()
800 data->table, &clk_lock); in sunxi_divider_clk_setup()
801 if (IS_ERR(clk)) { in sunxi_divider_clk_setup()
803 __func__, clk_name, PTR_ERR(clk)); in sunxi_divider_clk_setup()
807 if (of_clk_add_provider(node, of_clk_src_simple_get, clk)) { in sunxi_divider_clk_setup()
813 if (clk_register_clkdev(clk, clk_name, NULL)) { in sunxi_divider_clk_setup()
820 clk_unregister_divider(clk); in sunxi_divider_clk_setup()
830 CLK_OF_DECLARE(sun4i_ahb, "allwinner,sun4i-a10-ahb-clk",
837 CLK_OF_DECLARE(sun4i_apb0, "allwinner,sun4i-a10-apb0-clk",
844 CLK_OF_DECLARE(sun4i_axi, "allwinner,sun4i-a10-axi-clk",
851 CLK_OF_DECLARE(sun8i_axi, "allwinner,sun8i-a23-axi-clk",
857 * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
887 u8 pow; /* is it power-of-two based? */
890 } div[SUNXI_DIVS_MAX_QTY]; member
894 { .val = 0, .div = 6, },
895 { .val = 1, .div = 12, },
896 { .val = 2, .div = 18, },
897 { .val = 3, .div = 24, },
904 .div = {
915 .div = {
926 .div = {
933 * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
937 * | ___divisor 1---|----> to consumer
938 * parent >--| pll___/___divisor 2---|----> to consumer
943 static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node, in sunxi_divs_clk_setup()
949 struct clk **clks, *pclk; in sunxi_divs_clk_setup()
955 struct factors_data factors = *data->factors; in sunxi_divs_clk_setup()
962 if (data->ndivs) in sunxi_divs_clk_setup()
963 ndivs = data->ndivs; in sunxi_divs_clk_setup()
967 if (data->div[i].self) { in sunxi_divs_clk_setup()
968 of_property_read_string_index(node, "clock-output-names", in sunxi_divs_clk_setup()
973 /* If we don't have a .self clk use the first output-name up to '_' */ in sunxi_divs_clk_setup()
977 of_property_read_string_index(node, "clock-output-names", in sunxi_divs_clk_setup()
981 derived_name = kstrndup(clk_name, endp - clk_name, in sunxi_divs_clk_setup()
1001 pr_err("Could not map registers for divs-clk: %pOF\n", node); in sunxi_divs_clk_setup()
1013 clk_data->clks = clks; in sunxi_divs_clk_setup()
1020 if (of_property_read_string_index(node, "clock-output-names", in sunxi_divs_clk_setup()
1025 if (data->div[i].self) { in sunxi_divs_clk_setup()
1026 clk_data->clks[i] = pclk; in sunxi_divs_clk_setup()
1035 if (data->div[i].gate) { in sunxi_divs_clk_setup()
1040 gate->reg = reg; in sunxi_divs_clk_setup()
1041 gate->bit_idx = data->div[i].gate; in sunxi_divs_clk_setup()
1042 gate->lock = &clk_lock; in sunxi_divs_clk_setup()
1044 gate_hw = &gate->hw; in sunxi_divs_clk_setup()
1048 if (data->div[i].fixed) { in sunxi_divs_clk_setup()
1053 fix_factor->mult = 1; in sunxi_divs_clk_setup()
1054 fix_factor->div = data->div[i].fixed; in sunxi_divs_clk_setup()
1056 rate_hw = &fix_factor->hw; in sunxi_divs_clk_setup()
1063 flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0; in sunxi_divs_clk_setup()
1065 divider->reg = reg; in sunxi_divs_clk_setup()
1066 divider->shift = data->div[i].shift; in sunxi_divs_clk_setup()
1067 divider->width = SUNXI_DIVISOR_WIDTH; in sunxi_divs_clk_setup()
1068 divider->flags = flags; in sunxi_divs_clk_setup()
1069 divider->lock = &clk_lock; in sunxi_divs_clk_setup()
1070 divider->table = data->div[i].table; in sunxi_divs_clk_setup()
1072 rate_hw = ÷r->hw; in sunxi_divs_clk_setup()
1083 (data->div[i].critical ? in sunxi_divs_clk_setup()
1086 WARN_ON(IS_ERR(clk_data->clks[i])); in sunxi_divs_clk_setup()
1090 clk_data->clk_num = i; in sunxi_divs_clk_setup()
1114 CLK_OF_DECLARE(sun4i_pll5, "allwinner,sun4i-a10-pll5-clk",
1121 CLK_OF_DECLARE(sun4i_pll6, "allwinner,sun4i-a10-pll6-clk",
1128 CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk",
1140 if (req->rate > req->parent_rate) in sun6i_display_factors()
1141 req->rate = req->parent_rate; in sun6i_display_factors()
1143 m = DIV_ROUND_UP(req->parent_rate, req->rate); in sun6i_display_factors()
1145 req->rate = req->parent_rate / m; in sun6i_display_factors()
1146 req->m = m - 1; in sun6i_display_factors()
1166 CLK_OF_DECLARE(sun6i_display, "allwinner,sun6i-a31-display-clk",