Lines Matching +full:clk +full:- +full:div
1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
31 #define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
37 struct clk *clk; member
42 struct clockgen_pll_div div[MAX_PLL_DIV]; member
51 int div; /* PLL_DIVn */ member
80 int cmux_to_group[NUM_CMUX + 1]; /* array should be -1 terminated */
89 struct clk *sysclk, *coreclk;
91 struct clk *cmux[NUM_CMUX];
92 struct clk *hwaccel[NUM_HWACCEL];
93 struct clk *fman[2];
102 if (cg->info.flags & CG_LITTLE_ENDIAN) in cg_out()
112 if (cg->info.flags & CG_LITTLE_ENDIAN) in cg_in()
471 reg = ioread32be(&cg->guts->rcwsr[7]); in p2041_init_periph()
474 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk; in p2041_init_periph()
476 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p2041_init_periph()
483 reg = ioread32be(&cg->guts->rcwsr[7]); in p4080_init_periph()
486 cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; in p4080_init_periph()
488 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p4080_init_periph()
491 cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; in p4080_init_periph()
493 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p4080_init_periph()
499 int div = PLL_DIV2; in p5020_init_periph() local
501 reg = ioread32be(&cg->guts->rcwsr[7]); in p5020_init_periph()
503 div = PLL_DIV4; in p5020_init_periph()
506 cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk; in p5020_init_periph()
508 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5020_init_periph()
514 int div = PLL_DIV2; in p5040_init_periph() local
516 reg = ioread32be(&cg->guts->rcwsr[7]); in p5040_init_periph()
518 div = PLL_DIV4; in p5040_init_periph()
521 cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk; in p5040_init_periph()
523 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5040_init_periph()
526 cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk; in p5040_init_periph()
528 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5040_init_periph()
533 cg->fman[0] = cg->hwaccel[1]; in t1023_init_periph()
538 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk; in t1040_init_periph()
543 cg->fman[0] = cg->hwaccel[0]; in t2080_init_periph()
548 cg->fman[0] = cg->hwaccel[3]; in t4240_init_periph()
549 cg->fman[1] = cg->hwaccel[4]; in t4240_init_periph()
554 .compat = "fsl,b4420-clockgen",
555 .guts_compat = "fsl,b4860-device-config",
564 0, 1, 1, 1, -1
570 .compat = "fsl,b4860-clockgen",
571 .guts_compat = "fsl,b4860-device-config",
580 0, 1, 1, 1, -1
586 .compat = "fsl,ls1021a-clockgen",
591 0, -1
596 .compat = "fsl,ls1028a-clockgen",
605 0, 0, 0, 0, -1
611 .compat = "fsl,ls1043a-clockgen",
620 0, -1
626 .compat = "fsl,ls1046a-clockgen",
635 0, -1
641 .compat = "fsl,ls1088a-clockgen",
649 0, 0, -1
655 .compat = "fsl,ls1012a-clockgen",
660 0, -1
665 .compat = "fsl,ls2080a-clockgen",
670 0, 0, 1, 1, -1
676 .compat = "fsl,lx2160a-clockgen",
681 0, 0, 0, 0, 1, 1, 1, 1, -1
687 .compat = "fsl,p2041-clockgen",
688 .guts_compat = "fsl,qoriq-device-config-1.0",
694 0, 0, 1, 1, -1
699 .compat = "fsl,p3041-clockgen",
700 .guts_compat = "fsl,qoriq-device-config-1.0",
706 0, 0, 1, 1, -1
711 .compat = "fsl,p4080-clockgen",
712 .guts_compat = "fsl,qoriq-device-config-1.0",
718 0, 0, 0, 0, 1, 1, 1, 1, -1
723 .compat = "fsl,p5020-clockgen",
724 .guts_compat = "fsl,qoriq-device-config-1.0",
730 0, 1, -1
735 .compat = "fsl,p5040-clockgen",
736 .guts_compat = "fsl,p5040-device-config",
742 0, 0, 1, 1, -1
747 .compat = "fsl,t1023-clockgen",
748 .guts_compat = "fsl,t1023-device-config",
757 0, 0, -1
763 .compat = "fsl,t1040-clockgen",
764 .guts_compat = "fsl,t1040-device-config",
770 0, 0, 0, 0, -1
776 .compat = "fsl,t2080-clockgen",
777 .guts_compat = "fsl,t2080-device-config",
786 0, -1
792 .compat = "fsl,t4240-clockgen",
793 .guts_compat = "fsl,t4240-device-config",
802 0, 0, 1, -1
829 if (idx >= hwc->num_parents) in mux_set_parent()
830 return -EINVAL; in mux_set_parent()
832 clksel = hwc->parent_to_clksel[idx]; in mux_set_parent()
833 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg); in mux_set_parent()
844 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; in mux_get_parent()
846 ret = hwc->clksel_to_parent[clksel]; in mux_get_parent()
848 pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg); in mux_get_parent()
872 int pll, div; in get_pll_div() local
874 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID)) in get_pll_div()
877 pll = hwc->info->clksel[idx].pll; in get_pll_div()
878 div = hwc->info->clksel[idx].div; in get_pll_div()
880 return &cg->pll[pll].div[div]; in get_pll_div()
883 static struct clk * __init create_mux_common(struct clockgen *cg, in create_mux_common()
892 struct clk *clk; in create_mux_common() local
893 const struct clockgen_pll_div *div; in create_mux_common() local
903 hwc->clksel_to_parent[i] = -1; in create_mux_common()
905 div = get_pll_div(cg, hwc, i); in create_mux_common()
906 if (!div) in create_mux_common()
909 rate = clk_get_rate(div->clk); in create_mux_common()
911 if (hwc->info->clksel[i].flags & CLKSEL_80PCT && in create_mux_common()
919 parent_names[j] = div->name; in create_mux_common()
920 hwc->parent_to_clksel[j] = i; in create_mux_common()
921 hwc->clksel_to_parent[i] = j; in create_mux_common()
928 init.num_parents = hwc->num_parents = j; in create_mux_common()
930 hwc->hw.init = &init; in create_mux_common()
931 hwc->cg = cg; in create_mux_common()
933 clk = clk_register(NULL, &hwc->hw); in create_mux_common()
934 if (IS_ERR(clk)) { in create_mux_common()
936 PTR_ERR(clk)); in create_mux_common()
941 return clk; in create_mux_common()
944 static struct clk * __init create_one_cmux(struct clockgen *cg, int idx) in create_one_cmux()
947 const struct clockgen_pll_div *div; in create_one_cmux() local
956 if (cg->info.flags & CG_VER3) in create_one_cmux()
957 hwc->reg = cg->regs + 0x70000 + 0x20 * idx; in create_one_cmux()
959 hwc->reg = cg->regs + 0x20 * idx; in create_one_cmux()
961 hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]]; in create_one_cmux()
970 clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; in create_one_cmux()
971 div = get_pll_div(cg, hwc, clksel); in create_one_cmux()
972 if (!div) { in create_one_cmux()
977 max_rate = clk_get_rate(div->clk); in create_one_cmux()
981 plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk); in create_one_cmux()
983 if (cg->info.flags & CG_CMUX_GE_PLAT) in create_one_cmux()
989 pct80_rate, "cg-cmux%d", idx); in create_one_cmux()
992 static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx) in create_one_hwaccel()
1000 hwc->reg = cg->regs + 0x20 * idx + 0x10; in create_one_hwaccel()
1001 hwc->info = cg->info.hwaccel[idx]; in create_one_hwaccel()
1004 "cg-hwaccel%d", idx); in create_one_hwaccel()
1011 for (i = 0; i < ARRAY_SIZE(cg->cmux); i++) { in create_muxes()
1012 if (cg->info.cmux_to_group[i] < 0) in create_muxes()
1014 if (cg->info.cmux_to_group[i] >= in create_muxes()
1015 ARRAY_SIZE(cg->info.cmux_groups)) { in create_muxes()
1020 cg->cmux[i] = create_one_cmux(cg, i); in create_muxes()
1023 for (i = 0; i < ARRAY_SIZE(cg->hwaccel); i++) { in create_muxes()
1024 if (!cg->info.hwaccel[i]) in create_muxes()
1027 cg->hwaccel[i] = create_one_hwaccel(cg, i); in create_muxes()
1036 * contain a "clocks" property -- otherwise the input clocks may
1048 struct clk *clk; in core_mux_init() local
1058 clk = clockgen.cmux[idx]; in core_mux_init()
1060 rc = of_clk_add_provider(np, of_clk_src_simple_get, clk); in core_mux_init()
1062 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n", in core_mux_init()
1068 static struct clk __init
1073 if (of_property_read_u32(node, "clock-frequency", &rate)) in sysclk_from_fixed()
1074 return ERR_PTR(-ENODEV); in sysclk_from_fixed()
1079 static struct clk __init *input_clock(const char *name, struct clk *clk) in input_clock() argument
1084 input_name = __clk_get_name(clk); in input_clock()
1085 clk = clk_register_fixed_factor(NULL, name, input_name, in input_clock()
1087 if (IS_ERR(clk)) in input_clock()
1089 PTR_ERR(clk)); in input_clock()
1091 return clk; in input_clock()
1094 static struct clk __init *input_clock_by_name(const char *name, in input_clock_by_name()
1097 struct clk *clk; in input_clock_by_name() local
1099 clk = of_clk_get_by_name(clockgen.node, dtname); in input_clock_by_name()
1100 if (IS_ERR(clk)) in input_clock_by_name()
1101 return clk; in input_clock_by_name()
1103 return input_clock(name, clk); in input_clock_by_name()
1106 static struct clk __init *input_clock_by_index(const char *name, int idx) in input_clock_by_index()
1108 struct clk *clk; in input_clock_by_index() local
1110 clk = of_clk_get(clockgen.node, 0); in input_clock_by_index()
1111 if (IS_ERR(clk)) in input_clock_by_index()
1112 return clk; in input_clock_by_index()
1114 return input_clock(name, clk); in input_clock_by_index()
1117 static struct clk * __init create_sysclk(const char *name) in create_sysclk()
1120 struct clk *clk; in create_sysclk() local
1122 clk = sysclk_from_fixed(clockgen.node, name); in create_sysclk()
1123 if (!IS_ERR(clk)) in create_sysclk()
1124 return clk; in create_sysclk()
1126 clk = input_clock_by_name(name, "sysclk"); in create_sysclk()
1127 if (!IS_ERR(clk)) in create_sysclk()
1128 return clk; in create_sysclk()
1130 clk = input_clock_by_index(name, 0); in create_sysclk()
1131 if (!IS_ERR(clk)) in create_sysclk()
1132 return clk; in create_sysclk()
1136 clk = sysclk_from_fixed(sysclk, name); in create_sysclk()
1137 if (!IS_ERR(clk)) in create_sysclk()
1138 return clk; in create_sysclk()
1145 static struct clk * __init create_coreclk(const char *name) in create_coreclk()
1147 struct clk *clk; in create_coreclk() local
1149 clk = input_clock_by_name(name, "coreclk"); in create_coreclk()
1150 if (!IS_ERR(clk)) in create_coreclk()
1151 return clk; in create_coreclk()
1159 if (WARN_ON(PTR_ERR(clk) == -EPROBE_DEFER)) in create_coreclk()
1160 return clk; in create_coreclk()
1168 struct clk *clk; in sysclk_init() local
1172 clk = clockgen.sysclk; in sysclk_init()
1173 if (clk) in sysclk_init()
1174 of_clk_add_provider(node, of_clk_src_simple_get, clk); in sysclk_init()
1183 struct clockgen_pll *pll = &cg->pll[idx]; in create_one_pll()
1184 const char *input = "cg-sysclk"; in create_one_pll()
1187 if (!(cg->info.pll_mask & (1 << idx))) in create_one_pll()
1190 if (cg->coreclk && idx != PLATFORM_PLL) { in create_one_pll()
1191 if (IS_ERR(cg->coreclk)) in create_one_pll()
1194 input = "cg-coreclk"; in create_one_pll()
1197 if (cg->info.flags & CG_VER3) { in create_one_pll()
1200 reg = cg->regs + 0x60080; in create_one_pll()
1203 reg = cg->regs + 0x80; in create_one_pll()
1206 reg = cg->regs + 0xa0; in create_one_pll()
1209 reg = cg->regs + 0x10080; in create_one_pll()
1212 reg = cg->regs + 0x100a0; in create_one_pll()
1220 reg = cg->regs + 0xc00; in create_one_pll()
1222 reg = cg->regs + 0x800 + 0x20 * (idx - 1); in create_one_pll()
1234 if ((cg->info.flags & CG_VER3) || in create_one_pll()
1235 ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL)) in create_one_pll()
1240 for (i = 0; i < ARRAY_SIZE(pll->div); i++) { in create_one_pll()
1241 struct clk *clk; in create_one_pll() local
1251 snprintf(pll->div[i].name, sizeof(pll->div[i].name), in create_one_pll()
1252 "cg-pll%d-div%d", idx, i + 1); in create_one_pll()
1254 clk = clk_register_fixed_factor(NULL, in create_one_pll()
1255 pll->div[i].name, input, 0, mult, i + 1); in create_one_pll()
1256 if (IS_ERR(clk)) { in create_one_pll()
1258 __func__, pll->div[i].name, PTR_ERR(clk)); in create_one_pll()
1262 pll->div[i].clk = clk; in create_one_pll()
1263 ret = clk_register_clkdev(clk, pll->div[i].name, NULL); in create_one_pll()
1266 __func__, pll->div[i].name, ret); in create_one_pll()
1275 for (i = 0; i < ARRAY_SIZE(cg->pll); i++) in create_plls()
1283 struct clk **subclks; in legacy_pll_init()
1289 count = of_property_count_strings(np, "clock-output-names"); in legacy_pll_init()
1291 BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4); in legacy_pll_init()
1292 subclks = kcalloc(4, sizeof(struct clk *), GFP_KERNEL); in legacy_pll_init()
1301 subclks[0] = pll->div[0].clk; in legacy_pll_init()
1302 subclks[1] = pll->div[1].clk; in legacy_pll_init()
1303 subclks[2] = pll->div[3].clk; in legacy_pll_init()
1305 subclks[0] = pll->div[0].clk; in legacy_pll_init()
1306 subclks[1] = pll->div[1].clk; in legacy_pll_init()
1307 subclks[2] = pll->div[2].clk; in legacy_pll_init()
1308 subclks[3] = pll->div[3].clk; in legacy_pll_init()
1311 onecell_data->clks = subclks; in legacy_pll_init()
1312 onecell_data->clk_num = count; in legacy_pll_init()
1316 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n", in legacy_pll_init()
1355 static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data) in clockgen_clk_get()
1358 struct clk *clk; in clockgen_clk_get() local
1362 if (clkspec->args_count < 2) { in clockgen_clk_get()
1364 return ERR_PTR(-EINVAL); in clockgen_clk_get()
1367 type = clkspec->args[0]; in clockgen_clk_get()
1368 idx = clkspec->args[1]; in clockgen_clk_get()
1374 clk = cg->sysclk; in clockgen_clk_get()
1377 if (idx >= ARRAY_SIZE(cg->cmux)) in clockgen_clk_get()
1379 clk = cg->cmux[idx]; in clockgen_clk_get()
1382 if (idx >= ARRAY_SIZE(cg->hwaccel)) in clockgen_clk_get()
1384 clk = cg->hwaccel[idx]; in clockgen_clk_get()
1387 if (idx >= ARRAY_SIZE(cg->fman)) in clockgen_clk_get()
1389 clk = cg->fman[idx]; in clockgen_clk_get()
1392 pll = &cg->pll[PLATFORM_PLL]; in clockgen_clk_get()
1393 if (idx >= ARRAY_SIZE(pll->div)) in clockgen_clk_get()
1395 clk = pll->div[idx].clk; in clockgen_clk_get()
1400 clk = cg->coreclk; in clockgen_clk_get()
1401 if (IS_ERR(clk)) in clockgen_clk_get()
1402 clk = NULL; in clockgen_clk_get()
1408 if (!clk) in clockgen_clk_get()
1409 return ERR_PTR(-ENOENT); in clockgen_clk_get()
1410 return clk; in clockgen_clk_get()
1414 return ERR_PTR(-EINVAL); in clockgen_clk_get()
1485 !strcmp(chipinfo[i].compat, "fsl,ls1021a-clockgen")) in _clockgen_init()
1514 clockgen.sysclk = create_sysclk("cg-sysclk"); in _clockgen_init()
1515 clockgen.coreclk = create_coreclk("cg-coreclk"); in _clockgen_init()
1524 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n", in _clockgen_init()
1547 pdev = platform_device_register_simple("qoriq-cpufreq", -1, in clockgen_cpufreq_init()
1550 pr_err("Couldn't register qoriq-cpufreq err=%ld\n", in clockgen_cpufreq_init()
1557 CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
1558 CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
1559 CLK_OF_DECLARE(qoriq_clockgen_b4420, "fsl,b4420-clockgen", clockgen_init);
1560 CLK_OF_DECLARE(qoriq_clockgen_b4860, "fsl,b4860-clockgen", clockgen_init);
1561 CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
1562 CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
1563 CLK_OF_DECLARE(qoriq_clockgen_ls1028a, "fsl,ls1028a-clockgen", clockgen_init);
1564 CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
1565 CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
1566 CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
1567 CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
1568 CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen", clockgen_init);
1569 CLK_OF_DECLARE(qoriq_clockgen_p2041, "fsl,p2041-clockgen", clockgen_init);
1570 CLK_OF_DECLARE(qoriq_clockgen_p3041, "fsl,p3041-clockgen", clockgen_init);
1571 CLK_OF_DECLARE(qoriq_clockgen_p4080, "fsl,p4080-clockgen", clockgen_init);
1572 CLK_OF_DECLARE(qoriq_clockgen_p5020, "fsl,p5020-clockgen", clockgen_init);
1573 CLK_OF_DECLARE(qoriq_clockgen_p5040, "fsl,p5040-clockgen", clockgen_init);
1574 CLK_OF_DECLARE(qoriq_clockgen_t1023, "fsl,t1023-clockgen", clockgen_init);
1575 CLK_OF_DECLARE(qoriq_clockgen_t1040, "fsl,t1040-clockgen", clockgen_init);
1576 CLK_OF_DECLARE(qoriq_clockgen_t2080, "fsl,t2080-clockgen", clockgen_init);
1577 CLK_OF_DECLARE(qoriq_clockgen_t4240, "fsl,t4240-clockgen", clockgen_init);
1580 CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
1581 CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init);
1582 CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init);
1583 CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init);
1584 CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init);
1585 CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init);
1586 CLK_OF_DECLARE(qoriq_pltfrm_pll_1, "fsl,qoriq-platform-pll-1.0", pltfrm_pll_init);
1587 CLK_OF_DECLARE(qoriq_pltfrm_pll_2, "fsl,qoriq-platform-pll-2.0", pltfrm_pll_init);