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Searched +full:0 +full:x4e000 (Results 1 – 18 of 18) sorted by relevance

/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dqcom,q6sstopcc.yaml40 reg = <0x07500000 0x4e000>, <0x07550000 0x10000>;
/Linux-v6.1/Documentation/devicetree/bindings/firmware/
Dnvidia,tegra186-bpmp.yaml134 reg = <0x03c00000 0xa0000>;
142 reg = <0x30000000 0x50000>;
145 ranges = <0x0 0x30000000 0x50000>;
148 reg = <0x4e000 0x1000>;
154 reg = <0x4f000 0x1000>;
179 #size-cells = <0>;
/Linux-v6.1/drivers/soc/tegra/cbb/
Dtegra234-cbb.c8 * Error types supported by CBB2.0 are:
31 #define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0
32 #define FABRIC_EN_CFG_STATUS_0_0 0x40
33 #define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60
34 #define FABRIC_EN_CFG_ADDR_LOW_0 0x80
35 #define FABRIC_EN_CFG_ADDR_HI_0 0x84
37 #define FABRIC_MN_MASTER_ERR_EN_0 0x200
38 #define FABRIC_MN_MASTER_ERR_FORCE_0 0x204
39 #define FABRIC_MN_MASTER_ERR_STATUS_0 0x208
40 #define FABRIC_MN_MASTER_ERR_OVERFLOW_STATUS_0 0x20c
[all …]
/Linux-v6.1/drivers/clk/qcom/
Dgcc-qcm2290.c46 { 500000000, 1250000000, 0 },
58 .offset = 0x0,
61 .enable_reg = 0x79000,
62 .enable_mask = BIT(0),
75 { 0x1, 2 },
80 .offset = 0x0,
95 .offset = 0x1000,
98 .enable_reg = 0x79000,
113 .l = 0x3c,
114 .alpha = 0x0,
[all …]
Dgcc-sm6115.c49 { 500000000, 1250000000, 0 },
57 .offset = 0x0,
62 .enable_reg = 0x79000,
63 .enable_mask = BIT(0),
76 { 0x1, 2 },
81 .offset = 0x0,
96 { 0x0, 1 },
101 .offset = 0x0,
117 .l = 0x3c,
118 .vco_val = 0x1 << 20,
[all …]
Dgcc-sm6375.c53 { 249600000, 2000000000, 0 },
57 { 595200000, 3600000000UL, 0 },
61 .offset = 0x0,
64 .enable_reg = 0x79000,
65 .enable_mask = BIT(0),
78 { 0x1, 2 },
83 .offset = 0x0,
100 { 0x3, 3 },
105 .offset = 0x0,
122 .offset = 0x1000,
[all …]
Dgcc-sm6125.c43 .offset = 0x0,
46 .enable_reg = 0x79000,
47 .enable_mask = BIT(0),
86 .offset = 0x3000,
89 .enable_reg = 0x79000,
103 .offset = 0x4000,
106 .enable_reg = 0x79000,
120 .offset = 0x5000,
123 .enable_reg = 0x79000,
137 .offset = 0x6000,
[all …]
Dgcc-msm8909.c53 { P_XO, 0 },
65 .offset = 0x21000,
68 .enable_reg = 0x45000,
69 .enable_mask = BIT(0),
81 .offset = 0x21000,
95 .l_reg = 0x20004,
96 .m_reg = 0x20008,
97 .n_reg = 0x2000c,
98 .config_reg = 0x20010,
99 .mode_reg = 0x20000,
[all …]
Dgcc-qcs404.c42 { P_XO, 0 },
60 { P_XO, 0 },
70 { P_XO, 0 },
84 { P_XO, 0 },
98 { P_XO, 0 },
110 { P_XO, 0 },
124 { P_XO, 0 },
138 { P_XO, 0 },
156 { P_XO, 0 },
168 { P_XO, 0 },
[all …]
Dgcc-msm8998.c29 { 250000000, 2000000000, 0 },
34 .offset = 0x0,
39 .enable_reg = 0x52000,
40 .enable_mask = BIT(0),
53 .offset = 0x0,
66 .offset = 0x0,
79 .offset = 0x0,
92 .offset = 0x0,
105 .offset = 0x1000,
110 .enable_reg = 0x52000,
[all …]
Dgcc-msm8916.c46 .l_reg = 0x21004,
47 .m_reg = 0x21008,
48 .n_reg = 0x2100c,
49 .config_reg = 0x21010,
50 .mode_reg = 0x21000,
51 .status_reg = 0x2101c,
64 .enable_reg = 0x45000,
65 .enable_mask = BIT(0),
77 .l_reg = 0x20004,
78 .m_reg = 0x20008,
[all …]
Dgcc-msm8996.c50 .offset = 0x00000,
53 .enable_reg = 0x52000,
54 .enable_mask = BIT(0),
80 .offset = 0x00000,
95 .enable_reg = 0x5200c,
96 .enable_mask = BIT(0),
112 .enable_reg = 0x5200c,
127 .offset = 0x77000,
130 .enable_reg = 0x52000,
144 .offset = 0x77000,
[all …]
Dgcc-msm8976.c56 .l_reg = 0x21004,
57 .m_reg = 0x21008,
58 .n_reg = 0x2100c,
59 .config_reg = 0x21014,
60 .mode_reg = 0x21000,
61 .status_reg = 0x2101c,
74 .enable_reg = 0x45000,
75 .enable_mask = BIT(0),
89 .l_reg = 0x4a004,
90 .m_reg = 0x4a008,
[all …]
Dgcc-msm8939.c54 .l_reg = 0x21004,
55 .m_reg = 0x21008,
56 .n_reg = 0x2100c,
57 .config_reg = 0x21010,
58 .mode_reg = 0x21000,
59 .status_reg = 0x2101c,
72 .enable_reg = 0x45000,
73 .enable_mask = BIT(0),
85 .l_reg = 0x20004,
86 .m_reg = 0x20008,
[all …]
Dgcc-msm8953.c41 .offset = 0x21000,
44 .enable_reg = 0x45000,
45 .enable_mask = BIT(0),
71 .offset = 0x21000,
84 .offset = 0x4a000,
87 .enable_reg = 0x45000,
101 .offset = 0x4a000,
114 { 1000000000, 2000000000, 0 },
119 .config_ctl_val = 0x4001055b,
120 .early_output_mask = 0,
[all …]
/Linux-v6.1/arch/arm64/boot/dts/nvidia/
Dtegra186.dtsi20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x1000>;
27 reg = <0x0 0x2200000 0x0 0x10000>,
28 <0x0 0x2210000 0x0 0x10000>;
44 reg = <0x0 0x02490000 0x0 0x10000>;
71 snps,burst-map = <0x7>;
78 reg = <0x0 0x2600000 0x0 0x210000>;
127 ranges = <0x02900000 0x0 0x02900000 0x200000>;
132 reg = <0x02930000 0x20000>;
134 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
[all …]
Dtegra194.dtsi20 bus@0 {
24 ranges = <0x0 0x0 0x0 0x40000000>;
28 reg = <0x00100000 0xf000>,
29 <0x0010f000 0x1000>;
35 reg = <0x2200000 0x10000>,
36 <0x2210000 0x10000>;
93 reg = <0x02300000 0x1000>;
103 reg = <0x2390000 0x1000>,
104 <0x23a0000 0x1000>,
105 <0x23b0000 0x1000>,
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
16 segment@0 { /* 0x4a000000 */
20 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]