Lines Matching +full:0 +full:x4e000
53 { 249600000, 2000000000, 0 },
57 { 595200000, 3600000000UL, 0 },
61 .offset = 0x0,
64 .enable_reg = 0x79000,
65 .enable_mask = BIT(0),
78 { 0x1, 2 },
83 .offset = 0x0,
100 { 0x3, 3 },
105 .offset = 0x0,
122 .offset = 0x1000,
125 .enable_reg = 0x79000,
140 .l = 0x3c,
141 .alpha = 0x0,
142 .config_ctl_val = 0x20485699,
143 .config_ctl_hi_val = 0x00002261,
144 .config_ctl_hi1_val = 0x329a299c,
145 .user_ctl_val = 0x00000001,
146 .user_ctl_hi_val = 0x00000805,
147 .user_ctl_hi1_val = 0x00000000,
151 .offset = 0xa000,
157 .enable_reg = 0x79000,
172 .l = 0x1b,
173 .alpha = 0xb555,
174 .config_ctl_val = 0x20485699,
175 .config_ctl_hi_val = 0x00002261,
176 .config_ctl_hi1_val = 0x329a299c,
177 .user_ctl_val = 0x00000001,
178 .user_ctl_hi_val = 0x00000805,
179 .user_ctl_hi1_val = 0x00000000,
183 .offset = 0xb000,
189 .enable_reg = 0x79000,
203 .offset = 0x3000,
206 .enable_reg = 0x79000,
220 { 0x1, 2 },
225 .offset = 0x3000,
242 .offset = 0x4000,
245 .enable_reg = 0x79000,
259 .offset = 0x5000,
262 .enable_reg = 0x79000,
276 .offset = 0x6000,
279 .enable_reg = 0x79000,
293 { 0x1, 2 },
298 .offset = 0x6000,
315 .offset = 0x7000,
318 .enable_reg = 0x79000,
333 .l = 0x14,
334 .alpha = 0xd555,
335 .config_ctl_val = 0x20485699,
336 .config_ctl_hi_val = 0x00002261,
337 .config_ctl_hi1_val = 0x329a299c,
338 .user_ctl_val = 0x00000101,
339 .user_ctl_hi_val = 0x00000805,
340 .user_ctl_hi1_val = 0x00000000,
344 .offset = 0x8000,
350 .enable_reg = 0x79000,
364 { 0x1, 2 },
369 .offset = 0x8000,
388 .l = 0x4b,
389 .alpha = 0x0,
390 .config_ctl_val = 0x08200800,
391 .config_ctl_hi_val = 0x05022011,
392 .config_ctl_hi1_val = 0x08000000,
393 .user_ctl_val = 0x00000301,
397 .offset = 0x9000,
402 .enable_reg = 0x79000,
416 { 0x3, 4 },
421 .offset = 0x9000,
439 { P_BI_TCXO, 0 },
451 { P_BI_TCXO, 0 },
465 { P_BI_TCXO, 0 },
486 { P_BI_TCXO, 0 },
504 { P_BI_TCXO, 0 },
522 { P_BI_TCXO, 0 },
542 { P_BI_TCXO, 0 },
562 { P_BI_TCXO, 0 },
578 { P_BI_TCXO, 0 },
596 { P_BI_TCXO, 0 },
616 { P_BI_TCXO, 0 },
636 { P_BI_TCXO, 0 },
654 { P_BI_TCXO, 0 },
670 { P_BI_TCXO, 0 },
680 { P_BI_TCXO, 0 },
692 F(19200000, P_BI_TCXO, 1, 0, 0),
693 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
694 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
695 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
700 .cmd_rcgr = 0x5802c,
701 .mnd_width = 0,
714 F(19200000, P_BI_TCXO, 1, 0, 0),
715 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
720 .cmd_rcgr = 0x56000,
721 .mnd_width = 0,
734 .cmd_rcgr = 0x5c000,
735 .mnd_width = 0,
748 F(19200000, P_BI_TCXO, 1, 0, 0),
749 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
750 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
755 .cmd_rcgr = 0x59000,
756 .mnd_width = 0,
769 .cmd_rcgr = 0x5901c,
770 .mnd_width = 0,
783 .cmd_rcgr = 0x59038,
784 .mnd_width = 0,
797 .cmd_rcgr = 0x59054,
798 .mnd_width = 0,
811 F(19200000, P_BI_TCXO, 1, 0, 0),
818 .cmd_rcgr = 0x51000,
832 .cmd_rcgr = 0x5101c,
846 .cmd_rcgr = 0x51038,
860 .cmd_rcgr = 0x51054,
874 .cmd_rcgr = 0x51070,
888 F(19200000, P_BI_TCXO, 1, 0, 0),
889 F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
890 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
895 .cmd_rcgr = 0x55024,
896 .mnd_width = 0,
909 F(19200000, P_BI_TCXO, 1, 0, 0),
910 F(200000000, P_GPLL8_OUT_EVEN, 1, 0, 0),
911 F(266600000, P_GPLL8_OUT_EVEN, 1, 0, 0),
912 F(480000000, P_GPLL8_OUT_EVEN, 1, 0, 0),
913 F(580000000, P_GPLL8_OUT_EVEN, 1, 0, 0),
918 .cmd_rcgr = 0x55004,
919 .mnd_width = 0,
933 F(19200000, P_BI_TCXO, 1, 0, 0),
934 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
935 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
936 F(144000000, P_GPLL9_OUT_MAIN, 2.5, 0, 0),
937 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
938 F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
939 F(180000000, P_GPLL9_OUT_MAIN, 2, 0, 0),
940 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
941 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
942 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
943 F(329142857, P_GPLL10_OUT_EVEN, 3.5, 0, 0),
944 F(384000000, P_GPLL10_OUT_EVEN, 3, 0, 0),
945 F(460800000, P_GPLL10_OUT_EVEN, 2.5, 0, 0),
946 F(576000000, P_GPLL10_OUT_EVEN, 2, 0, 0),
951 .cmd_rcgr = 0x52004,
965 F(19200000, P_BI_TCXO, 1, 0, 0),
966 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
967 F(266571429, P_GPLL5_OUT_EVEN, 3.5, 0, 0),
968 F(426400000, P_GPLL3_OUT_MAIN, 2.5, 0, 0),
969 F(466500000, P_GPLL5_OUT_EVEN, 2, 0, 0),
974 .cmd_rcgr = 0x52094,
975 .mnd_width = 0,
988 .cmd_rcgr = 0x52024,
1002 .cmd_rcgr = 0x520b4,
1003 .mnd_width = 0,
1016 .cmd_rcgr = 0x52044,
1030 .cmd_rcgr = 0x520d4,
1031 .mnd_width = 0,
1044 F(19200000, P_BI_TCXO, 1, 0, 0),
1045 F(256000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
1046 F(384000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
1051 .cmd_rcgr = 0x52064,
1052 .mnd_width = 0,
1065 F(19200000, P_BI_TCXO, 1, 0, 0),
1066 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
1067 F(80000000, P_GPLL0_OUT_MAIN, 7.5, 0, 0),
1072 .cmd_rcgr = 0x58010,
1073 .mnd_width = 0,
1086 F(19200000, P_BI_TCXO, 1, 0, 0),
1087 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
1088 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
1093 .cmd_rcgr = 0x2b13c,
1094 .mnd_width = 0,
1107 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1108 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
1109 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
1110 F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
1115 .cmd_rcgr = 0x4d004,
1129 .cmd_rcgr = 0x4e004,
1143 .cmd_rcgr = 0x4f004,
1157 F(19200000, P_BI_TCXO, 1, 0, 0),
1158 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
1163 .cmd_rcgr = 0x20010,
1164 .mnd_width = 0,
1179 F(19200000, P_BI_TCXO, 1, 0, 0),
1184 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1187 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
1191 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
1192 F(128000000, P_GPLL6_OUT_EVEN, 3, 0, 0),
1204 .cmd_rcgr = 0x1f148,
1220 .cmd_rcgr = 0x1f278,
1236 .cmd_rcgr = 0x1f3a8,
1252 .cmd_rcgr = 0x1f4d8,
1268 .cmd_rcgr = 0x1f608,
1284 .cmd_rcgr = 0x1f738,
1300 .cmd_rcgr = 0x5301c,
1316 .cmd_rcgr = 0x5314c,
1332 .cmd_rcgr = 0x5327c,
1348 .cmd_rcgr = 0x533ac,
1364 .cmd_rcgr = 0x534dc,
1380 .cmd_rcgr = 0x5360c,
1393 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
1394 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
1395 F(192000000, P_GPLL6_OUT_EVEN, 2, 0, 0),
1396 F(384000000, P_GPLL6_OUT_EVEN, 1, 0, 0),
1401 .cmd_rcgr = 0x38028,
1415 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1416 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
1417 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
1418 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1419 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
1424 .cmd_rcgr = 0x38010,
1425 .mnd_width = 0,
1439 F(19200000, P_BI_TCXO, 1, 0, 0),
1440 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1441 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
1442 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
1443 F(202000000, P_GPLL7_OUT_EVEN, 4, 0, 0),
1448 .cmd_rcgr = 0x1e00c,
1462 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1463 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
1464 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
1465 F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
1466 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1471 .cmd_rcgr = 0x45020,
1485 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
1486 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1487 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
1488 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
1493 .cmd_rcgr = 0x45048,
1494 .mnd_width = 0,
1507 F(9600000, P_BI_TCXO, 2, 0, 0),
1508 F(19200000, P_BI_TCXO, 1, 0, 0),
1513 .cmd_rcgr = 0x4507c,
1514 .mnd_width = 0,
1527 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
1528 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1529 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
1534 .cmd_rcgr = 0x45060,
1535 .mnd_width = 0,
1548 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
1549 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1550 F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
1551 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1556 .cmd_rcgr = 0x1a01c,
1570 F(19200000, P_BI_TCXO, 1, 0, 0),
1575 .cmd_rcgr = 0x1a034,
1576 .mnd_width = 0,
1589 .cmd_rcgr = 0x1a060,
1590 .mnd_width = 0,
1603 F(133000000, P_GPLL11_OUT_EVEN, 4, 0, 0),
1604 F(240000000, P_GPLL11_OUT_EVEN, 2.5, 0, 0),
1605 F(300000000, P_GPLL11_OUT_EVEN, 2, 0, 0),
1606 F(384000000, P_GPLL11_OUT_EVEN, 2, 0, 0),
1611 .cmd_rcgr = 0x58060,
1612 .mnd_width = 0,
1626 .reg = 0x2b154,
1627 .shift = 0,
1641 .reg = 0x1a04c,
1642 .shift = 0,
1656 .halt_reg = 0x1d004,
1658 .hwcg_reg = 0x1d004,
1661 .enable_reg = 0x1d004,
1662 .enable_mask = BIT(0),
1671 .halt_reg = 0x1d008,
1673 .hwcg_reg = 0x1d008,
1676 .enable_reg = 0x1d008,
1677 .enable_mask = BIT(0),
1686 .halt_reg = 0x71154,
1688 .hwcg_reg = 0x71154,
1691 .enable_reg = 0x71154,
1692 .enable_mask = BIT(0),
1701 .halt_reg = 0x23004,
1703 .hwcg_reg = 0x23004,
1706 .enable_reg = 0x79004,
1716 .halt_reg = 0x17070,
1718 .hwcg_reg = 0x17070,
1721 .enable_reg = 0x79004,
1731 .halt_reg = 0x1706c,
1733 .hwcg_reg = 0x1706c,
1736 .enable_reg = 0x79004,
1746 .halt_reg = 0x17008,
1748 .hwcg_reg = 0x17008,
1751 .enable_reg = 0x17008,
1752 .enable_mask = BIT(0),
1762 .halt_reg = 0x58044,
1765 .enable_reg = 0x58044,
1766 .enable_mask = BIT(0),
1780 .halt_reg = 0x56018,
1783 .enable_reg = 0x56018,
1784 .enable_mask = BIT(0),
1798 .halt_reg = 0x5c018,
1801 .enable_reg = 0x5c018,
1802 .enable_mask = BIT(0),
1816 .halt_reg = 0x52088,
1819 .enable_reg = 0x52088,
1820 .enable_mask = BIT(0),
1834 .halt_reg = 0x5208c,
1837 .enable_reg = 0x5208c,
1838 .enable_mask = BIT(0),
1852 .halt_reg = 0x52090,
1855 .enable_reg = 0x52090,
1856 .enable_mask = BIT(0),
1870 .halt_reg = 0x520f8,
1873 .enable_reg = 0x520f8,
1874 .enable_mask = BIT(0),
1888 .halt_reg = 0x59018,
1891 .enable_reg = 0x59018,
1892 .enable_mask = BIT(0),
1906 .halt_reg = 0x59034,
1909 .enable_reg = 0x59034,
1910 .enable_mask = BIT(0),
1924 .halt_reg = 0x59050,
1927 .enable_reg = 0x59050,
1928 .enable_mask = BIT(0),
1942 .halt_reg = 0x5906c,
1945 .enable_reg = 0x5906c,
1946 .enable_mask = BIT(0),
1960 .halt_reg = 0x51018,
1963 .enable_reg = 0x51018,
1964 .enable_mask = BIT(0),
1978 .halt_reg = 0x51034,
1981 .enable_reg = 0x51034,
1982 .enable_mask = BIT(0),
1996 .halt_reg = 0x51050,
1999 .enable_reg = 0x51050,
2000 .enable_mask = BIT(0),
2014 .halt_reg = 0x5106c,
2017 .enable_reg = 0x5106c,
2018 .enable_mask = BIT(0),
2032 .halt_reg = 0x51088,
2035 .enable_reg = 0x51088,
2036 .enable_mask = BIT(0),
2050 .halt_reg = 0x58054,
2053 .enable_reg = 0x58054,
2054 .enable_mask = BIT(0),
2063 .halt_reg = 0x5503c,
2066 .enable_reg = 0x5503c,
2067 .enable_mask = BIT(0),
2081 .halt_reg = 0x5501c,
2084 .enable_reg = 0x5501c,
2085 .enable_mask = BIT(0),
2099 .halt_reg = 0x5805c,
2102 .enable_reg = 0x5805c,
2103 .enable_mask = BIT(0),
2112 .halt_reg = 0x5201c,
2115 .enable_reg = 0x5201c,
2116 .enable_mask = BIT(0),
2130 .halt_reg = 0x5207c,
2133 .enable_reg = 0x5207c,
2134 .enable_mask = BIT(0),
2148 .halt_reg = 0x520ac,
2151 .enable_reg = 0x520ac,
2152 .enable_mask = BIT(0),
2166 .halt_reg = 0x5203c,
2169 .enable_reg = 0x5203c,
2170 .enable_mask = BIT(0),
2184 .halt_reg = 0x52080,
2187 .enable_reg = 0x52080,
2188 .enable_mask = BIT(0),
2202 .halt_reg = 0x520cc,
2205 .enable_reg = 0x520cc,
2206 .enable_mask = BIT(0),
2220 .halt_reg = 0x5205c,
2223 .enable_reg = 0x5205c,
2224 .enable_mask = BIT(0),
2238 .halt_reg = 0x52084,
2241 .enable_reg = 0x52084,
2242 .enable_mask = BIT(0),
2256 .halt_reg = 0x520ec,
2259 .enable_reg = 0x520ec,
2260 .enable_mask = BIT(0),
2274 .halt_reg = 0x58028,
2277 .enable_reg = 0x58028,
2278 .enable_mask = BIT(0),
2292 .halt_reg = 0x1a084,
2294 .hwcg_reg = 0x1a084,
2297 .enable_reg = 0x1a084,
2298 .enable_mask = BIT(0),
2312 .halt_reg = 0x1700c,
2314 .hwcg_reg = 0x1700c,
2317 .enable_reg = 0x1700c,
2318 .enable_mask = BIT(0),
2328 .reg = 0x17058,
2329 .shift = 0,
2343 .enable_reg = 0x79004,
2358 .halt_reg = 0x17020,
2360 .hwcg_reg = 0x17020,
2363 .enable_reg = 0x17020,
2364 .enable_mask = BIT(0),
2373 .halt_reg = 0x17074,
2375 .hwcg_reg = 0x17074,
2378 .enable_reg = 0x17074,
2379 .enable_mask = BIT(0),
2388 .halt_reg = 0x17064,
2390 .hwcg_reg = 0x17064,
2393 .enable_reg = 0x7900c,
2403 .halt_reg = 0x4d000,
2406 .enable_reg = 0x4d000,
2407 .enable_mask = BIT(0),
2421 .halt_reg = 0x4e000,
2424 .enable_reg = 0x4e000,
2425 .enable_mask = BIT(0),
2439 .halt_reg = 0x4f000,
2442 .enable_reg = 0x4f000,
2443 .enable_mask = BIT(0),
2457 .halt_reg = 0x36004,
2459 .hwcg_reg = 0x36004,
2462 .enable_reg = 0x36004,
2463 .enable_mask = BIT(0),
2475 .enable_reg = 0x79004,
2492 .enable_reg = 0x79004,
2507 .halt_reg = 0x3600c,
2509 .hwcg_reg = 0x3600c,
2512 .enable_reg = 0x3600c,
2513 .enable_mask = BIT(0),
2522 .halt_reg = 0x36018,
2525 .enable_reg = 0x36018,
2526 .enable_mask = BIT(0),
2535 .halt_reg = 0x36048,
2537 .hwcg_reg = 0x36048,
2540 .enable_reg = 0x79004,
2550 .halt_reg = 0x2000c,
2553 .enable_reg = 0x2000c,
2554 .enable_mask = BIT(0),
2568 .halt_reg = 0x20004,
2570 .hwcg_reg = 0x20004,
2573 .enable_reg = 0x20004,
2574 .enable_mask = BIT(0),
2583 .halt_reg = 0x20008,
2586 .enable_reg = 0x20008,
2587 .enable_mask = BIT(0),
2596 .halt_reg = 0x21004,
2598 .hwcg_reg = 0x21004,
2601 .enable_reg = 0x79004,
2611 .halt_reg = 0x17014,
2613 .hwcg_reg = 0x17014,
2616 .enable_reg = 0x7900c,
2617 .enable_mask = BIT(0),
2626 .halt_reg = 0x17060,
2628 .hwcg_reg = 0x17060,
2631 .enable_reg = 0x7900c,
2641 .halt_reg = 0x17018,
2643 .hwcg_reg = 0x17018,
2646 .enable_reg = 0x7900c,
2656 .halt_reg = 0x36040,
2658 .hwcg_reg = 0x36040,
2661 .enable_reg = 0x7900c,
2671 .halt_reg = 0x17010,
2673 .hwcg_reg = 0x17010,
2676 .enable_reg = 0x79004,
2686 .halt_reg = 0x1f014,
2689 .enable_reg = 0x7900c,
2699 .halt_reg = 0x1f00c,
2702 .enable_reg = 0x7900c,
2712 .halt_reg = 0x1f144,
2715 .enable_reg = 0x7900c,
2730 .halt_reg = 0x1f274,
2733 .enable_reg = 0x7900c,
2748 .halt_reg = 0x1f3a4,
2751 .enable_reg = 0x7900c,
2766 .halt_reg = 0x1f4d4,
2769 .enable_reg = 0x7900c,
2784 .halt_reg = 0x1f604,
2787 .enable_reg = 0x7900c,
2802 .halt_reg = 0x1f734,
2805 .enable_reg = 0x7900c,
2820 .halt_reg = 0x53014,
2823 .enable_reg = 0x7900c,
2833 .halt_reg = 0x5300c,
2836 .enable_reg = 0x7900c,
2846 .halt_reg = 0x53018,
2849 .enable_reg = 0x7900c,
2864 .halt_reg = 0x53148,
2867 .enable_reg = 0x7900c,
2882 .halt_reg = 0x53278,
2885 .enable_reg = 0x7900c,
2900 .halt_reg = 0x533a8,
2903 .enable_reg = 0x7900c,
2918 .halt_reg = 0x534d8,
2921 .enable_reg = 0x7900c,
2936 .halt_reg = 0x53608,
2939 .enable_reg = 0x7900c,
2954 .halt_reg = 0x1f004,
2956 .hwcg_reg = 0x1f004,
2959 .enable_reg = 0x7900c,
2969 .halt_reg = 0x1f008,
2971 .hwcg_reg = 0x1f008,
2974 .enable_reg = 0x7900c,
2984 .halt_reg = 0x53004,
2986 .hwcg_reg = 0x53004,
2989 .enable_reg = 0x7900c,
2999 .halt_reg = 0x53008,
3001 .hwcg_reg = 0x53008,
3004 .enable_reg = 0x7900c,
3014 .halt_reg = 0x38008,
3017 .enable_reg = 0x38008,
3018 .enable_mask = BIT(0),
3027 .halt_reg = 0x38004,
3030 .enable_reg = 0x38004,
3031 .enable_mask = BIT(0),
3045 .halt_reg = 0x3800c,
3047 .hwcg_reg = 0x3800c,
3050 .enable_reg = 0x3800c,
3051 .enable_mask = BIT(0),
3065 .halt_reg = 0x1e008,
3068 .enable_reg = 0x1e008,
3069 .enable_mask = BIT(0),
3078 .halt_reg = 0x1e004,
3081 .enable_reg = 0x1e004,
3082 .enable_mask = BIT(0),
3096 .halt_reg = 0x2b06c,
3098 .hwcg_reg = 0x2b06c,
3101 .enable_reg = 0x79004,
3102 .enable_mask = BIT(0),
3116 .halt_reg = 0x45098,
3119 .enable_reg = 0x45098,
3120 .enable_mask = BIT(0),
3134 .halt_reg = 0x1a080,
3136 .hwcg_reg = 0x1a080,
3139 .enable_reg = 0x1a080,
3140 .enable_mask = BIT(0),
3154 .halt_reg = 0x45014,
3156 .hwcg_reg = 0x45014,
3159 .enable_reg = 0x45014,
3160 .enable_mask = BIT(0),
3169 .halt_reg = 0x45010,
3171 .hwcg_reg = 0x45010,
3174 .enable_reg = 0x45010,
3175 .enable_mask = BIT(0),
3189 .halt_reg = 0x45044,
3191 .hwcg_reg = 0x45044,
3194 .enable_reg = 0x45044,
3195 .enable_mask = BIT(0),
3209 .halt_reg = 0x45078,
3211 .hwcg_reg = 0x45078,
3214 .enable_reg = 0x45078,
3215 .enable_mask = BIT(0),
3229 .halt_reg = 0x4501c,
3232 .enable_reg = 0x4501c,
3233 .enable_mask = BIT(0),
3242 .halt_reg = 0x45018,
3245 .enable_reg = 0x45018,
3246 .enable_mask = BIT(0),
3255 .halt_reg = 0x45040,
3257 .hwcg_reg = 0x45040,
3260 .enable_reg = 0x45040,
3261 .enable_mask = BIT(0),
3275 .halt_reg = 0x1a010,
3278 .enable_reg = 0x1a010,
3279 .enable_mask = BIT(0),
3293 .halt_reg = 0x1a018,
3296 .enable_reg = 0x1a018,
3297 .enable_mask = BIT(0),
3311 .halt_reg = 0x1a014,
3314 .enable_reg = 0x1a014,
3315 .enable_mask = BIT(0),
3324 .halt_reg = 0x8c000,
3327 .enable_reg = 0x8c000,
3328 .enable_mask = BIT(0),
3337 .halt_reg = 0x8c00c,
3340 .enable_reg = 0x8c00c,
3341 .enable_mask = BIT(0),
3350 .halt_reg = 0x8c010,
3353 .enable_reg = 0x8c010,
3354 .enable_mask = BIT(0),
3363 .halt_reg = 0x1a054,
3366 .enable_reg = 0x1a054,
3367 .enable_mask = BIT(0),
3381 .halt_reg = 0x1a058,
3383 .hwcg_reg = 0x1a058,
3386 .enable_reg = 0x1a058,
3387 .enable_mask = BIT(0),
3396 .halt_reg = 0x6e008,
3399 .enable_reg = 0x6e008,
3400 .enable_mask = BIT(0),
3409 .halt_reg = 0x6e010,
3412 .enable_reg = 0x6e010,
3413 .enable_mask = BIT(0),
3422 .halt_reg = 0x6e004,
3425 .enable_reg = 0x6e004,
3426 .enable_mask = BIT(0),
3435 .halt_reg = 0x17004,
3437 .hwcg_reg = 0x17004,
3440 .enable_reg = 0x17004,
3441 .enable_mask = BIT(0),
3451 .halt_reg = 0x1701c,
3453 .hwcg_reg = 0x1701c,
3456 .enable_reg = 0x1701c,
3457 .enable_mask = BIT(0),
3466 .halt_reg = 0x17068,
3468 .hwcg_reg = 0x17068,
3471 .enable_reg = 0x79004,
3481 .halt_reg = 0x580a4,
3483 .hwcg_reg = 0x580a4,
3486 .enable_reg = 0x580a4,
3487 .enable_mask = BIT(0),
3501 .halt_reg = 0x5808c,
3504 .enable_reg = 0x5808c,
3505 .enable_mask = BIT(0),
3519 .halt_reg = 0x17024,
3522 .enable_reg = 0x17024,
3523 .enable_mask = BIT(0),
3532 .gdscr = 0x1a004,
3540 .gdscr = 0x45004,
3548 .gdscr = 0x58004,
3556 .gdscr = 0x5807c,
3564 .gdscr = 0x58098,
3573 .gdscr = 0x7d074,
3582 .gdscr = 0x7d078,
3591 .gdscr = 0x7d060,
3600 .gdscr = 0x7d07c,
3795 [GCC_MMSS_BCR] = { 0x17000 },
3796 [GCC_USB30_PRIM_BCR] = { 0x1a000 },
3797 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
3798 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x1b020 },
3799 [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
3800 [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 },
3801 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
3802 [GCC_SDCC2_BCR] = { 0x1e000 },
3803 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x1f000 },
3804 [GCC_PDM_BCR] = { 0x20000 },
3805 [GCC_GPU_BCR] = { 0x36000 },
3806 [GCC_SDCC1_BCR] = { 0x38000 },
3807 [GCC_UFS_PHY_BCR] = { 0x45000 },
3808 [GCC_CAMSS_TFE_BCR] = { 0x52000 },
3809 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x53000 },
3810 [GCC_CAMSS_OPE_BCR] = { 0x55000 },
3811 [GCC_CAMSS_TOP_BCR] = { 0x58000 },
3812 [GCC_VENUS_BCR] = { 0x58078 },
3813 [GCC_VCODEC0_BCR] = { 0x58094 },
3814 [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 },
3849 .max_register = 0xc7000,
3886 regmap_update_bits(regmap, 0x17028, BIT(0), BIT(0)); in gcc_sm6375_probe()
3887 regmap_update_bits(regmap, 0x2b004, BIT(0), BIT(0)); in gcc_sm6375_probe()
3888 regmap_update_bits(regmap, 0x1702c, BIT(0), BIT(0)); in gcc_sm6375_probe()