Lines Matching +full:0 +full:x4e000
49 { 500000000, 1250000000, 0 },
57 .offset = 0x0,
62 .enable_reg = 0x79000,
63 .enable_mask = BIT(0),
76 { 0x1, 2 },
81 .offset = 0x0,
96 { 0x0, 1 },
101 .offset = 0x0,
117 .l = 0x3c,
118 .vco_val = 0x1 << 20,
120 .main_output_mask = BIT(0),
121 .config_ctl_val = 0x4001055b,
125 .offset = 0xa000,
130 .enable_reg = 0x79000,
144 { 0x0, 1 },
149 .offset = 0xa000,
166 .l = 0x1F,
167 .alpha = 0x0,
168 .alpha_hi = 0x40,
170 .vco_val = 0x2 << 20,
172 .config_ctl_val = 0x4001055b,
176 .offset = 0xb000,
182 .enable_reg = 0x79000,
196 { 0x0, 1 },
201 .offset = 0xb000,
217 .offset = 0x3000,
222 .enable_reg = 0x79000,
236 .offset = 0x4000,
241 .enable_reg = 0x79000,
255 { 0x0, 1 },
260 .offset = 0x4000,
275 .offset = 0x6000,
280 .enable_reg = 0x79000,
294 { 0x1, 2 },
299 .offset = 0x6000,
314 .offset = 0x7000,
319 .enable_reg = 0x79000,
333 { 0x0, 1 },
338 .offset = 0x7000,
354 .l = 0x29,
355 .alpha = 0xAAAAAAAA,
356 .alpha_hi = 0xAA,
358 .vco_val = 0x2 << 20,
360 .main_output_mask = BIT(0),
362 .post_div_val = 0x1 << 8,
364 .config_ctl_val = 0x4001055b,
368 .offset = 0x8000,
374 .enable_reg = 0x79000,
388 { 0x1, 2 },
393 .offset = 0x8000,
410 .l = 0x3C,
411 .alpha = 0x0,
412 .post_div_val = 0x1 << 8,
414 .main_output_mask = BIT(0),
415 .config_ctl_val = 0x00004289,
419 .offset = 0x9000,
424 .enable_reg = 0x79000,
438 { 0x1, 2 },
443 .offset = 0x9000,
459 { P_BI_TCXO, 0 },
471 { P_BI_TCXO, 0 },
485 { P_BI_TCXO, 0 },
499 { P_BI_TCXO, 0 },
515 { P_BI_TCXO, 0 },
529 { P_BI_TCXO, 0 },
547 { P_BI_TCXO, 0 },
567 { P_BI_TCXO, 0 },
585 { P_BI_TCXO, 0 },
605 { P_BI_TCXO, 0 },
625 { P_BI_TCXO, 0 },
643 { P_BI_TCXO, 0 },
659 { P_BI_TCXO, 0 },
669 { P_BI_TCXO, 0 },
679 F(19200000, P_BI_TCXO, 1, 0, 0),
680 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
681 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
682 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
687 .cmd_rcgr = 0x5802c,
688 .mnd_width = 0,
702 F(19200000, P_BI_TCXO, 1, 0, 0),
703 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
708 .cmd_rcgr = 0x56000,
709 .mnd_width = 0,
723 F(19200000, P_BI_TCXO, 1, 0, 0),
724 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
725 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
726 F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0),
731 .cmd_rcgr = 0x59000,
732 .mnd_width = 0,
746 .cmd_rcgr = 0x5901c,
747 .mnd_width = 0,
761 .cmd_rcgr = 0x59038,
762 .mnd_width = 0,
776 F(19200000, P_BI_TCXO, 1, 0, 0),
783 .cmd_rcgr = 0x51000,
798 .cmd_rcgr = 0x5101c,
813 .cmd_rcgr = 0x51038,
828 .cmd_rcgr = 0x51054,
843 F(19200000, P_BI_TCXO, 1, 0, 0),
844 F(171428571, P_GPLL0_OUT_EARLY, 3.5, 0, 0),
845 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
850 .cmd_rcgr = 0x55024,
851 .mnd_width = 0,
865 F(19200000, P_BI_TCXO, 1, 0, 0),
866 F(200000000, P_GPLL8_OUT_MAIN, 2, 0, 0),
867 F(266600000, P_GPLL8_OUT_MAIN, 1, 0, 0),
868 F(465000000, P_GPLL8_OUT_MAIN, 1, 0, 0),
869 F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0),
874 .cmd_rcgr = 0x55004,
875 .mnd_width = 0,
889 F(19200000, P_BI_TCXO, 1, 0, 0),
890 F(128000000, P_GPLL10_OUT_MAIN, 9, 0, 0),
891 F(135529412, P_GPLL10_OUT_MAIN, 8.5, 0, 0),
892 F(144000000, P_GPLL10_OUT_MAIN, 8, 0, 0),
893 F(153600000, P_GPLL10_OUT_MAIN, 7.5, 0, 0),
894 F(164571429, P_GPLL10_OUT_MAIN, 7, 0, 0),
895 F(177230769, P_GPLL10_OUT_MAIN, 6.5, 0, 0),
896 F(192000000, P_GPLL10_OUT_MAIN, 6, 0, 0),
897 F(209454545, P_GPLL10_OUT_MAIN, 5.5, 0, 0),
898 F(230400000, P_GPLL10_OUT_MAIN, 5, 0, 0),
899 F(256000000, P_GPLL10_OUT_MAIN, 4.5, 0, 0),
900 F(288000000, P_GPLL10_OUT_MAIN, 4, 0, 0),
901 F(329142857, P_GPLL10_OUT_MAIN, 3.5, 0, 0),
902 F(384000000, P_GPLL10_OUT_MAIN, 3, 0, 0),
903 F(460800000, P_GPLL10_OUT_MAIN, 2.5, 0, 0),
904 F(576000000, P_GPLL10_OUT_MAIN, 2, 0, 0),
909 .cmd_rcgr = 0x52004,
924 F(19200000, P_BI_TCXO, 1, 0, 0),
925 F(120000000, P_GPLL0_OUT_EARLY, 5, 0, 0),
926 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
927 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
928 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
929 F(426400000, P_GPLL3_OUT_EARLY, 2.5, 0, 0),
934 .cmd_rcgr = 0x52094,
935 .mnd_width = 0,
949 .cmd_rcgr = 0x52024,
964 .cmd_rcgr = 0x520b4,
965 .mnd_width = 0,
979 .cmd_rcgr = 0x52044,
994 .cmd_rcgr = 0x520d4,
995 .mnd_width = 0,
1009 F(19200000, P_BI_TCXO, 1, 0, 0),
1010 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1012 F(384000000, P_GPLL6_OUT_EARLY, 2, 0, 0),
1017 .cmd_rcgr = 0x52064,
1032 F(19200000, P_BI_TCXO, 1, 0, 0),
1033 F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0),
1034 F(80000000, P_GPLL0_OUT_EARLY, 7.5, 0, 0),
1039 .cmd_rcgr = 0x58010,
1040 .mnd_width = 0,
1054 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1055 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1056 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1057 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
1062 .cmd_rcgr = 0x4d004,
1076 .cmd_rcgr = 0x4e004,
1090 .cmd_rcgr = 0x4f004,
1104 F(19200000, P_BI_TCXO, 1, 0, 0),
1105 F(60000000, P_GPLL0_OUT_AUX2, 5, 0, 0),
1110 .cmd_rcgr = 0x20010,
1111 .mnd_width = 0,
1126 F(19200000, P_BI_TCXO, 1, 0, 0),
1131 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1134 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1138 F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0),
1139 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
1151 .cmd_rcgr = 0x1f148,
1167 .cmd_rcgr = 0x1f278,
1183 .cmd_rcgr = 0x1f3a8,
1199 .cmd_rcgr = 0x1f4d8,
1215 .cmd_rcgr = 0x1f608,
1231 .cmd_rcgr = 0x1f738,
1244 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1245 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1246 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
1247 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
1252 .cmd_rcgr = 0x38028,
1266 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1267 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1268 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
1269 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1270 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
1275 .cmd_rcgr = 0x38010,
1276 .mnd_width = 0,
1290 F(19200000, P_BI_TCXO, 1, 0, 0),
1291 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1292 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1293 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1294 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1299 .cmd_rcgr = 0x1e00c,
1314 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1315 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1316 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1317 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1318 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1323 .cmd_rcgr = 0x45020,
1337 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
1338 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1339 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
1340 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
1345 .cmd_rcgr = 0x45048,
1346 .mnd_width = 0,
1359 F(9600000, P_BI_TCXO, 2, 0, 0),
1360 F(19200000, P_BI_TCXO, 1, 0, 0),
1365 .cmd_rcgr = 0x4507c,
1366 .mnd_width = 0,
1379 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
1380 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1381 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
1386 .cmd_rcgr = 0x45060,
1387 .mnd_width = 0,
1400 F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0),
1401 F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0),
1402 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1403 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1408 .cmd_rcgr = 0x1a01c,
1422 F(19200000, P_BI_TCXO, 1, 0, 0),
1427 .cmd_rcgr = 0x1a034,
1428 .mnd_width = 0,
1441 .reg = 0x1a04c,
1442 .shift = 0,
1454 .cmd_rcgr = 0x1a060,
1455 .mnd_width = 0,
1468 F(133333333, P_GPLL11_OUT_MAIN, 4.5, 0, 0),
1469 F(240000000, P_GPLL11_OUT_MAIN, 2.5, 0, 0),
1470 F(300000000, P_GPLL11_OUT_MAIN, 2, 0, 0),
1471 F(384000000, P_GPLL11_OUT_MAIN, 2, 0, 0),
1476 .cmd_rcgr = 0x58060,
1477 .mnd_width = 0,
1491 .halt_reg = 0x1d004,
1493 .hwcg_reg = 0x1d004,
1496 .enable_reg = 0x1d004,
1497 .enable_mask = BIT(0),
1506 .halt_reg = 0x1d008,
1508 .hwcg_reg = 0x1d008,
1511 .enable_reg = 0x1d008,
1512 .enable_mask = BIT(0),
1521 .halt_reg = 0x71154,
1523 .hwcg_reg = 0x71154,
1526 .enable_reg = 0x71154,
1527 .enable_mask = BIT(0),
1536 .halt_reg = 0x23004,
1538 .hwcg_reg = 0x23004,
1541 .enable_reg = 0x79004,
1551 .halt_reg = 0x17070,
1553 .hwcg_reg = 0x17070,
1556 .enable_reg = 0x79004,
1566 .halt_reg = 0x1706c,
1568 .hwcg_reg = 0x1706c,
1571 .enable_reg = 0x79004,
1581 .halt_reg = 0x17008,
1583 .hwcg_reg = 0x17008,
1586 .enable_reg = 0x17008,
1587 .enable_mask = BIT(0),
1597 .halt_reg = 0x17028,
1600 .enable_reg = 0x17028,
1601 .enable_mask = BIT(0),
1611 .halt_reg = 0x58044,
1614 .enable_reg = 0x58044,
1615 .enable_mask = BIT(0),
1629 .halt_reg = 0x5804c,
1631 .hwcg_reg = 0x5804c,
1634 .enable_reg = 0x5804c,
1635 .enable_mask = BIT(0),
1644 .halt_reg = 0x58050,
1646 .hwcg_reg = 0x58050,
1649 .enable_reg = 0x58050,
1650 .enable_mask = BIT(0),
1659 .halt_reg = 0x56018,
1662 .enable_reg = 0x56018,
1663 .enable_mask = BIT(0),
1677 .halt_reg = 0x52088,
1680 .enable_reg = 0x52088,
1681 .enable_mask = BIT(0),
1695 .halt_reg = 0x5208c,
1698 .enable_reg = 0x5208c,
1699 .enable_mask = BIT(0),
1713 .halt_reg = 0x52090,
1716 .enable_reg = 0x52090,
1717 .enable_mask = BIT(0),
1731 .halt_reg = 0x59018,
1734 .enable_reg = 0x59018,
1735 .enable_mask = BIT(0),
1749 .halt_reg = 0x59034,
1752 .enable_reg = 0x59034,
1753 .enable_mask = BIT(0),
1767 .halt_reg = 0x59050,
1770 .enable_reg = 0x59050,
1771 .enable_mask = BIT(0),
1785 .halt_reg = 0x51018,
1788 .enable_reg = 0x51018,
1789 .enable_mask = BIT(0),
1803 .halt_reg = 0x51034,
1806 .enable_reg = 0x51034,
1807 .enable_mask = BIT(0),
1821 .halt_reg = 0x51050,
1824 .enable_reg = 0x51050,
1825 .enable_mask = BIT(0),
1839 .halt_reg = 0x5106c,
1842 .enable_reg = 0x5106c,
1843 .enable_mask = BIT(0),
1857 .halt_reg = 0x58054,
1860 .enable_reg = 0x58054,
1861 .enable_mask = BIT(0),
1870 .halt_reg = 0x5503c,
1873 .enable_reg = 0x5503c,
1874 .enable_mask = BIT(0),
1888 .halt_reg = 0x5501c,
1891 .enable_reg = 0x5501c,
1892 .enable_mask = BIT(0),
1906 .halt_reg = 0x5805c,
1909 .enable_reg = 0x5805c,
1910 .enable_mask = BIT(0),
1919 .halt_reg = 0x5201c,
1922 .enable_reg = 0x5201c,
1923 .enable_mask = BIT(0),
1937 .halt_reg = 0x5207c,
1940 .enable_reg = 0x5207c,
1941 .enable_mask = BIT(0),
1955 .halt_reg = 0x520ac,
1958 .enable_reg = 0x520ac,
1959 .enable_mask = BIT(0),
1973 .halt_reg = 0x5203c,
1976 .enable_reg = 0x5203c,
1977 .enable_mask = BIT(0),
1991 .halt_reg = 0x52080,
1994 .enable_reg = 0x52080,
1995 .enable_mask = BIT(0),
2009 .halt_reg = 0x520cc,
2012 .enable_reg = 0x520cc,
2013 .enable_mask = BIT(0),
2027 .halt_reg = 0x5205c,
2030 .enable_reg = 0x5205c,
2031 .enable_mask = BIT(0),
2045 .halt_reg = 0x52084,
2048 .enable_reg = 0x52084,
2049 .enable_mask = BIT(0),
2063 .halt_reg = 0x520ec,
2066 .enable_reg = 0x520ec,
2067 .enable_mask = BIT(0),
2081 .halt_reg = 0x58028,
2084 .enable_reg = 0x58028,
2085 .enable_mask = BIT(0),
2099 .halt_reg = 0x1a084,
2101 .hwcg_reg = 0x1a084,
2104 .enable_reg = 0x1a084,
2105 .enable_mask = BIT(0),
2119 .halt_reg = 0x2b004,
2121 .hwcg_reg = 0x2b004,
2124 .enable_reg = 0x79004,
2135 .halt_reg = 0x1700c,
2137 .hwcg_reg = 0x1700c,
2140 .enable_reg = 0x1700c,
2141 .enable_mask = BIT(0),
2151 .reg = 0x17058,
2152 .shift = 0,
2165 .enable_reg = 0x79004,
2180 .halt_reg = 0x17020,
2182 .hwcg_reg = 0x17020,
2185 .enable_reg = 0x17020,
2186 .enable_mask = BIT(0),
2195 .halt_reg = 0x17064,
2197 .hwcg_reg = 0x17064,
2200 .enable_reg = 0x7900c,
2210 .halt_reg = 0x1702c,
2213 .enable_reg = 0x1702c,
2214 .enable_mask = BIT(0),
2224 .halt_reg = 0x4d000,
2227 .enable_reg = 0x4d000,
2228 .enable_mask = BIT(0),
2242 .halt_reg = 0x4e000,
2245 .enable_reg = 0x4e000,
2246 .enable_mask = BIT(0),
2260 .halt_reg = 0x4f000,
2263 .enable_reg = 0x4f000,
2264 .enable_mask = BIT(0),
2278 .halt_reg = 0x36004,
2280 .hwcg_reg = 0x36004,
2283 .enable_reg = 0x36004,
2284 .enable_mask = BIT(0),
2296 .enable_reg = 0x79004,
2313 .enable_reg = 0x79004,
2328 .halt_reg = 0x36100,
2331 .enable_reg = 0x36100,
2332 .enable_mask = BIT(0),
2341 .halt_reg = 0x3600c,
2343 .hwcg_reg = 0x3600c,
2346 .enable_reg = 0x3600c,
2347 .enable_mask = BIT(0),
2356 .halt_reg = 0x36018,
2359 .enable_reg = 0x36018,
2360 .enable_mask = BIT(0),
2369 .halt_reg = 0x36048,
2371 .hwcg_reg = 0x36048,
2374 .enable_reg = 0x79004,
2384 .halt_reg = 0x2000c,
2387 .enable_reg = 0x2000c,
2388 .enable_mask = BIT(0),
2402 .halt_reg = 0x20004,
2404 .hwcg_reg = 0x20004,
2407 .enable_reg = 0x20004,
2408 .enable_mask = BIT(0),
2417 .halt_reg = 0x20008,
2420 .enable_reg = 0x20008,
2421 .enable_mask = BIT(0),
2430 .halt_reg = 0x21004,
2432 .hwcg_reg = 0x21004,
2435 .enable_reg = 0x79004,
2445 .halt_reg = 0x17014,
2447 .hwcg_reg = 0x17014,
2450 .enable_reg = 0x7900c,
2451 .enable_mask = BIT(0),
2460 .halt_reg = 0x17060,
2462 .hwcg_reg = 0x17060,
2465 .enable_reg = 0x7900c,
2475 .halt_reg = 0x17018,
2477 .hwcg_reg = 0x17018,
2480 .enable_reg = 0x7900c,
2490 .halt_reg = 0x36040,
2492 .hwcg_reg = 0x36040,
2495 .enable_reg = 0x7900c,
2505 .halt_reg = 0x17010,
2507 .hwcg_reg = 0x17010,
2510 .enable_reg = 0x79004,
2520 .halt_reg = 0x1f014,
2523 .enable_reg = 0x7900c,
2533 .halt_reg = 0x1f00c,
2536 .enable_reg = 0x7900c,
2546 .halt_reg = 0x1f144,
2549 .enable_reg = 0x7900c,
2564 .halt_reg = 0x1f274,
2567 .enable_reg = 0x7900c,
2582 .halt_reg = 0x1f3a4,
2585 .enable_reg = 0x7900c,
2600 .halt_reg = 0x1f4d4,
2603 .enable_reg = 0x7900c,
2618 .halt_reg = 0x1f604,
2621 .enable_reg = 0x7900c,
2636 .halt_reg = 0x1f734,
2639 .enable_reg = 0x7900c,
2654 .halt_reg = 0x1f004,
2656 .hwcg_reg = 0x1f004,
2659 .enable_reg = 0x7900c,
2669 .halt_reg = 0x1f008,
2671 .hwcg_reg = 0x1f008,
2674 .enable_reg = 0x7900c,
2684 .halt_reg = 0x38008,
2687 .enable_reg = 0x38008,
2688 .enable_mask = BIT(0),
2697 .halt_reg = 0x38004,
2700 .enable_reg = 0x38004,
2701 .enable_mask = BIT(0),
2715 .halt_reg = 0x3800c,
2717 .hwcg_reg = 0x3800c,
2720 .enable_reg = 0x3800c,
2721 .enable_mask = BIT(0),
2735 .halt_reg = 0x1e008,
2738 .enable_reg = 0x1e008,
2739 .enable_mask = BIT(0),
2748 .halt_reg = 0x1e004,
2751 .enable_reg = 0x1e004,
2752 .enable_mask = BIT(0),
2766 .halt_reg = 0x2b06c,
2768 .hwcg_reg = 0x2b06c,
2771 .enable_reg = 0x79004,
2772 .enable_mask = BIT(0),
2782 .halt_reg = 0x45098,
2785 .enable_reg = 0x45098,
2786 .enable_mask = BIT(0),
2800 .halt_reg = 0x1a080,
2802 .hwcg_reg = 0x1a080,
2805 .enable_reg = 0x1a080,
2806 .enable_mask = BIT(0),
2820 .halt_reg = 0x8c000,
2823 .enable_reg = 0x8c000,
2824 .enable_mask = BIT(0),
2833 .halt_reg = 0x45014,
2835 .hwcg_reg = 0x45014,
2838 .enable_reg = 0x45014,
2839 .enable_mask = BIT(0),
2848 .halt_reg = 0x45010,
2850 .hwcg_reg = 0x45010,
2853 .enable_reg = 0x45010,
2854 .enable_mask = BIT(0),
2868 .halt_reg = 0x45044,
2870 .hwcg_reg = 0x45044,
2873 .enable_reg = 0x45044,
2874 .enable_mask = BIT(0),
2888 .halt_reg = 0x45078,
2890 .hwcg_reg = 0x45078,
2893 .enable_reg = 0x45078,
2894 .enable_mask = BIT(0),
2908 .halt_reg = 0x4501c,
2911 .enable_reg = 0x4501c,
2912 .enable_mask = BIT(0),
2921 .halt_reg = 0x45018,
2924 .enable_reg = 0x45018,
2925 .enable_mask = BIT(0),
2934 .halt_reg = 0x45040,
2936 .hwcg_reg = 0x45040,
2939 .enable_reg = 0x45040,
2940 .enable_mask = BIT(0),
2954 .halt_reg = 0x1a010,
2957 .enable_reg = 0x1a010,
2958 .enable_mask = BIT(0),
2972 .halt_reg = 0x1a018,
2975 .enable_reg = 0x1a018,
2976 .enable_mask = BIT(0),
2990 .halt_reg = 0x1a014,
2993 .enable_reg = 0x1a014,
2994 .enable_mask = BIT(0),
3003 .halt_reg = 0x9f000,
3006 .enable_reg = 0x9f000,
3007 .enable_mask = BIT(0),
3016 .halt_reg = 0x1a054,
3019 .enable_reg = 0x1a054,
3020 .enable_mask = BIT(0),
3034 .halt_reg = 0x1a058,
3036 .hwcg_reg = 0x1a058,
3039 .enable_reg = 0x1a058,
3040 .enable_mask = BIT(0),
3049 .halt_reg = 0x6e008,
3052 .enable_reg = 0x6e008,
3053 .enable_mask = BIT(0),
3062 .halt_reg = 0x6e010,
3065 .enable_reg = 0x6e010,
3066 .enable_mask = BIT(0),
3075 .halt_reg = 0x6e004,
3078 .enable_reg = 0x6e004,
3079 .enable_mask = BIT(0),
3088 .halt_reg = 0x17004,
3090 .hwcg_reg = 0x17004,
3093 .enable_reg = 0x17004,
3094 .enable_mask = BIT(0),
3103 .halt_reg = 0x1701c,
3105 .hwcg_reg = 0x1701c,
3108 .enable_reg = 0x1701c,
3109 .enable_mask = BIT(0),
3118 .halt_reg = 0x17068,
3120 .hwcg_reg = 0x17068,
3123 .enable_reg = 0x79004,
3133 .halt_reg = 0x580a4,
3135 .hwcg_reg = 0x580a4,
3138 .enable_reg = 0x580a4,
3139 .enable_mask = BIT(0),
3153 .halt_reg = 0x5808c,
3156 .enable_reg = 0x5808c,
3157 .enable_mask = BIT(0),
3171 .halt_reg = 0x17024,
3174 .enable_reg = 0x17024,
3175 .enable_mask = BIT(0),
3184 .gdscr = 0x58004,
3192 .gdscr = 0x45004,
3200 .gdscr = 0x1a004,
3208 .gdscr = 0x58098,
3216 .gdscr = 0x5807c,
3224 .gdscr = 0x7d060,
3233 .gdscr = 0x7d07c,
3242 .gdscr = 0x7d074,
3251 .gdscr = 0x7d078,
3429 [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
3430 [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 },
3431 [GCC_SDCC1_BCR] = { 0x38000 },
3432 [GCC_SDCC2_BCR] = { 0x1e000 },
3433 [GCC_UFS_PHY_BCR] = { 0x45000 },
3434 [GCC_USB30_PRIM_BCR] = { 0x1a000 },
3435 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
3436 [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 },
3437 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
3438 [GCC_VCODEC0_BCR] = { 0x58094 },
3439 [GCC_VENUS_BCR] = { 0x58078 },
3440 [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 },
3468 .max_register = 0xc7000,