Lines Matching +full:0 +full:x4e000
42 { P_XO, 0 },
60 { P_XO, 0 },
70 { P_XO, 0 },
84 { P_XO, 0 },
98 { P_XO, 0 },
110 { P_XO, 0 },
124 { P_XO, 0 },
138 { P_XO, 0 },
156 { P_XO, 0 },
168 { P_XO, 0 },
184 { P_XO, 0 },
196 { P_XO, 0 },
208 { P_XO, 0 },
222 { P_XO, 0 },
238 { P_XO, 0 },
252 { P_XO, 0 },
264 { P_XO, 0 },
289 .offset = 0x21000,
292 .enable_reg = 0x45008,
305 .offset = 0x21000,
309 .enable_reg = 0x45000,
310 .enable_mask = BIT(0),
322 .offset = 0x21000,
326 .enable_reg = 0x45000,
327 .enable_mask = BIT(0),
339 .offset = 0x20000,
342 .enable_reg = 0x45000,
356 .alpha = 0x0,
358 .post_div_mask = 0xf << 8,
359 .post_div_val = 0x1 << 8,
360 .vco_mask = 0x3 << 20,
361 .main_output_mask = 0x1,
362 .config_ctl_val = 0x4001055b,
366 { 700000000, 1400000000, 0 },
370 .offset = 0x22000,
385 .offset = 0x24000,
388 .enable_reg = 0x45000,
400 .l_reg = 0x37004,
401 .m_reg = 0x37008,
402 .n_reg = 0x3700C,
403 .config_reg = 0x37014,
404 .mode_reg = 0x37000,
405 .status_reg = 0x3701C,
416 .enable_reg = 0x45000,
427 F(19200000, P_XO, 1, 0, 0),
428 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
429 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
430 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
435 .cmd_rcgr = 0x46000,
436 .mnd_width = 0,
450 F(19200000, P_XO, 1, 0, 0),
451 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
456 .cmd_rcgr = 0x602c,
457 .mnd_width = 0,
471 F(4800000, P_XO, 4, 0, 0),
472 F(9600000, P_XO, 2, 0, 0),
474 F(19200000, P_XO, 1, 0, 0),
476 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
481 .cmd_rcgr = 0x6034,
495 .cmd_rcgr = 0x200c,
496 .mnd_width = 0,
510 F(4800000, P_XO, 4, 0, 0),
511 F(9600000, P_XO, 2, 0, 0),
514 F(19200000, P_XO, 1, 0, 0),
520 .cmd_rcgr = 0x2024,
534 .cmd_rcgr = 0x3000,
535 .mnd_width = 0,
549 F(4800000, P_XO, 4, 0, 0),
550 F(9600000, P_XO, 2, 0, 0),
553 F(19200000, P_XO, 1, 0, 0),
560 .cmd_rcgr = 0x3014,
574 .cmd_rcgr = 0x4000,
575 .mnd_width = 0,
588 .cmd_rcgr = 0x4024,
602 .cmd_rcgr = 0x5000,
603 .mnd_width = 0,
616 .cmd_rcgr = 0x5024,
634 F(19200000, P_XO, 1, 0, 0),
650 .cmd_rcgr = 0x600c,
664 .cmd_rcgr = 0x2044,
678 .cmd_rcgr = 0x3034,
692 .cmd_rcgr = 0x4014,
695 .cfg_off = 0x20,
707 .cmd_rcgr = 0xc00c,
708 .mnd_width = 0,
721 .cmd_rcgr = 0xc024,
735 .cmd_rcgr = 0xc044,
749 .cmd_rcgr = 0x4d044,
750 .mnd_width = 0,
764 F(50000000, P_GPLL1_OUT_MAIN, 10, 0, 0),
765 F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
766 F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
771 .cmd_rcgr = 0x4e01c,
785 F(50000000, P_GPLL1_OUT_MAIN, 10, 0, 0),
786 F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
787 F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
792 .cmd_rcgr = 0x4e014,
793 .mnd_width = 0,
806 F(19200000, P_XO, 1, 0, 0),
811 .cmd_rcgr = 0x4d05c,
812 .mnd_width = 0,
825 F(19200000, P_XO, 1, 0, 0),
826 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
827 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
828 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
829 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
830 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
831 F(228571429, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
832 F(240000000, P_GPLL6_OUT_AUX, 4.5, 0, 0),
833 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
834 F(270000000, P_GPLL6_OUT_AUX, 4, 0, 0),
835 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
836 F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
837 F(484800000, P_GPLL3_OUT_MAIN, 1, 0, 0),
838 F(523200000, P_GPLL3_OUT_MAIN, 1, 0, 0),
839 F(550000000, P_GPLL3_OUT_MAIN, 1, 0, 0),
840 F(598000000, P_GPLL3_OUT_MAIN, 1, 0, 0),
845 .cmd_rcgr = 0x59000,
846 .mnd_width = 0,
859 F(19200000, P_XO, 1, 0, 0),
860 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
861 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
866 .cmd_rcgr = 0x8004,
880 .cmd_rcgr = 0x9004,
894 .cmd_rcgr = 0xa004,
908 .cmd_rcgr = 0x4d0e4,
909 .mnd_width = 0,
922 .cmd_rcgr = 0x4d0dc,
923 .mnd_width = 0,
936 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
937 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
938 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
939 F(145454545, P_GPLL0_OUT_MAIN, 5.5, 0, 0),
940 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
941 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
942 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
943 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
944 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
949 .cmd_rcgr = 0x4d014,
950 .mnd_width = 0,
963 F(1200000, P_XO, 16, 0, 0),
968 .cmd_rcgr = 0x3e024,
982 F(19200000, P_XO, 1, 0, 0),
983 F(125000000, P_PCIE_0_PIPE_CLK, 2, 0, 0),
984 F(250000000, P_PCIE_0_PIPE_CLK, 1, 0, 0),
989 .cmd_rcgr = 0x3e01c,
990 .mnd_width = 0,
1003 .cmd_rcgr = 0x4d000,
1017 F(19200000, P_XO, 1, 0, 0),
1018 F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
1023 .cmd_rcgr = 0x44010,
1024 .mnd_width = 0,
1041 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1042 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1043 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1044 F(192000000, P_GPLL4_OUT_MAIN, 6, 0, 0),
1045 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1046 F(384000000, P_GPLL4_OUT_MAIN, 3, 0, 0),
1051 .cmd_rcgr = 0x42004,
1065 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1066 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1071 .cmd_rcgr = 0x5d000,
1089 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1090 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1091 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1092 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1097 .cmd_rcgr = 0x43004,
1111 .cmd_rcgr = 0x41048,
1112 .mnd_width = 0,
1125 F(19200000, P_XO, 1, 0, 0),
1126 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1127 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1128 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1133 .cmd_rcgr = 0x39028,
1147 .cmd_rcgr = 0x3901c,
1148 .mnd_width = 0,
1161 .cmd_rcgr = 0x3903c,
1162 .mnd_width = 0,
1175 F(19200000, P_XO, 1, 0, 0),
1176 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1177 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1178 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1179 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1184 .cmd_rcgr = 0x41010,
1185 .mnd_width = 0,
1198 .cmd_rcgr = 0x4d02c,
1199 .mnd_width = 0,
1212 F(19200000, P_XO, 1, 0, 0),
1213 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1214 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1215 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1220 .cmd_rcgr = 0x5e010,
1221 .mnd_width = 0,
1234 .halt_reg = 0x4601c,
1237 .enable_reg = 0x45004,
1252 .halt_reg = 0x5b004,
1255 .enable_reg = 0x4500c,
1265 .halt_reg = 0x59034,
1268 .enable_reg = 0x59034,
1269 .enable_mask = BIT(0),
1282 .halt_reg = 0x59030,
1285 .enable_reg = 0x59030,
1286 .enable_mask = BIT(0),
1295 .halt_reg = 0x31030,
1298 .enable_reg = 0x31030,
1299 .enable_mask = BIT(0),
1313 .halt_reg = 0x31038,
1316 .enable_reg = 0x31038,
1317 .enable_mask = BIT(0),
1326 .halt_reg = 0x1008,
1329 .enable_reg = 0x45004,
1339 .halt_reg = 0x77004,
1342 .enable_reg = 0x77004,
1343 .enable_mask = BIT(0),
1352 .halt_reg = 0x77008,
1355 .enable_reg = 0x77008,
1356 .enable_mask = BIT(0),
1365 .halt_reg = 0x6028,
1368 .enable_reg = 0x6028,
1369 .enable_mask = BIT(0),
1383 .halt_reg = 0x6024,
1386 .enable_reg = 0x6024,
1387 .enable_mask = BIT(0),
1401 .halt_reg = 0x2008,
1404 .enable_reg = 0x2008,
1405 .enable_mask = BIT(0),
1419 .halt_reg = 0x2004,
1422 .enable_reg = 0x2004,
1423 .enable_mask = BIT(0),
1437 .halt_reg = 0x3010,
1440 .enable_reg = 0x3010,
1441 .enable_mask = BIT(0),
1455 .halt_reg = 0x300c,
1458 .enable_reg = 0x300c,
1459 .enable_mask = BIT(0),
1473 .halt_reg = 0x4020,
1476 .enable_reg = 0x4020,
1477 .enable_mask = BIT(0),
1491 .halt_reg = 0x401c,
1494 .enable_reg = 0x401c,
1495 .enable_mask = BIT(0),
1509 .halt_reg = 0x5020,
1512 .enable_reg = 0x5020,
1513 .enable_mask = BIT(0),
1527 .halt_reg = 0x501c,
1530 .enable_reg = 0x501c,
1531 .enable_mask = BIT(0),
1545 .halt_reg = 0x6004,
1548 .enable_reg = 0x6004,
1549 .enable_mask = BIT(0),
1563 .halt_reg = 0x203c,
1566 .enable_reg = 0x203c,
1567 .enable_mask = BIT(0),
1581 .halt_reg = 0x302c,
1584 .enable_reg = 0x302c,
1585 .enable_mask = BIT(0),
1599 .halt_reg = 0x400c,
1602 .enable_reg = 0x400c,
1603 .enable_mask = BIT(0),
1617 .halt_reg = 0xb008,
1620 .enable_reg = 0x45004,
1630 .halt_reg = 0xc008,
1633 .enable_reg = 0xc008,
1634 .enable_mask = BIT(0),
1648 .halt_reg = 0xc004,
1651 .enable_reg = 0xc004,
1652 .enable_mask = BIT(0),
1666 .halt_reg = 0xc03c,
1669 .enable_reg = 0xc03c,
1670 .enable_mask = BIT(0),
1684 .halt_reg = 0x1300c,
1687 .enable_reg = 0x45004,
1697 .halt_reg = 0x16024,
1700 .enable_reg = 0x45004,
1701 .enable_mask = BIT(0),
1710 .halt_reg = 0x16020,
1713 .enable_reg = 0x45004,
1723 .halt_reg = 0x1601c,
1726 .enable_reg = 0x45004,
1736 .halt_reg = 0x4e010,
1739 .enable_reg = 0x4e010,
1740 .enable_mask = BIT(0),
1749 .halt_reg = 0x4e004,
1752 .enable_reg = 0x4e004,
1753 .enable_mask = BIT(0),
1767 .halt_reg = 0x4e008,
1770 .enable_reg = 0x4e008,
1771 .enable_mask = BIT(0),
1785 .halt_reg = 0x4e00c,
1788 .enable_reg = 0x4e00c,
1789 .enable_mask = BIT(0),
1798 .halt_reg = 0xf008,
1801 .enable_reg = 0xf008,
1802 .enable_mask = BIT(0),
1811 .halt_reg = 0xf004,
1814 .enable_reg = 0xf004,
1815 .enable_mask = BIT(0),
1824 .halt_reg = 0x12020,
1827 .enable_reg = 0x4500C,
1837 .halt_reg = 0x12010,
1840 .enable_reg = 0x4500C,
1850 .halt_reg = 0x1203c,
1853 .enable_reg = 0x13020,
1868 .halt_reg = 0x8000,
1871 .enable_reg = 0x8000,
1872 .enable_mask = BIT(0),
1886 .halt_reg = 0x9000,
1889 .enable_reg = 0x9000,
1890 .enable_mask = BIT(0),
1904 .halt_reg = 0xa000,
1907 .enable_reg = 0xa000,
1908 .enable_mask = BIT(0),
1922 .halt_reg = 0x12044,
1925 .enable_reg = 0x4500c,
1935 .halt_reg = 0x1201c,
1938 .enable_reg = 0x4500c,
1948 .halt_reg = 0x4d07c,
1951 .enable_reg = 0x4d07c,
1952 .enable_mask = BIT(0),
1961 .halt_reg = 0x4d080,
1964 .enable_reg = 0x4d080,
1965 .enable_mask = BIT(0),
1974 .halt_reg = 0x4d094,
1977 .enable_reg = 0x4d094,
1978 .enable_mask = BIT(0),
1992 .halt_reg = 0x4d098,
1995 .enable_reg = 0x4d098,
1996 .enable_mask = BIT(0),
2010 .halt_reg = 0x4d0d8,
2013 .enable_reg = 0x4d0d8,
2014 .enable_mask = BIT(0),
2028 .halt_reg = 0x4d0d4,
2031 .enable_reg = 0x4d0d4,
2032 .enable_mask = BIT(0),
2046 .halt_reg = 0x4d088,
2049 .enable_reg = 0x4d088,
2050 .enable_mask = BIT(0),
2064 .halt_reg = 0x4d084,
2067 .enable_reg = 0x4d084,
2068 .enable_mask = BIT(0),
2082 .halt_reg = 0x4d090,
2085 .enable_reg = 0x4d090,
2086 .enable_mask = BIT(0),
2100 .halt_reg = 0x59028,
2103 .enable_reg = 0x59028,
2104 .enable_mask = BIT(0),
2113 .halt_reg = 0x59020,
2116 .enable_reg = 0x59020,
2117 .enable_mask = BIT(0),
2131 .halt_reg = 0x3e014,
2134 .enable_reg = 0x45004,
2149 .halt_reg = 0x3e008,
2152 .enable_reg = 0x45004,
2162 .halt_reg = 0x3e018,
2165 .enable_reg = 0x45004,
2175 .halt_reg = 0x3e00c,
2178 .enable_reg = 0x45004,
2193 .halt_reg = 0x3e010,
2196 .enable_reg = 0x45004,
2206 .halt_reg = 0x27008,
2209 .enable_reg = 0x27008,
2210 .enable_mask = BIT(0),
2220 .halt_reg = 0x2700c,
2223 .enable_reg = 0x2700c,
2224 .enable_mask = BIT(0),
2234 .halt_reg = 0x4400c,
2237 .enable_reg = 0x4400c,
2238 .enable_mask = BIT(0),
2252 .halt_reg = 0x44004,
2255 .enable_reg = 0x44004,
2256 .enable_mask = BIT(0),
2265 .halt_reg = 0x13004,
2268 .enable_reg = 0x45004,
2279 .halt_reg = 0x44018,
2282 .enable_reg = 0x44018,
2283 .enable_mask = BIT(0),
2292 .halt_reg = 0x49004,
2295 .enable_reg = 0x49004,
2296 .enable_mask = BIT(0),
2305 .halt_reg = 0x4a004,
2308 .enable_reg = 0x4a004,
2309 .enable_mask = BIT(0),
2318 .halt_reg = 0x29084,
2321 .enable_reg = 0x45004,
2331 .halt_reg = 0x4201c,
2334 .enable_reg = 0x4201c,
2335 .enable_mask = BIT(0),
2344 .halt_reg = 0x42018,
2347 .enable_reg = 0x42018,
2348 .enable_mask = BIT(0),
2362 .halt_reg = 0x5d014,
2365 .enable_reg = 0x5d014,
2366 .enable_mask = BIT(0),
2380 .halt_reg = 0x5e004,
2383 .enable_reg = 0x5e004,
2384 .enable_mask = BIT(0),
2393 .halt_reg = 0x4301c,
2396 .enable_reg = 0x4301c,
2397 .enable_mask = BIT(0),
2406 .halt_reg = 0x43018,
2409 .enable_reg = 0x43018,
2410 .enable_mask = BIT(0),
2424 .halt_reg = 0x12038,
2427 .enable_reg = 0x3600C,
2437 .halt_reg = 0x26014,
2440 .enable_reg = 0x26014,
2441 .enable_mask = BIT(0),
2454 .halt_reg = 0x4100C,
2457 .enable_reg = 0x4100C,
2458 .enable_mask = BIT(0),
2467 .halt_reg = 0x41044,
2470 .enable_reg = 0x41044,
2471 .enable_mask = BIT(0),
2485 .halt_reg = 0x4102c,
2488 .enable_reg = 0x4102c,
2489 .enable_mask = BIT(0),
2498 .halt_reg = 0x3900c,
2501 .enable_reg = 0x3900c,
2502 .enable_mask = BIT(0),
2516 .halt_reg = 0x39014,
2519 .enable_reg = 0x39014,
2520 .enable_mask = BIT(0),
2534 .halt_reg = 0x39010,
2537 .enable_reg = 0x39010,
2538 .enable_mask = BIT(0),
2547 .halt_reg = 0x39044,
2550 .enable_reg = 0x39044,
2551 .enable_mask = BIT(0),
2567 .enable_reg = 0x39018,
2568 .enable_mask = BIT(0),
2577 .halt_reg = 0x41030,
2580 .enable_reg = 0x41030,
2581 .enable_mask = BIT(0),
2590 .halt_reg = 0x41004,
2593 .enable_reg = 0x41004,
2594 .enable_mask = BIT(0),
2608 .halt_reg = 0x1e004,
2611 .enable_reg = 0x1e004,
2612 .enable_mask = BIT(0),
2621 .halt_reg = 0x1e008,
2624 .enable_reg = 0x1e008,
2625 .enable_mask = BIT(0),
2784 [GCC_GENI_IR_BCR] = { 0x0F000 },
2785 [GCC_CDSP_RESTART] = { 0x18000 },
2786 [GCC_USB_HS_BCR] = { 0x41000 },
2787 [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
2788 [GCC_QUSB2_PHY_BCR] = { 0x4103c },
2789 [GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 },
2790 [GCC_USB2A_PHY_BCR] = { 0x0000c, 0 },
2791 [GCC_USB3_PHY_BCR] = { 0x39004 },
2792 [GCC_USB_30_BCR] = { 0x39000 },
2793 [GCC_USB3PHY_PHY_BCR] = { 0x39008 },
2794 [GCC_PCIE_0_BCR] = { 0x3e000 },
2795 [GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
2796 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
2797 [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
2798 [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6},
2799 [GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 },
2800 [GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 },
2801 [GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 },
2802 [GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 },
2803 [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
2804 [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
2805 [GCC_EMAC_BCR] = { 0x4e000 },
2806 [GCC_WDSP_RESTART] = {0x19000},
2813 .max_register = 0x7f000,