Lines Matching +full:0 +full:x4e000
53 { P_XO, 0 },
65 .offset = 0x21000,
68 .enable_reg = 0x45000,
69 .enable_mask = BIT(0),
81 .offset = 0x21000,
95 .l_reg = 0x20004,
96 .m_reg = 0x20008,
97 .n_reg = 0x2000c,
98 .config_reg = 0x20010,
99 .mode_reg = 0x20000,
100 .status_reg = 0x2001c,
111 .enable_reg = 0x45000,
124 .offset = 0x25000,
127 .enable_reg = 0x45000,
140 .offset = 0x25000,
154 .offset = 0x23000,
157 .enable_reg = 0x45000,
170 .offset = 0x23000,
184 { P_XO, 0 },
194 { P_XO, 0 },
206 F(19200000, P_XO, 1, 0, 0),
207 F(50000000, P_GPLL0, 16, 0, 0),
208 F(100000000, P_GPLL0, 8, 0, 0),
213 .cmd_rcgr = 0x46000,
226 .cmd_rcgr = 0x32004,
239 .cmd_rcgr = 0x31028,
252 F(19200000, P_XO, 1, 0, 0),
253 F(50000000, P_GPLL0, 16, 0, 0),
258 .cmd_rcgr = 0x0200c,
271 .cmd_rcgr = 0x03000,
284 .cmd_rcgr = 0x04000,
297 .cmd_rcgr = 0x05000,
310 .cmd_rcgr = 0x06000,
323 .cmd_rcgr = 0x07000,
337 F(4800000, P_XO, 4, 0, 0),
338 F(9600000, P_XO, 2, 0, 0),
340 F(19200000, P_XO, 1, 0, 0),
342 F(50000000, P_GPLL0, 16, 0, 0),
347 .cmd_rcgr = 0x02024,
361 .cmd_rcgr = 0x03014,
375 .cmd_rcgr = 0x04024,
389 .cmd_rcgr = 0x05024,
403 .cmd_rcgr = 0x06024,
417 .cmd_rcgr = 0x07024,
435 F(19200000, P_XO, 1, 0, 0),
450 .cmd_rcgr = 0x02044,
464 .cmd_rcgr = 0x03034,
478 { P_XO, 0 },
488 .cmd_rcgr = 0x4d044,
501 F(100000000, P_GPLL0, 8, 0, 0),
502 F(200000000, P_GPLL0, 4, 0, 0),
507 .cmd_rcgr = 0x54000,
521 .cmd_rcgr = 0x55000,
536 F(80000000, P_GPLL0, 10, 0, 0),
541 .cmd_rcgr = 0x5a000,
555 F(50000000, P_GPLL0, 16, 0, 0),
556 F(80000000, P_GPLL0, 10, 0, 0),
557 F(100000000, P_GPLL0, 8, 0, 0),
558 F(160000000, P_GPLL0, 5, 0, 0),
563 .cmd_rcgr = 0x16004,
576 F(100000000, P_GPLL0, 8, 0, 0),
577 F(200000000, P_GPLL0, 4, 0, 0),
582 .cmd_rcgr = 0x4e020,
595 .cmd_rcgr = 0x4f020,
608 F(100000000, P_GPLL0, 8, 0, 0),
609 F(200000000, P_GPLL0, 4, 0, 0),
614 .cmd_rcgr = 0x4e000,
627 F(19200000, P_XO, 1, 0, 0),
632 .cmd_rcgr = 0x4d05c,
645 { P_XO, 0 },
657 F(19200000, P_XO, 1, 0, 0),
658 F(50000000, P_GPLL0, 16, 0, 0),
659 F(80000000, P_GPLL0, 10, 0, 0),
660 F(100000000, P_GPLL0, 8, 0, 0),
661 F(160000000, P_GPLL0, 5, 0, 0),
662 F(177780000, P_GPLL0, 4.5, 0, 0),
663 F(200000000, P_GPLL0, 4, 0, 0),
664 F(266670000, P_GPLL0, 3, 0, 0),
665 F(307200000, P_GPLL1, 4, 0, 0),
666 F(409600000, P_GPLL1, 3, 0, 0),
671 .cmd_rcgr = 0x59000,
685 F(19200000, P_XO, 1, 0, 0),
690 .cmd_rcgr = 0x08004,
704 .cmd_rcgr = 0x09004,
718 .cmd_rcgr = 0x0a004,
732 { P_XO, 0 },
745 F(66667000, P_GPLL0, 12, 0, 0),
750 .cmd_rcgr = 0x52000,
764 .cmd_rcgr = 0x53000,
778 { P_XO, 0 },
790 F(50000000, P_GPLL0, 16, 0, 0),
791 F(80000000, P_GPLL0, 10, 0, 0),
792 F(100000000, P_GPLL0, 8, 0, 0),
793 F(160000000, P_GPLL0, 5, 0, 0),
794 F(177780000, P_GPLL0, 4.5, 0, 0),
795 F(200000000, P_GPLL0, 4, 0, 0),
796 F(266670000, P_GPLL0, 3, 0, 0),
797 F(307200000, P_GPLL1, 4, 0, 0),
802 .cmd_rcgr = 0x4d014,
815 { P_XO, 0 },
825 .cmd_rcgr = 0x4d000,
839 .cmd_rcgr = 0x27000,
851 F(64000000, P_GPLL0, 12.5, 0, 0),
856 .cmd_rcgr = 0x44010,
873 F(50000000, P_GPLL0, 16, 0, 0),
874 F(100000000, P_GPLL0, 8, 0, 0),
875 F(177770000, P_GPLL0, 4.5, 0, 0),
876 F(200000000, P_GPLL0, 4, 0, 0),
881 .cmd_rcgr = 0x42004,
895 .cmd_rcgr = 0x43004,
909 .cmd_rcgr = 0x26004,
921 F(57140000, P_GPLL0, 14, 0, 0),
922 F(80000000, P_GPLL0, 10, 0, 0),
923 F(100000000, P_GPLL0, 8, 0, 0),
928 .cmd_rcgr = 0x41010,
941 { P_XO, 0 },
953 F(133330000, P_GPLL0, 6, 0, 0),
954 F(266670000, P_GPLL0, 3, 0, 0),
955 F(307200000, P_GPLL1, 4, 0, 0),
960 .cmd_rcgr = 0x4c000,
974 F(50000000, P_GPLL0, 16, 0, 0),
975 F(80000000, P_GPLL0, 10, 0, 0),
976 F(100000000, P_GPLL0, 8, 0, 0),
977 F(133330000, P_GPLL0, 6, 0, 0),
978 F(160000000, P_GPLL0, 5, 0, 0),
979 F(177780000, P_GPLL0, 4.5, 0, 0),
980 F(200000000, P_GPLL0, 4, 0, 0),
981 F(266670000, P_GPLL0, 3, 0, 0),
982 F(320000000, P_GPLL0, 2.5, 0, 0),
987 .cmd_rcgr = 0x58000,
1000 F(19200000, P_XO, 1, 0, 0),
1005 .cmd_rcgr = 0x4d02c,
1018 .halt_reg = 0x12018,
1021 .enable_reg = 0x4500c,
1035 .halt_reg = 0x01008,
1038 .enable_reg = 0x45004,
1052 .halt_reg = 0x01004,
1055 .enable_reg = 0x45004,
1067 .halt_reg = 0x1300c,
1070 .enable_reg = 0x45004,
1084 .halt_reg = 0x1601c,
1087 .enable_reg = 0x45004,
1102 .halt_reg = 0x16024,
1105 .enable_reg = 0x45004,
1106 .enable_mask = BIT(0),
1119 .halt_reg = 0x16020,
1122 .enable_reg = 0x45004,
1136 .halt_reg = 0x12010,
1139 .enable_reg = 0x4500c,
1153 .halt_reg = 0x12020,
1156 .enable_reg = 0x4500c,
1170 .halt_reg = 0x12044,
1173 .enable_reg = 0x4500c,
1187 .halt_reg = 0x1201c,
1190 .enable_reg = 0x4500c,
1204 .halt_reg = 0x13004,
1207 .enable_reg = 0x45004,
1221 .halt_reg = 0x12038,
1224 .enable_reg = 0x4500c,
1238 .halt_reg = 0x12014,
1241 .enable_reg = 0x4500c,
1255 .halt_reg = 0x1203c,
1258 .enable_reg = 0x4500c,
1272 .halt_reg = 0x31024,
1275 .enable_reg = 0x31024,
1276 .enable_mask = BIT(0),
1289 .halt_reg = 0x31040,
1292 .enable_reg = 0x31040,
1293 .enable_mask = BIT(0),
1306 .halt_reg = 0x02008,
1309 .enable_reg = 0x02008,
1310 .enable_mask = BIT(0),
1324 .halt_reg = 0x03010,
1327 .enable_reg = 0x03010,
1328 .enable_mask = BIT(0),
1342 .halt_reg = 0x04020,
1345 .enable_reg = 0x04020,
1346 .enable_mask = BIT(0),
1360 .halt_reg = 0x05020,
1363 .enable_reg = 0x05020,
1364 .enable_mask = BIT(0),
1378 .halt_reg = 0x06020,
1381 .enable_reg = 0x06020,
1382 .enable_mask = BIT(0),
1396 .halt_reg = 0x07020,
1399 .enable_reg = 0x07020,
1400 .enable_mask = BIT(0),
1414 .halt_reg = 0x02004,
1417 .enable_reg = 0x02004,
1418 .enable_mask = BIT(0),
1432 .halt_reg = 0x0300c,
1435 .enable_reg = 0x0300c,
1436 .enable_mask = BIT(0),
1450 .halt_reg = 0x0401c,
1453 .enable_reg = 0x0401c,
1454 .enable_mask = BIT(0),
1468 .halt_reg = 0x0501c,
1471 .enable_reg = 0x0501c,
1472 .enable_mask = BIT(0),
1486 .halt_reg = 0x0601c,
1489 .enable_reg = 0x0601c,
1490 .enable_mask = BIT(0),
1504 .halt_reg = 0x0701c,
1507 .enable_reg = 0x0701c,
1508 .enable_mask = BIT(0),
1522 .halt_reg = 0x0203c,
1525 .enable_reg = 0x0203c,
1526 .enable_mask = BIT(0),
1540 .halt_reg = 0x0302c,
1543 .enable_reg = 0x0302c,
1544 .enable_mask = BIT(0),
1558 .halt_reg = 0x5a014,
1561 .enable_reg = 0x5a014,
1562 .enable_mask = BIT(0),
1575 .halt_reg = 0x4e03c,
1578 .enable_reg = 0x4e03c,
1579 .enable_mask = BIT(0),
1593 .halt_reg = 0x4e040,
1596 .enable_reg = 0x4e040,
1597 .enable_mask = BIT(0),
1611 .halt_reg = 0x4e048,
1614 .enable_reg = 0x4e048,
1615 .enable_mask = BIT(0),
1629 .halt_reg = 0x4e01c,
1632 .enable_reg = 0x4e01c,
1633 .enable_mask = BIT(0),
1647 .halt_reg = 0x4e058,
1650 .enable_reg = 0x4e058,
1651 .enable_mask = BIT(0),
1665 .halt_reg = 0x4e050,
1668 .enable_reg = 0x4e050,
1669 .enable_mask = BIT(0),
1683 .halt_reg = 0x4f03c,
1686 .enable_reg = 0x4f03c,
1687 .enable_mask = BIT(0),
1701 .halt_reg = 0x4f040,
1704 .enable_reg = 0x4f040,
1705 .enable_mask = BIT(0),
1719 .halt_reg = 0x4f048,
1722 .enable_reg = 0x4f048,
1723 .enable_mask = BIT(0),
1737 .halt_reg = 0x4f058,
1740 .enable_reg = 0x4f058,
1741 .enable_mask = BIT(0),
1755 .halt_reg = 0x4f050,
1758 .enable_reg = 0x4f050,
1759 .enable_mask = BIT(0),
1773 .halt_reg = 0x58050,
1776 .enable_reg = 0x58050,
1777 .enable_mask = BIT(0),
1791 .halt_reg = 0x54018,
1794 .enable_reg = 0x54018,
1795 .enable_mask = BIT(0),
1809 .halt_reg = 0x55018,
1812 .enable_reg = 0x55018,
1813 .enable_mask = BIT(0),
1827 .halt_reg = 0x50004,
1830 .enable_reg = 0x50004,
1831 .enable_mask = BIT(0),
1845 .halt_reg = 0x52018,
1848 .enable_reg = 0x52018,
1849 .enable_mask = BIT(0),
1863 .halt_reg = 0x53018,
1866 .enable_reg = 0x53018,
1867 .enable_mask = BIT(0),
1881 .halt_reg = 0x56004,
1884 .enable_reg = 0x56004,
1885 .enable_mask = BIT(0),
1899 .halt_reg = 0x58038,
1902 .enable_reg = 0x58038,
1903 .enable_mask = BIT(0),
1917 .halt_reg = 0x58044,
1920 .enable_reg = 0x58044,
1921 .enable_mask = BIT(0),
1935 .halt_reg = 0x58048,
1938 .enable_reg = 0x58048,
1939 .enable_mask = BIT(0),
1952 .halt_reg = 0x08000,
1955 .enable_reg = 0x08000,
1956 .enable_mask = BIT(0),
1970 .halt_reg = 0x09000,
1973 .enable_reg = 0x09000,
1974 .enable_mask = BIT(0),
1988 .halt_reg = 0x0a000,
1991 .enable_reg = 0x0a000,
1992 .enable_mask = BIT(0),
2006 .halt_reg = 0x4d07c,
2009 .enable_reg = 0x4d07c,
2010 .enable_mask = BIT(0),
2023 .halt_reg = 0x4d080,
2026 .enable_reg = 0x4d080,
2027 .enable_mask = BIT(0),
2040 .halt_reg = 0x4d094,
2043 .enable_reg = 0x4d094,
2044 .enable_mask = BIT(0),
2058 .halt_reg = 0x4d098,
2061 .enable_reg = 0x4d098,
2062 .enable_mask = BIT(0),
2076 .halt_reg = 0x4d088,
2079 .enable_reg = 0x4d088,
2080 .enable_mask = BIT(0),
2094 .halt_reg = 0x4d084,
2097 .enable_reg = 0x4d084,
2098 .enable_mask = BIT(0),
2112 .halt_reg = 0x4d090,
2115 .enable_reg = 0x4d090,
2116 .enable_mask = BIT(0),
2130 .halt_reg = 0x49000,
2133 .enable_reg = 0x49000,
2134 .enable_mask = BIT(0),
2147 .halt_reg = 0x49004,
2150 .enable_reg = 0x49004,
2151 .enable_mask = BIT(0),
2164 .halt_reg = 0x59028,
2167 .enable_reg = 0x59028,
2168 .enable_mask = BIT(0),
2181 .halt_reg = 0x59020,
2184 .enable_reg = 0x59020,
2185 .enable_mask = BIT(0),
2199 .halt_reg = 0x4400c,
2202 .enable_reg = 0x4400c,
2203 .enable_mask = BIT(0),
2217 .halt_reg = 0x44004,
2220 .enable_reg = 0x44004,
2221 .enable_mask = BIT(0),
2234 .halt_reg = 0x4201c,
2237 .enable_reg = 0x4201c,
2238 .enable_mask = BIT(0),
2251 .halt_reg = 0x42018,
2254 .enable_reg = 0x42018,
2255 .enable_mask = BIT(0),
2269 .halt_reg = 0x4301c,
2272 .enable_reg = 0x4301c,
2273 .enable_mask = BIT(0),
2286 .halt_reg = 0x43018,
2289 .enable_reg = 0x43018,
2290 .enable_mask = BIT(0),
2304 .halt_reg = 0x4102c,
2307 .enable_reg = 0x4102c,
2308 .enable_mask = BIT(0),
2319 .halt_reg = 0x41008,
2322 .enable_reg = 0x41008,
2323 .enable_mask = BIT(0),
2336 .halt_reg = 0x41030,
2339 .enable_reg = 0x41030,
2340 .enable_mask = BIT(0),
2353 .halt_reg = 0x41004,
2356 .enable_reg = 0x41004,
2357 .enable_mask = BIT(0),
2371 .halt_reg = 0x4c020,
2374 .enable_reg = 0x4c020,
2375 .enable_mask = BIT(0),
2388 .halt_reg = 0x4c024,
2391 .enable_reg = 0x4c024,
2392 .enable_mask = BIT(0),
2405 .halt_reg = 0x4c02c,
2408 .enable_reg = 0x4c02c,
2409 .enable_mask = BIT(0),
2423 .halt_reg = 0x4c01c,
2426 .enable_reg = 0x4c01c,
2427 .enable_mask = BIT(0),
2441 .gdscr = 0x4d078,
2442 .cxcs = (unsigned int []) { 0x4d080, 0x4d088 },
2451 .gdscr = 0x5901c,
2452 .cxcs = (unsigned int []) { 0x59020 },
2461 .gdscr = 0x4c018,
2462 .cxcs = (unsigned int []) { 0x4c024, 0x4c01c },
2471 .gdscr = 0x4c028,
2472 .cxcs = (unsigned int []) { 0x4c02c },
2482 .gdscr = 0x58034,
2483 .cxcs = (unsigned int []) { 0x58038, 0x58048, 0x58050 },
2635 [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
2636 [GCC_BLSP1_BCR] = { 0x01000 },
2637 [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
2638 [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
2639 [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
2640 [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
2641 [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
2642 [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
2643 [GCC_BLSP1_UART1_BCR] = { 0x02038 },
2644 [GCC_BLSP1_UART2_BCR] = { 0x03028 },
2645 [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
2646 [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
2647 [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
2648 [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
2649 [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
2650 [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
2651 [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
2652 [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
2653 [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
2654 [GCC_CAMSS_GP0_BCR] = { 0x54014 },
2655 [GCC_CAMSS_GP1_BCR] = { 0x55014 },
2656 [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
2657 [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
2658 [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
2659 [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
2660 [GCC_CAMSS_TOP_BCR] = { 0x56000 },
2661 [GCC_CAMSS_TOP_AHB_BCR] = { 0x5a018 },
2662 [GCC_CAMSS_VFE_BCR] = { 0x58030 },
2663 [GCC_CRYPTO_BCR] = { 0x16000 },
2664 [GCC_MDSS_BCR] = { 0x4d074 },
2665 [GCC_OXILI_BCR] = { 0x59018 },
2666 [GCC_PDM_BCR] = { 0x44000 },
2667 [GCC_PRNG_BCR] = { 0x13000 },
2668 [GCC_QUSB2_PHY_BCR] = { 0x4103c },
2669 [GCC_SDCC1_BCR] = { 0x42000 },
2670 [GCC_SDCC2_BCR] = { 0x43000 },
2671 [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
2672 [GCC_USB2A_PHY_BCR] = { 0x41028 },
2673 [GCC_USB2_HS_PHY_ONLY_BCR] = { .reg = 0x41034, .udelay = 15 },
2674 [GCC_USB_HS_BCR] = { 0x41000 },
2675 [GCC_VENUS0_BCR] = { 0x4c014 },
2677 [GCC_MSS_RESTART] = { 0x3e000 },
2684 .max_register = 0x80000,