Lines Matching +full:0 +full:x4e000
43 .offset = 0x0,
46 .enable_reg = 0x79000,
47 .enable_mask = BIT(0),
86 .offset = 0x3000,
89 .enable_reg = 0x79000,
103 .offset = 0x4000,
106 .enable_reg = 0x79000,
120 .offset = 0x5000,
123 .enable_reg = 0x79000,
137 .offset = 0x6000,
140 .enable_reg = 0x79000,
167 .offset = 0x7000,
170 .enable_reg = 0x79000,
197 .offset = 0x8000,
200 .enable_reg = 0x79000,
227 .offset = 0x9000,
230 .enable_reg = 0x79000,
257 { P_BI_TCXO, 0 },
269 { P_BI_TCXO, 0 },
283 { P_BI_TCXO, 0 },
297 { P_BI_TCXO, 0 },
311 { P_BI_TCXO, 0 },
323 { P_BI_TCXO, 0 },
333 { P_BI_TCXO, 0 },
345 { P_BI_TCXO, 0 },
357 { P_BI_TCXO, 0 },
377 { P_BI_TCXO, 0 },
389 { P_BI_TCXO, 0 },
407 { P_BI_TCXO, 0 },
421 { P_BI_TCXO, 0 },
435 { P_BI_TCXO, 0 },
451 { P_BI_TCXO, 0 },
461 F(19200000, P_BI_TCXO, 1, 0, 0),
462 F(40000000, P_GPLL8_OUT_MAIN, 12, 0, 0),
463 F(80000000, P_GPLL8_OUT_MAIN, 6, 0, 0),
468 .cmd_rcgr = 0x56088,
469 .mnd_width = 0,
482 F(37500000, P_GPLL0_OUT_EARLY, 16, 0, 0),
483 F(50000000, P_GPLL0_OUT_EARLY, 12, 0, 0),
484 F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
489 .cmd_rcgr = 0x52004,
503 F(120000000, P_GPLL8_OUT_MAIN, 4, 0, 0),
504 F(240000000, P_GPLL8_OUT_MAIN, 2, 0, 0),
505 F(320000000, P_GPLL8_OUT_MAIN, 1.5, 0, 0),
506 F(480000000, P_GPLL8_OUT_MAIN, 1, 0, 0),
507 F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0),
512 .cmd_rcgr = 0x560c8,
513 .mnd_width = 0,
526 F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
527 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
528 F(311000000, P_GPLL5_OUT_MAIN, 3, 0, 0),
529 F(403200000, P_GPLL4_OUT_MAIN, 2, 0, 0),
530 F(466500000, P_GPLL5_OUT_MAIN, 2, 0, 0),
535 .cmd_rcgr = 0x55030,
536 .mnd_width = 0,
549 F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
550 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
551 F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0),
556 .cmd_rcgr = 0x53004,
557 .mnd_width = 0,
570 .cmd_rcgr = 0x5506c,
571 .mnd_width = 0,
584 .cmd_rcgr = 0x53024,
585 .mnd_width = 0,
598 .cmd_rcgr = 0x550a4,
599 .mnd_width = 0,
612 .cmd_rcgr = 0x53044,
613 .mnd_width = 0,
626 .cmd_rcgr = 0x550e0,
627 .mnd_width = 0,
640 F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
641 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
642 F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0),
643 F(320000000, P_GPLL8_OUT_EARLY, 3, 0, 0),
648 .cmd_rcgr = 0x55000,
649 .mnd_width = 0,
662 F(50000000, P_GPLL0_OUT_EARLY, 12, 0, 0),
663 F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
664 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
669 .cmd_rcgr = 0x50000,
683 .cmd_rcgr = 0x5001c,
697 F(66666667, P_GPLL0_OUT_EARLY, 9, 0, 0),
698 F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0),
699 F(219428571, P_GPLL6_OUT_EARLY, 3.5, 0, 0),
700 F(320000000, P_GPLL8_OUT_EARLY, 3, 0, 0),
701 F(480000000, P_GPLL8_OUT_EARLY, 2, 0, 0),
706 .cmd_rcgr = 0x52028,
707 .mnd_width = 0,
720 F(19200000, P_BI_TCXO, 1, 0, 0),
727 .cmd_rcgr = 0x51000,
741 .cmd_rcgr = 0x5101c,
755 .cmd_rcgr = 0x51038,
769 .cmd_rcgr = 0x51054,
783 F(120000000, P_GPLL8_OUT_MAIN, 4, 0, 0),
784 F(256000000, P_GPLL6_OUT_EARLY, 3, 0, 0),
785 F(403200000, P_GPLL4_OUT_MAIN, 2, 0, 0),
786 F(480000000, P_GPLL8_OUT_MAIN, 1, 0, 0),
787 F(533000000, P_GPLL3_OUT_EARLY, 2, 0, 0),
788 F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0),
793 .cmd_rcgr = 0x54010,
794 .mnd_width = 0,
807 .cmd_rcgr = 0x54048,
808 .mnd_width = 0,
821 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
822 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
823 F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
824 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
829 .cmd_rcgr = 0x4d004,
843 .cmd_rcgr = 0x4e004,
857 .cmd_rcgr = 0x4f004,
871 F(19200000, P_BI_TCXO, 1, 0, 0),
872 F(60000000, P_GPLL0_OUT_EARLY, 10, 0, 0),
877 .cmd_rcgr = 0x20010,
878 .mnd_width = 0,
893 F(19200000, P_BI_TCXO, 1, 0, 0),
898 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
901 F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
905 F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0),
906 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
918 .cmd_rcgr = 0x1f148,
934 .cmd_rcgr = 0x1f278,
950 .cmd_rcgr = 0x1f3a8,
966 .cmd_rcgr = 0x1f4d8,
982 .cmd_rcgr = 0x1f608,
998 .cmd_rcgr = 0x1f738,
1014 .cmd_rcgr = 0x39148,
1030 .cmd_rcgr = 0x39278,
1046 .cmd_rcgr = 0x393a8,
1062 .cmd_rcgr = 0x394d8,
1078 .cmd_rcgr = 0x39608,
1094 .cmd_rcgr = 0x39738,
1107 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1108 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1109 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
1110 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
1115 .cmd_rcgr = 0x38028,
1129 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1130 F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0),
1131 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1132 F(300000000, P_GPLL0_OUT_EARLY, 2, 0, 0),
1137 .cmd_rcgr = 0x38010,
1138 .mnd_width = 0,
1152 F(19200000, P_BI_TCXO, 1, 0, 0),
1153 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1154 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1155 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1156 F(202000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
1161 .cmd_rcgr = 0x1e00c,
1175 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1176 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1177 F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
1178 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1179 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1184 .cmd_rcgr = 0x45020,
1198 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
1199 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1200 F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0),
1201 F(300000000, P_GPLL0_OUT_EARLY, 2, 0, 0),
1206 .cmd_rcgr = 0x45048,
1207 .mnd_width = 0,
1220 F(9600000, P_BI_TCXO, 2, 0, 0),
1221 F(19200000, P_BI_TCXO, 1, 0, 0),
1226 .cmd_rcgr = 0x4507c,
1227 .mnd_width = 0,
1240 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
1241 F(75000000, P_GPLL0_OUT_EARLY, 8, 0, 0),
1242 F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0),
1247 .cmd_rcgr = 0x45060,
1248 .mnd_width = 0,
1261 F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0),
1262 F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0),
1263 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1264 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1269 .cmd_rcgr = 0x1a01c,
1283 F(19200000, P_BI_TCXO, 1, 0, 0),
1284 F(20000000, P_GPLL0_OUT_AUX2, 15, 0, 0),
1285 F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0),
1286 F(60000000, P_GPLL0_OUT_EARLY, 10, 0, 0),
1291 .cmd_rcgr = 0x1a034,
1292 .mnd_width = 0,
1305 F(19200000, P_BI_TCXO, 1, 0, 0),
1310 .cmd_rcgr = 0x1a060,
1311 .mnd_width = 0,
1324 .cmd_rcgr = 0x42030,
1325 .mnd_width = 0,
1338 F(19200000, P_BI_TCXO, 1, 0, 0),
1339 F(400000000, P_GPLL0_OUT_EARLY, 1.5, 0, 0),
1340 F(600000000, P_GPLL0_OUT_EARLY, 1, 0, 0),
1345 .cmd_rcgr = 0x42018,
1346 .mnd_width = 0,
1359 .halt_reg = 0x1d004,
1361 .hwcg_reg = 0x1d004,
1364 .enable_reg = 0x1d004,
1365 .enable_mask = BIT(0),
1374 .halt_reg = 0x1d008,
1376 .hwcg_reg = 0x1d008,
1379 .enable_reg = 0x1d008,
1380 .enable_mask = BIT(0),
1389 .halt_reg = 0x4204c,
1392 .enable_reg = 0x4204c,
1393 .enable_mask = BIT(0),
1407 .halt_reg = 0x71154,
1410 .enable_reg = 0x71154,
1411 .enable_mask = BIT(0),
1420 .halt_reg = 0x23004,
1422 .hwcg_reg = 0x23004,
1425 .enable_reg = 0x79004,
1435 .halt_reg = 0x17008,
1437 .hwcg_reg = 0x17008,
1440 .enable_reg = 0x17008,
1441 .enable_mask = BIT(0),
1451 .halt_reg = 0x17028,
1454 .enable_reg = 0x17028,
1455 .enable_mask = BIT(0),
1465 .halt_reg = 0x52020,
1468 .enable_reg = 0x52020,
1469 .enable_mask = BIT(0),
1483 .halt_reg = 0x5201c,
1486 .enable_reg = 0x5201c,
1487 .enable_mask = BIT(0),
1501 .halt_reg = 0x5504c,
1504 .enable_reg = 0x5504c,
1505 .enable_mask = BIT(0),
1519 .halt_reg = 0x55088,
1522 .enable_reg = 0x55088,
1523 .enable_mask = BIT(0),
1537 .halt_reg = 0x550c0,
1540 .enable_reg = 0x550c0,
1541 .enable_mask = BIT(0),
1555 .halt_reg = 0x550fc,
1558 .enable_reg = 0x550fc,
1559 .enable_mask = BIT(0),
1573 .halt_reg = 0x560e8,
1576 .enable_reg = 0x560e8,
1577 .enable_mask = BIT(0),
1591 .halt_reg = 0x560f4,
1594 .enable_reg = 0x560f4,
1595 .enable_mask = BIT(0),
1604 .halt_reg = 0x560e0,
1607 .enable_reg = 0x560e0,
1608 .enable_mask = BIT(0),
1622 .halt_reg = 0x560f0,
1625 .enable_reg = 0x560f0,
1626 .enable_mask = BIT(0),
1640 .halt_reg = 0x55050,
1643 .enable_reg = 0x55050,
1644 .enable_mask = BIT(0),
1658 .halt_reg = 0x55048,
1661 .enable_reg = 0x55048,
1662 .enable_mask = BIT(0),
1676 .halt_reg = 0x5301c,
1679 .enable_reg = 0x5301c,
1680 .enable_mask = BIT(0),
1694 .halt_reg = 0x55060,
1697 .enable_reg = 0x55060,
1698 .enable_mask = BIT(0),
1712 .halt_reg = 0x55058,
1715 .enable_reg = 0x55058,
1716 .enable_mask = BIT(0),
1730 .halt_reg = 0x5508c,
1733 .enable_reg = 0x5508c,
1734 .enable_mask = BIT(0),
1748 .halt_reg = 0x55084,
1751 .enable_reg = 0x55084,
1752 .enable_mask = BIT(0),
1766 .halt_reg = 0x5303c,
1769 .enable_reg = 0x5303c,
1770 .enable_mask = BIT(0),
1784 .halt_reg = 0x5509c,
1787 .enable_reg = 0x5509c,
1788 .enable_mask = BIT(0),
1802 .halt_reg = 0x55094,
1805 .enable_reg = 0x55094,
1806 .enable_mask = BIT(0),
1820 .halt_reg = 0x550c4,
1823 .enable_reg = 0x550c4,
1824 .enable_mask = BIT(0),
1838 .halt_reg = 0x550bc,
1841 .enable_reg = 0x550bc,
1842 .enable_mask = BIT(0),
1856 .halt_reg = 0x5305c,
1859 .enable_reg = 0x5305c,
1860 .enable_mask = BIT(0),
1874 .halt_reg = 0x550d4,
1877 .enable_reg = 0x550d4,
1878 .enable_mask = BIT(0),
1892 .halt_reg = 0x550cc,
1895 .enable_reg = 0x550cc,
1896 .enable_mask = BIT(0),
1910 .halt_reg = 0x55100,
1913 .enable_reg = 0x55100,
1914 .enable_mask = BIT(0),
1928 .halt_reg = 0x550f8,
1931 .enable_reg = 0x550f8,
1932 .enable_mask = BIT(0),
1946 .halt_reg = 0x55110,
1949 .enable_reg = 0x55110,
1950 .enable_mask = BIT(0),
1964 .halt_reg = 0x55108,
1967 .enable_reg = 0x55108,
1968 .enable_mask = BIT(0),
1982 .halt_reg = 0x54074,
1985 .enable_reg = 0x54074,
1986 .enable_mask = BIT(0),
2000 .halt_reg = 0x54080,
2003 .enable_reg = 0x54080,
2004 .enable_mask = BIT(0),
2018 .halt_reg = 0x55018,
2021 .enable_reg = 0x55018,
2022 .enable_mask = BIT(0),
2036 .halt_reg = 0x5501c,
2039 .enable_reg = 0x5501c,
2040 .enable_mask = BIT(0),
2054 .halt_reg = 0x55020,
2057 .enable_reg = 0x55020,
2058 .enable_mask = BIT(0),
2072 .halt_reg = 0x50018,
2075 .enable_reg = 0x50018,
2076 .enable_mask = BIT(0),
2090 .halt_reg = 0x50034,
2093 .enable_reg = 0x50034,
2094 .enable_mask = BIT(0),
2108 .halt_reg = 0x540a4,
2111 .enable_reg = 0x540a4,
2112 .enable_mask = BIT(0),
2126 .halt_reg = 0x52048,
2129 .enable_reg = 0x52048,
2130 .enable_mask = BIT(0),
2144 .halt_reg = 0x5204c,
2147 .enable_reg = 0x5204c,
2148 .enable_mask = BIT(0),
2157 .halt_reg = 0x52040,
2160 .enable_reg = 0x52040,
2161 .enable_mask = BIT(0),
2175 .halt_reg = 0x51018,
2178 .enable_reg = 0x51018,
2179 .enable_mask = BIT(0),
2193 .halt_reg = 0x51034,
2196 .enable_reg = 0x51034,
2197 .enable_mask = BIT(0),
2211 .halt_reg = 0x51050,
2214 .enable_reg = 0x51050,
2215 .enable_mask = BIT(0),
2229 .halt_reg = 0x5106c,
2232 .enable_reg = 0x5106c,
2233 .enable_mask = BIT(0),
2247 .halt_reg = 0x560b0,
2250 .enable_reg = 0x560b0,
2251 .enable_mask = BIT(0),
2265 .halt_reg = 0x560a4,
2268 .enable_reg = 0x79004,
2278 .halt_reg = 0x560a8,
2281 .enable_reg = 0x79004,
2291 .halt_reg = 0x560a0,
2294 .enable_reg = 0x560a0,
2295 .enable_mask = BIT(0),
2309 .halt_reg = 0x54034,
2312 .enable_reg = 0x54034,
2313 .enable_mask = BIT(0),
2327 .halt_reg = 0x54028,
2330 .enable_reg = 0x54028,
2331 .enable_mask = BIT(0),
2345 .halt_reg = 0x54030,
2348 .enable_reg = 0x54030,
2349 .enable_mask = BIT(0),
2363 .halt_reg = 0x5406c,
2366 .enable_reg = 0x5406c,
2367 .enable_mask = BIT(0),
2381 .halt_reg = 0x54060,
2384 .enable_reg = 0x54060,
2385 .enable_mask = BIT(0),
2399 .halt_reg = 0x54068,
2402 .enable_reg = 0x54068,
2403 .enable_mask = BIT(0),
2417 .halt_reg = 0x5409c,
2420 .enable_reg = 0x5409c,
2421 .enable_mask = BIT(0),
2430 .halt_reg = 0x5408c,
2433 .enable_reg = 0x5408c,
2434 .enable_mask = BIT(0),
2448 .halt_reg = 0x54090,
2451 .enable_reg = 0x54090,
2452 .enable_mask = BIT(0),
2461 .halt_reg = 0x2700c,
2463 .hwcg_reg = 0x2700c,
2466 .enable_reg = 0x79004,
2476 .halt_reg = 0x27008,
2479 .enable_reg = 0x79004,
2489 .halt_reg = 0x27004,
2492 .enable_reg = 0x79004,
2502 .halt_reg = 0x1a084,
2505 .enable_reg = 0x1a084,
2506 .enable_mask = BIT(0),
2520 .halt_reg = 0x2b004,
2522 .hwcg_reg = 0x2b004,
2525 .enable_reg = 0x79004,
2536 .halt_reg = 0x1700c,
2538 .hwcg_reg = 0x1700c,
2541 .enable_reg = 0x1700c,
2542 .enable_mask = BIT(0),
2554 .enable_reg = 0x79004,
2568 .halt_reg = 0x17020,
2571 .enable_reg = 0x17020,
2572 .enable_mask = BIT(0),
2581 .halt_reg = 0x17064,
2584 .enable_reg = 0x7900c,
2594 .halt_reg = 0x1702c,
2597 .enable_reg = 0x1702c,
2598 .enable_mask = BIT(0),
2608 .halt_reg = 0x4d000,
2611 .enable_reg = 0x4d000,
2612 .enable_mask = BIT(0),
2626 .halt_reg = 0x4e000,
2629 .enable_reg = 0x4e000,
2630 .enable_mask = BIT(0),
2644 .halt_reg = 0x4f000,
2647 .enable_reg = 0x4f000,
2648 .enable_mask = BIT(0),
2662 .halt_reg = 0x36004,
2664 .hwcg_reg = 0x36004,
2667 .enable_reg = 0x36004,
2668 .enable_mask = BIT(0),
2680 .enable_reg = 0x79004,
2696 .enable_reg = 0x79004,
2710 .halt_reg = 0x3600c,
2713 .enable_reg = 0x3600c,
2714 .enable_mask = BIT(0),
2723 .halt_reg = 0x36018,
2726 .enable_reg = 0x36018,
2727 .enable_mask = BIT(0),
2736 .halt_reg = 0x36048,
2739 .enable_reg = 0x79004,
2749 .halt_reg = 0x36044,
2752 .enable_reg = 0x36044,
2753 .enable_mask = BIT(0),
2762 .halt_reg = 0x42048,
2765 .enable_reg = 0x42048,
2766 .enable_mask = BIT(0),
2780 .halt_reg = 0x2000c,
2783 .enable_reg = 0x2000c,
2784 .enable_mask = BIT(0),
2798 .halt_reg = 0x20004,
2800 .hwcg_reg = 0x20004,
2803 .enable_reg = 0x20004,
2804 .enable_mask = BIT(0),
2813 .halt_reg = 0x20008,
2816 .enable_reg = 0x20008,
2817 .enable_mask = BIT(0),
2826 .halt_reg = 0x21004,
2828 .hwcg_reg = 0x21004,
2831 .enable_reg = 0x79004,
2841 .halt_reg = 0x17014,
2843 .hwcg_reg = 0x17014,
2846 .enable_reg = 0x7900c,
2847 .enable_mask = BIT(0),
2856 .halt_reg = 0x17060,
2858 .hwcg_reg = 0x17060,
2861 .enable_reg = 0x7900c,
2871 .halt_reg = 0x17018,
2873 .hwcg_reg = 0x17018,
2876 .enable_reg = 0x7900c,
2886 .halt_reg = 0x36040,
2888 .hwcg_reg = 0x36040,
2891 .enable_reg = 0x7900c,
2901 .halt_reg = 0x17010,
2903 .hwcg_reg = 0x17010,
2906 .enable_reg = 0x79004,
2916 .halt_reg = 0x1f014,
2919 .enable_reg = 0x7900c,
2929 .halt_reg = 0x1f00c,
2932 .enable_reg = 0x7900c,
2942 .halt_reg = 0x1f144,
2945 .enable_reg = 0x7900c,
2960 .halt_reg = 0x1f274,
2963 .enable_reg = 0x7900c,
2978 .halt_reg = 0x1f3a4,
2981 .enable_reg = 0x7900c,
2996 .halt_reg = 0x1f4d4,
2999 .enable_reg = 0x7900c,
3014 .halt_reg = 0x1f604,
3017 .enable_reg = 0x7900c,
3032 .halt_reg = 0x1f734,
3035 .enable_reg = 0x7900c,
3050 .halt_reg = 0x39014,
3053 .enable_reg = 0x7900c,
3063 .halt_reg = 0x3900c,
3066 .enable_reg = 0x7900c,
3076 .halt_reg = 0x39144,
3079 .enable_reg = 0x7900c,
3094 .halt_reg = 0x39274,
3097 .enable_reg = 0x7900c,
3112 .halt_reg = 0x393a4,
3115 .enable_reg = 0x7900c,
3130 .halt_reg = 0x394d4,
3133 .enable_reg = 0x7900c,
3148 .halt_reg = 0x39604,
3151 .enable_reg = 0x7900c,
3166 .halt_reg = 0x39734,
3169 .enable_reg = 0x7900c,
3184 .halt_reg = 0x1f004,
3187 .enable_reg = 0x7900c,
3197 .halt_reg = 0x1f008,
3199 .hwcg_reg = 0x1f008,
3202 .enable_reg = 0x7900c,
3212 .halt_reg = 0x39004,
3215 .enable_reg = 0x7900c,
3225 .halt_reg = 0x39008,
3227 .hwcg_reg = 0x39008,
3230 .enable_reg = 0x7900c,
3240 .halt_reg = 0x38008,
3243 .enable_reg = 0x38008,
3244 .enable_mask = BIT(0),
3253 .halt_reg = 0x38004,
3256 .enable_reg = 0x38004,
3257 .enable_mask = BIT(0),
3271 .halt_reg = 0x3800c,
3274 .enable_reg = 0x3800c,
3275 .enable_mask = BIT(0),
3289 .halt_reg = 0x1e008,
3292 .enable_reg = 0x1e008,
3293 .enable_mask = BIT(0),
3302 .halt_reg = 0x1e004,
3305 .enable_reg = 0x1e004,
3306 .enable_mask = BIT(0),
3320 .halt_reg = 0x1050c,
3323 .enable_reg = 0x1050c,
3324 .enable_mask = BIT(0),
3334 .halt_reg = 0x2b06c,
3337 .enable_reg = 0x79004,
3338 .enable_mask = BIT(0),
3348 .halt_reg = 0x45098,
3351 .enable_reg = 0x45098,
3352 .enable_mask = BIT(0),
3366 .halt_reg = 0x1a080,
3369 .enable_reg = 0x1a080,
3370 .enable_mask = BIT(0),
3384 .halt_reg = 0x8c000,
3387 .enable_reg = 0x8c000,
3388 .enable_mask = BIT(0),
3397 .halt_reg = 0x45014,
3399 .hwcg_reg = 0x45014,
3402 .enable_reg = 0x45014,
3403 .enable_mask = BIT(0),
3412 .halt_reg = 0x45010,
3414 .hwcg_reg = 0x45010,
3417 .enable_reg = 0x45010,
3418 .enable_mask = BIT(0),
3432 .halt_reg = 0x45044,
3434 .hwcg_reg = 0x45044,
3437 .enable_reg = 0x45044,
3438 .enable_mask = BIT(0),
3452 .halt_reg = 0x45078,
3454 .hwcg_reg = 0x45078,
3457 .enable_reg = 0x45078,
3458 .enable_mask = BIT(0),
3472 .halt_reg = 0x4501c,
3475 .enable_reg = 0x4501c,
3476 .enable_mask = BIT(0),
3485 .halt_reg = 0x45018,
3488 .enable_reg = 0x45018,
3489 .enable_mask = BIT(0),
3498 .halt_reg = 0x45040,
3500 .hwcg_reg = 0x45040,
3503 .enable_reg = 0x45040,
3504 .enable_mask = BIT(0),
3518 .halt_reg = 0x1a010,
3521 .enable_reg = 0x1a010,
3522 .enable_mask = BIT(0),
3536 .halt_reg = 0x1a018,
3539 .enable_reg = 0x1a018,
3540 .enable_mask = BIT(0),
3554 .halt_reg = 0x1a014,
3557 .enable_reg = 0x1a014,
3558 .enable_mask = BIT(0),
3567 .halt_reg = 0x80278,
3570 .enable_reg = 0x80278,
3571 .enable_mask = BIT(0),
3580 .halt_reg = 0x1a054,
3583 .enable_reg = 0x1a054,
3584 .enable_mask = BIT(0),
3600 .enable_reg = 0x1a058,
3601 .enable_mask = BIT(0),
3610 .halt_reg = 0x4200c,
3613 .enable_reg = 0x4200c,
3614 .enable_mask = BIT(0),
3628 .halt_reg = 0x42004,
3631 .enable_reg = 0x42004,
3632 .enable_mask = BIT(0),
3646 .halt_reg = 0x42008,
3649 .enable_reg = 0x42008,
3650 .enable_mask = BIT(0),
3664 .halt_reg = 0x17004,
3666 .hwcg_reg = 0x17004,
3669 .enable_reg = 0x17004,
3670 .enable_mask = BIT(0),
3680 .halt_reg = 0x1701c,
3683 .enable_reg = 0x1701c,
3684 .enable_mask = BIT(0),
3693 .halt_reg = 0x17068,
3696 .enable_reg = 0x79004,
3706 .halt_reg = 0x17024,
3709 .enable_reg = 0x17024,
3710 .enable_mask = BIT(0),
3720 .halt_reg = 0x42014,
3722 .hwcg_reg = 0x42014,
3725 .enable_reg = 0x42014,
3726 .enable_mask = BIT(0),
3735 .halt_reg = 0x42010,
3738 .enable_reg = 0x42010,
3739 .enable_mask = BIT(0),
3753 .halt_reg = 0x42050,
3756 .enable_reg = 0x42050,
3757 .enable_mask = BIT(0),
3771 .gdscr = 0x1a004,
3779 .gdscr = 0x45004,
3787 .gdscr = 0x54004,
3795 .gdscr = 0x5403c,
3803 .gdscr = 0x5607c,
3811 .gdscr = 0x560bc,
3819 .gdscr = 0x7d060,
3828 .gdscr = 0x80074,
3837 .gdscr = 0x80084,
3847 .gdscr = 0x80094,
4086 [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
4087 [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 },
4088 [GCC_UFS_PHY_BCR] = { 0x45000 },
4089 [GCC_USB30_PRIM_BCR] = { 0x1a000 },
4090 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
4091 [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 },
4092 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
4093 [GCC_CAMSS_MICRO_BCR] = { 0x560ac },
4115 .max_register = 0xc7000,
4150 regmap_update_bits(regmap, 0x80258, 0x1, 0x1); in gcc_sm6125_probe()
4156 regmap_update_bits(regmap, 0x51004, 0x3000, 0x2000); in gcc_sm6125_probe()
4157 regmap_update_bits(regmap, 0x51020, 0x3000, 0x2000); in gcc_sm6125_probe()
4158 regmap_update_bits(regmap, 0x5103c, 0x3000, 0x2000); in gcc_sm6125_probe()
4159 regmap_update_bits(regmap, 0x51058, 0x3000, 0x2000); in gcc_sm6125_probe()