Lines Matching +full:0 +full:x4e000
41 .offset = 0x21000,
44 .enable_reg = 0x45000,
45 .enable_mask = BIT(0),
71 .offset = 0x21000,
84 .offset = 0x4a000,
87 .enable_reg = 0x45000,
101 .offset = 0x4a000,
114 { 1000000000, 2000000000, 0 },
119 .config_ctl_val = 0x4001055b,
120 .early_output_mask = 0,
126 .offset = 0x22000,
144 .offset = 0x22000,
158 .offset = 0x24000,
161 .enable_reg = 0x45000,
175 .offset = 0x24000,
188 .offset = 0x37000,
191 .enable_reg = 0x45000,
218 .offset = 0x37000,
231 { P_XO, 0 },
237 { P_XO, 0 },
249 { P_XO, 0 },
261 F(19200000, P_XO, 1, 0, 0),
262 F(400000000, P_GPLL0, 2, 0, 0),
263 F(576000000, P_GPLL4, 2, 0, 0),
268 .cmd_rcgr = 0x78008,
280 .cmd_rcgr = 0x79008,
293 F(19200000, P_XO, 1, 0, 0),
294 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
295 F(50000000, P_GPLL0, 16, 0, 0),
296 F(100000000, P_GPLL0, 8, 0, 0),
297 F(133330000, P_GPLL0, 6, 0, 0),
302 .cmd_rcgr = 0x46000,
315 F(19200000, P_XO, 1, 0, 0),
316 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
317 F(50000000, P_GPLL0, 16, 0, 0),
322 .cmd_rcgr = 0x0200c,
335 .cmd_rcgr = 0x03000,
348 .cmd_rcgr = 0x04000,
361 .cmd_rcgr = 0x05000,
374 .cmd_rcgr = 0x0c00c,
387 .cmd_rcgr = 0x0d000,
400 .cmd_rcgr = 0x0f000,
413 .cmd_rcgr = 0x18000,
427 F(4800000, P_XO, 4, 0, 0),
428 F(9600000, P_XO, 2, 0, 0),
431 F(19200000, P_XO, 1, 0, 0),
433 F(50000000, P_GPLL0, 16, 0, 0),
438 .cmd_rcgr = 0x02024,
452 .cmd_rcgr = 0x03014,
466 .cmd_rcgr = 0x04024,
480 .cmd_rcgr = 0x05024,
494 .cmd_rcgr = 0x0c024,
508 .cmd_rcgr = 0x0d014,
522 .cmd_rcgr = 0x0f024,
536 .cmd_rcgr = 0x18024,
554 F(19200000, P_XO, 1, 0, 0),
570 .cmd_rcgr = 0x02044,
584 .cmd_rcgr = 0x03034,
598 .cmd_rcgr = 0x0c044,
612 .cmd_rcgr = 0x0d034,
626 { P_XO, 0 },
632 { P_XO, 0 },
644 .cmd_rcgr = 0x4d044,
657 .cmd_rcgr = 0x4d0b0,
670 { P_XO, 0 },
686 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
687 F(100000000, P_GPLL0, 8, 0, 0),
688 F(200000000, P_GPLL0, 4, 0, 0),
689 F(266670000, P_GPLL0, 3, 0, 0),
694 .cmd_rcgr = 0x54000,
708 .cmd_rcgr = 0x55000,
722 F(40000000, P_GPLL0_DIV2, 10, 0, 0),
723 F(80000000, P_GPLL0, 10, 0, 0),
728 .cmd_rcgr = 0x5a000,
741 { P_XO, 0 },
755 F(19200000, P_XO, 1, 0, 0),
761 .cmd_rcgr = 0x51000,
775 { P_XO, 0 },
791 F(100000000, P_GPLL0_DIV2, 4, 0, 0),
792 F(200000000, P_GPLL0, 4, 0, 0),
793 F(266670000, P_GPLL0, 3, 0, 0),
794 F(320000000, P_GPLL0, 2.5, 0, 0),
795 F(400000000, P_GPLL0, 2, 0, 0),
796 F(465000000, P_GPLL2, 2, 0, 0),
801 .cmd_rcgr = 0x58018,
814 F(40000000, P_GPLL0_DIV2, 10, 0, 0),
815 F(80000000, P_GPLL0, 10, 0, 0),
816 F(100000000, P_GPLL0, 8, 0, 0),
817 F(160000000, P_GPLL0, 5, 0, 0),
822 .cmd_rcgr = 0x16004,
835 { P_XO, 0 },
842 { P_XO, 0 },
856 F(100000000, P_GPLL0_DIV2, 4, 0, 0),
857 F(200000000, P_GPLL0, 4, 0, 0),
858 F(310000000, P_GPLL2, 3, 0, 0),
859 F(400000000, P_GPLL0, 2, 0, 0),
860 F(465000000, P_GPLL2, 2, 0, 0),
865 .cmd_rcgr = 0x4e020,
878 .cmd_rcgr = 0x4f020,
891 .cmd_rcgr = 0x3c020,
904 { P_XO, 0 },
920 F(66670000, P_GPLL0_DIV2, 6, 0, 0),
921 F(133330000, P_GPLL0, 6, 0, 0),
922 F(200000000, P_GPLL0, 4, 0, 0),
923 F(266670000, P_GPLL0, 3, 0, 0),
924 F(310000000, P_GPLL2, 3, 0, 0),
929 .cmd_rcgr = 0x58084,
942 .cmd_rcgr = 0x58094,
955 .cmd_rcgr = 0x580a4,
968 F(100000000, P_GPLL0_DIV2, 4, 0, 0),
969 F(200000000, P_GPLL0, 4, 0, 0),
970 F(266670000, P_GPLL0, 3, 0, 0),
975 .cmd_rcgr = 0x4e000,
988 .cmd_rcgr = 0x4f000,
1001 .cmd_rcgr = 0x4f05c,
1014 { P_XO, 0 },
1024 F(19200000, P_XO, 1, 0, 0),
1029 .cmd_rcgr = 0x4d05c,
1042 .cmd_rcgr = 0x4d0a8,
1055 { P_XO, 0 },
1075 F(19200000, P_XO, 1, 0, 0),
1076 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1077 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1078 F(100000000, P_GPLL0_DIV2, 4, 0, 0),
1079 F(133330000, P_GPLL0_DIV2, 3, 0, 0),
1080 F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
1081 F(200000000, P_GPLL0_DIV2, 2, 0, 0),
1082 F(266670000, P_GPLL0, 3.0, 0, 0),
1083 F(320000000, P_GPLL0, 2.5, 0, 0),
1084 F(400000000, P_GPLL0, 2, 0, 0),
1085 F(460800000, P_GPLL4, 2.5, 0, 0),
1086 F(510000000, P_GPLL3, 2, 0, 0),
1087 F(560000000, P_GPLL3, 2, 0, 0),
1088 F(600000000, P_GPLL3, 2, 0, 0),
1089 F(650000000, P_GPLL3, 2, 0, 0),
1090 F(685000000, P_GPLL3, 2, 0, 0),
1091 F(725000000, P_GPLL3, 2, 0, 0),
1096 .cmd_rcgr = 0x59000,
1110 F(19200000, P_XO, 1, 0, 0),
1115 .cmd_rcgr = 0x08004,
1129 .cmd_rcgr = 0x09004,
1143 .cmd_rcgr = 0x0a004,
1157 { P_XO, 0 },
1173 F(66670000, P_GPLL0_DIV2, 6, 0, 0),
1174 F(133330000, P_GPLL0, 6, 0, 0),
1175 F(200000000, P_GPLL0, 4, 0, 0),
1176 F(266670000, P_GPLL0, 3, 0, 0),
1177 F(310000000, P_GPLL2, 3, 0, 0),
1178 F(320000000, P_GPLL0, 2.5, 0, 0),
1183 .cmd_rcgr = 0x57000,
1196 { P_XO, 0 },
1217 F(33330000, P_GPLL0_DIV2, 12, 0, 0),
1219 F(66667000, P_GPLL0, 12, 0, 0),
1224 .cmd_rcgr = 0x52000,
1238 .cmd_rcgr = 0x53000,
1252 .cmd_rcgr = 0x5c000,
1266 .cmd_rcgr = 0x5e000,
1280 { P_XO, 0 },
1294 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1295 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1296 F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
1297 F(200000000, P_GPLL0, 4, 0, 0),
1298 F(266670000, P_GPLL0, 3, 0, 0),
1299 F(320000000, P_GPLL0, 2.5, 0, 0),
1300 F(400000000, P_GPLL0, 2, 0, 0),
1305 .cmd_rcgr = 0x4d014,
1318 { P_XO, 0 },
1324 { P_XO, 0 },
1336 .cmd_rcgr = 0x4d000,
1350 .cmd_rcgr = 0x4d0b8,
1364 F(32000000, P_GPLL0_DIV2, 12.5, 0, 0),
1365 F(64000000, P_GPLL0, 12.5, 0, 0),
1370 .cmd_rcgr = 0x44010,
1383 F(19200000, P_XO, 1, 0, 0),
1384 F(50000000, P_GPLL0, 16, 0, 0),
1389 .cmd_rcgr = 0x3a00c,
1402 { P_XO, 0 },
1416 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1417 F(160000000, P_GPLL0, 5, 0, 0),
1418 F(270000000, P_GPLL6, 4, 0, 0),
1423 .cmd_rcgr = 0x5d000,
1436 { P_XO, 0 },
1453 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1454 F(50000000, P_GPLL0, 16, 0, 0),
1455 F(100000000, P_GPLL0, 8, 0, 0),
1456 F(177770000, P_GPLL0, 4.5, 0, 0),
1457 F(192000000, P_GPLL4, 6, 0, 0),
1458 F(384000000, P_GPLL4, 3, 0, 0),
1463 .cmd_rcgr = 0x42004,
1480 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1481 F(50000000, P_GPLL0, 16, 0, 0),
1482 F(100000000, P_GPLL0, 8, 0, 0),
1483 F(177770000, P_GPLL0, 4.5, 0, 0),
1484 F(192000000, P_GPLL4, 6, 0, 0),
1485 F(200000000, P_GPLL0, 4, 0, 0),
1490 .cmd_rcgr = 0x43004,
1504 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1505 F(100000000, P_GPLL0, 8, 0, 0),
1506 F(133330000, P_GPLL0, 6, 0, 0),
1511 .cmd_rcgr = 0x3f00c,
1524 { P_XO, 0 },
1540 F(19200000, P_XO, 1, 0, 0),
1546 .cmd_rcgr = 0x3f020,
1560 { P_XO, 0 },
1570 F(19200000, P_XO, 1, 0, 0),
1575 .cmd_rcgr = 0x3f05c,
1589 { P_XO, 0 },
1605 F(114290000, P_GPLL0_DIV2, 3.5, 0, 0),
1606 F(228570000, P_GPLL0, 3.5, 0, 0),
1607 F(310000000, P_GPLL2, 3, 0, 0),
1608 F(360000000, P_GPLL6, 3, 0, 0),
1609 F(400000000, P_GPLL0, 2, 0, 0),
1610 F(465000000, P_GPLL2, 2, 0, 0),
1611 F(540000000, P_GPLL6, 2, 0, 0),
1616 .cmd_rcgr = 0x4c000,
1629 { P_XO, 0 },
1647 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1648 F(100000000, P_GPLL0_DIV2, 4, 0, 0),
1649 F(133330000, P_GPLL0, 6, 0, 0),
1650 F(160000000, P_GPLL0, 5, 0, 0),
1651 F(200000000, P_GPLL0, 4, 0, 0),
1652 F(266670000, P_GPLL0, 3, 0, 0),
1653 F(310000000, P_GPLL2, 3, 0, 0),
1654 F(400000000, P_GPLL0, 2, 0, 0),
1655 F(465000000, P_GPLL2, 2, 0, 0),
1660 .cmd_rcgr = 0x58000,
1673 .cmd_rcgr = 0x58054,
1686 { P_XO, 0 },
1691 F(19200000, P_XO, 1, 0, 0),
1696 .cmd_rcgr = 0x4d02c,
1709 .halt_reg = 0x78004,
1712 .enable_reg = 0x78004,
1713 .enable_mask = BIT(0),
1727 .halt_reg = 0x79004,
1730 .enable_reg = 0x79004,
1731 .enable_mask = BIT(0),
1745 .halt_reg = 0x4601c,
1748 .enable_reg = 0x45004,
1763 .halt_reg = 0x46020,
1766 .enable_reg = 0x45004,
1776 .halt_reg = 0x12018,
1779 .enable_reg = 0x4500c,
1789 .halt_reg = 0x59034,
1792 .enable_reg = 0x59034,
1793 .enable_mask = BIT(0),
1802 .halt_reg = 0x59030,
1805 .enable_reg = 0x59030,
1806 .enable_mask = BIT(0),
1815 .halt_reg = 0x01008,
1818 .enable_reg = 0x45004,
1828 .halt_reg = 0x0b008,
1831 .enable_reg = 0x45004,
1841 .halt_reg = 0x02008,
1844 .enable_reg = 0x02008,
1845 .enable_mask = BIT(0),
1859 .halt_reg = 0x03010,
1862 .enable_reg = 0x03010,
1863 .enable_mask = BIT(0),
1877 .halt_reg = 0x04020,
1880 .enable_reg = 0x04020,
1881 .enable_mask = BIT(0),
1895 .halt_reg = 0x05020,
1898 .enable_reg = 0x05020,
1899 .enable_mask = BIT(0),
1913 .halt_reg = 0x0c008,
1916 .enable_reg = 0x0c008,
1917 .enable_mask = BIT(0),
1931 .halt_reg = 0x0d010,
1934 .enable_reg = 0x0d010,
1935 .enable_mask = BIT(0),
1949 .halt_reg = 0x0f020,
1952 .enable_reg = 0x0f020,
1953 .enable_mask = BIT(0),
1967 .halt_reg = 0x18020,
1970 .enable_reg = 0x18020,
1971 .enable_mask = BIT(0),
1985 .halt_reg = 0x02004,
1988 .enable_reg = 0x02004,
1989 .enable_mask = BIT(0),
2003 .halt_reg = 0x0300c,
2006 .enable_reg = 0x0300c,
2007 .enable_mask = BIT(0),
2021 .halt_reg = 0x0401c,
2024 .enable_reg = 0x0401c,
2025 .enable_mask = BIT(0),
2039 .halt_reg = 0x0501c,
2042 .enable_reg = 0x0501c,
2043 .enable_mask = BIT(0),
2057 .halt_reg = 0x0c004,
2060 .enable_reg = 0x0c004,
2061 .enable_mask = BIT(0),
2075 .halt_reg = 0x0d00c,
2078 .enable_reg = 0x0d00c,
2079 .enable_mask = BIT(0),
2093 .halt_reg = 0x0f01c,
2096 .enable_reg = 0x0f01c,
2097 .enable_mask = BIT(0),
2111 .halt_reg = 0x1801c,
2114 .enable_reg = 0x1801c,
2115 .enable_mask = BIT(0),
2129 .halt_reg = 0x0203c,
2132 .enable_reg = 0x0203c,
2133 .enable_mask = BIT(0),
2147 .halt_reg = 0x0302c,
2150 .enable_reg = 0x0302c,
2151 .enable_mask = BIT(0),
2165 .halt_reg = 0x0c03c,
2168 .enable_reg = 0x0c03c,
2169 .enable_mask = BIT(0),
2183 .halt_reg = 0x0d02c,
2186 .enable_reg = 0x0d02c,
2187 .enable_mask = BIT(0),
2201 .halt_reg = 0x1300c,
2204 .enable_reg = 0x45004,
2214 .halt_reg = 0x56004,
2217 .enable_reg = 0x56004,
2218 .enable_mask = BIT(0),
2227 .halt_reg = 0x5101c,
2230 .enable_reg = 0x5101c,
2231 .enable_mask = BIT(0),
2245 .halt_reg = 0x51018,
2248 .enable_reg = 0x51018,
2249 .enable_mask = BIT(0),
2263 .halt_reg = 0x58040,
2266 .enable_reg = 0x58040,
2267 .enable_mask = BIT(0),
2281 .halt_reg = 0x58064,
2284 .enable_reg = 0x58064,
2285 .enable_mask = BIT(0),
2294 .halt_reg = 0x5803c,
2297 .enable_reg = 0x5803c,
2298 .enable_mask = BIT(0),
2312 .halt_reg = 0x4e040,
2315 .enable_reg = 0x4e040,
2316 .enable_mask = BIT(0),
2330 .halt_reg = 0x4f040,
2333 .enable_reg = 0x4f040,
2334 .enable_mask = BIT(0),
2348 .halt_reg = 0x3c040,
2351 .enable_reg = 0x3c040,
2352 .enable_mask = BIT(0),
2366 .halt_reg = 0x4e03c,
2369 .enable_reg = 0x4e03c,
2370 .enable_mask = BIT(0),
2384 .halt_reg = 0x4f03c,
2387 .enable_reg = 0x4f03c,
2388 .enable_mask = BIT(0),
2402 .halt_reg = 0x3c03c,
2405 .enable_reg = 0x3c03c,
2406 .enable_mask = BIT(0),
2420 .halt_reg = 0x58090,
2423 .enable_reg = 0x58090,
2424 .enable_mask = BIT(0),
2438 .halt_reg = 0x580a0,
2441 .enable_reg = 0x580a0,
2442 .enable_mask = BIT(0),
2456 .halt_reg = 0x580b0,
2459 .enable_reg = 0x580b0,
2460 .enable_mask = BIT(0),
2474 .halt_reg = 0x4e048,
2477 .enable_reg = 0x4e048,
2478 .enable_mask = BIT(0),
2492 .halt_reg = 0x4f048,
2495 .enable_reg = 0x4f048,
2496 .enable_mask = BIT(0),
2510 .halt_reg = 0x3c048,
2513 .enable_reg = 0x3c048,
2514 .enable_mask = BIT(0),
2528 .halt_reg = 0x4e01c,
2531 .enable_reg = 0x4e01c,
2532 .enable_mask = BIT(0),
2546 .halt_reg = 0x4f01c,
2549 .enable_reg = 0x4f01c,
2550 .enable_mask = BIT(0),
2564 .halt_reg = 0x4f068,
2567 .enable_reg = 0x4f068,
2568 .enable_mask = BIT(0),
2582 .halt_reg = 0x4e058,
2585 .enable_reg = 0x4e058,
2586 .enable_mask = BIT(0),
2600 .halt_reg = 0x4f058,
2603 .enable_reg = 0x4f058,
2604 .enable_mask = BIT(0),
2618 .halt_reg = 0x3c058,
2621 .enable_reg = 0x3c058,
2622 .enable_mask = BIT(0),
2636 .halt_reg = 0x4e050,
2639 .enable_reg = 0x4e050,
2640 .enable_mask = BIT(0),
2654 .halt_reg = 0x4f050,
2657 .enable_reg = 0x4f050,
2658 .enable_mask = BIT(0),
2672 .halt_reg = 0x3c050,
2675 .enable_reg = 0x3c050,
2676 .enable_mask = BIT(0),
2690 .halt_reg = 0x58050,
2693 .enable_reg = 0x58050,
2694 .enable_mask = BIT(0),
2708 .halt_reg = 0x58074,
2711 .enable_reg = 0x58074,
2712 .enable_mask = BIT(0),
2726 .halt_reg = 0x54018,
2729 .enable_reg = 0x54018,
2730 .enable_mask = BIT(0),
2744 .halt_reg = 0x55018,
2747 .enable_reg = 0x55018,
2748 .enable_mask = BIT(0),
2762 .halt_reg = 0x50004,
2765 .enable_reg = 0x50004,
2766 .enable_mask = BIT(0),
2780 .halt_reg = 0x57020,
2783 .enable_reg = 0x57020,
2784 .enable_mask = BIT(0),
2798 .halt_reg = 0x57024,
2801 .enable_reg = 0x57024,
2802 .enable_mask = BIT(0),
2816 .halt_reg = 0x57028,
2819 .enable_reg = 0x57028,
2820 .enable_mask = BIT(0),
2829 .halt_reg = 0x52018,
2832 .enable_reg = 0x52018,
2833 .enable_mask = BIT(0),
2847 .halt_reg = 0x53018,
2850 .enable_reg = 0x53018,
2851 .enable_mask = BIT(0),
2865 .halt_reg = 0x5c018,
2868 .enable_reg = 0x5c018,
2869 .enable_mask = BIT(0),
2883 .halt_reg = 0x5e018,
2886 .enable_reg = 0x5e018,
2887 .enable_mask = BIT(0),
2901 .halt_reg = 0x5600c,
2904 .enable_reg = 0x5600c,
2905 .enable_mask = BIT(0),
2919 .halt_reg = 0x5a014,
2922 .enable_reg = 0x5a014,
2923 .enable_mask = BIT(0),
2937 .halt_reg = 0x58044,
2940 .enable_reg = 0x58044,
2941 .enable_mask = BIT(0),
2955 .halt_reg = 0x58048,
2958 .enable_reg = 0x58048,
2959 .enable_mask = BIT(0),
2968 .halt_reg = 0x58038,
2971 .enable_reg = 0x58038,
2972 .enable_mask = BIT(0),
2986 .halt_reg = 0x58060,
2989 .enable_reg = 0x58060,
2990 .enable_mask = BIT(0),
3004 .halt_reg = 0x58068,
3007 .enable_reg = 0x58068,
3008 .enable_mask = BIT(0),
3017 .halt_reg = 0x5805c,
3020 .enable_reg = 0x5805c,
3021 .enable_mask = BIT(0),
3035 .halt_reg = 0x12040,
3038 .enable_reg = 0x4500c,
3048 .halt_reg = 0x16024,
3051 .enable_reg = 0x45004,
3052 .enable_mask = BIT(0),
3061 .halt_reg = 0x16020,
3064 .enable_reg = 0x45004,
3074 .halt_reg = 0x1601c,
3077 .enable_reg = 0x45004,
3092 .halt_reg = 0x77004,
3095 .enable_reg = 0x77004,
3096 .enable_mask = BIT(0),
3105 .halt_reg = 0x08000,
3108 .enable_reg = 0x08000,
3109 .enable_mask = BIT(0),
3123 .halt_reg = 0x09000,
3126 .enable_reg = 0x09000,
3127 .enable_mask = BIT(0),
3141 .halt_reg = 0x0a000,
3144 .enable_reg = 0x0a000,
3145 .enable_mask = BIT(0),
3159 .halt_reg = 0x12034,
3162 .enable_reg = 0x4500c,
3172 .halt_reg = 0x1201c,
3175 .enable_reg = 0x4500c,
3185 .halt_reg = 0x4d07c,
3188 .enable_reg = 0x4d07c,
3189 .enable_mask = BIT(0),
3198 .halt_reg = 0x4d080,
3201 .enable_reg = 0x4d080,
3202 .enable_mask = BIT(0),
3211 .halt_reg = 0x4d094,
3214 .enable_reg = 0x4d094,
3215 .enable_mask = BIT(0),
3229 .halt_reg = 0x4d0a0,
3232 .enable_reg = 0x4d0a0,
3233 .enable_mask = BIT(0),
3247 .halt_reg = 0x4d098,
3250 .enable_reg = 0x4d098,
3251 .enable_mask = BIT(0),
3265 .halt_reg = 0x4d09c,
3268 .enable_reg = 0x4d09c,
3269 .enable_mask = BIT(0),
3283 .halt_reg = 0x4d088,
3286 .enable_reg = 0x4d088,
3287 .enable_mask = BIT(0),
3301 .halt_reg = 0x4d084,
3304 .enable_reg = 0x4d084,
3305 .enable_mask = BIT(0),
3319 .halt_reg = 0x4d0a4,
3322 .enable_reg = 0x4d0a4,
3323 .enable_mask = BIT(0),
3337 .halt_reg = 0x4d090,
3340 .enable_reg = 0x4d090,
3341 .enable_mask = BIT(0),
3355 .halt_reg = 0x49000,
3358 .enable_reg = 0x49000,
3359 .enable_mask = BIT(0),
3368 .halt_reg = 0x49004,
3371 .enable_reg = 0x49004,
3372 .enable_mask = BIT(0),
3381 .halt_reg = 0x59028,
3384 .enable_reg = 0x59028,
3385 .enable_mask = BIT(0),
3394 .halt_reg = 0x59044,
3397 .enable_reg = 0x59044,
3398 .enable_mask = BIT(0),
3411 .halt_reg = 0x59020,
3414 .enable_reg = 0x59020,
3415 .enable_mask = BIT(0),
3429 .halt_reg = 0x59040,
3432 .enable_reg = 0x59040,
3433 .enable_mask = BIT(0),
3442 .halt_reg = 0x3f038,
3445 .enable_reg = 0x3f038,
3446 .enable_mask = BIT(0),
3460 .halt_reg = 0x4400c,
3463 .enable_reg = 0x4400c,
3464 .enable_mask = BIT(0),
3478 .halt_reg = 0x44004,
3481 .enable_reg = 0x44004,
3482 .enable_mask = BIT(0),
3491 .halt_reg = 0x13004,
3494 .enable_reg = 0x45004,
3504 .halt_reg = 0x29084,
3507 .enable_reg = 0x45004,
3517 .halt_reg = 0,
3520 .enable_reg = 0x41030,
3521 .enable_mask = BIT(0),
3530 .halt_reg = 0x3a004,
3533 .enable_reg = 0x3a004,
3534 .enable_mask = BIT(0),
3548 .halt_reg = 0x5d014,
3551 .enable_reg = 0x5d014,
3552 .enable_mask = BIT(0),
3566 .halt_reg = 0x4201c,
3569 .enable_reg = 0x4201c,
3570 .enable_mask = BIT(0),
3579 .halt_reg = 0x4301c,
3582 .enable_reg = 0x4301c,
3583 .enable_mask = BIT(0),
3592 .halt_reg = 0x42018,
3595 .enable_reg = 0x42018,
3596 .enable_mask = BIT(0),
3610 .halt_reg = 0x43018,
3613 .enable_reg = 0x43018,
3614 .enable_mask = BIT(0),
3628 .halt_reg = 0x12038,
3631 .enable_reg = 0x4500c,
3641 .halt_reg = 0x3f000,
3644 .enable_reg = 0x3f000,
3645 .enable_mask = BIT(0),
3659 .halt_reg = 0x3f008,
3662 .enable_reg = 0x3f008,
3663 .enable_mask = BIT(0),
3677 .halt_reg = 0x3f004,
3680 .enable_reg = 0x3f004,
3681 .enable_mask = BIT(0),
3690 .halt_reg = 0x3f044,
3693 .enable_reg = 0x3f044,
3694 .enable_mask = BIT(0),
3708 .halt_reg = 0,
3711 .enable_reg = 0x3f040,
3712 .enable_mask = BIT(0),
3721 .halt_reg = 0x3f080,
3724 .enable_reg = 0x3f080,
3725 .enable_mask = BIT(0),
3734 .halt_reg = 0,
3737 .enable_reg = 0x3f07c,
3738 .enable_mask = BIT(0),
3747 .halt_reg = 0x4c020,
3750 .enable_reg = 0x4c020,
3751 .enable_mask = BIT(0),
3760 .halt_reg = 0x4c024,
3763 .enable_reg = 0x4c024,
3764 .enable_mask = BIT(0),
3773 .halt_reg = 0x4c02c,
3776 .enable_reg = 0x4c02c,
3777 .enable_mask = BIT(0),
3791 .halt_reg = 0x4c01c,
3794 .enable_reg = 0x4c01c,
3795 .enable_mask = BIT(0),
3809 .halt_reg = 0x12014,
3812 .enable_reg = 0x4500c,
3822 .halt_reg = 0x12090,
3825 .enable_reg = 0x4500c,
3835 .halt_reg = 0x1203c,
3838 .enable_reg = 0x4500c,
3848 .gdscr = 0x3f078,
3861 .gdscr = 0x4c018,
3862 .cxcs = (unsigned int []){ 0x4c024, 0x4c01c },
3871 .gdscr = 0x4c028,
3872 .cxcs = (unsigned int []){ 0x4c02c },
3882 .gdscr = 0x4d078,
3883 .cxcs = (unsigned int []){ 0x4d080, 0x4d088 },
3892 .gdscr = 0x5701c,
3893 .cxcs = (unsigned int []){ 0x57020, 0x57028 },
3902 .gdscr = 0x58034,
3903 .cxcs = (unsigned int []){ 0x58038, 0x58048, 0x5600c, 0x58050 },
3912 .gdscr = 0x5806c,
3913 .cxcs = (unsigned int []){ 0x5805c, 0x58068, 0x5600c, 0x58074 },
3922 .gdscr = 0x5901c,
3923 .clamp_io_ctrl = 0x5b00c,
3924 .cxcs = (unsigned int []){ 0x59000, 0x59024 },
3934 .gdscr = 0x5904c,
3935 .cxcs = (unsigned int []){ 0x59020 },
3944 .gdscr = 0x58078,
3945 .cxcs = (unsigned int []){ 0x5803c, 0x58064 },
4169 [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
4170 [GCC_MSS_BCR] = { 0x71000 },
4171 [GCC_QUSB2_PHY_BCR] = { 0x4103c },
4172 [GCC_USB3PHY_PHY_BCR] = { 0x3f03c },
4173 [GCC_USB3_PHY_BCR] = { 0x3f034 },
4174 [GCC_USB_30_BCR] = { 0x3f070 },
4181 .max_register = 0x80000,