Lines Matching +full:0 +full:x4e000
20 bus@0 {
24 ranges = <0x0 0x0 0x0 0x40000000>;
28 reg = <0x00100000 0xf000>,
29 <0x0010f000 0x1000>;
35 reg = <0x2200000 0x10000>,
36 <0x2210000 0x10000>;
93 reg = <0x02300000 0x1000>;
103 reg = <0x2390000 0x1000>,
104 <0x23a0000 0x1000>,
105 <0x23b0000 0x1000>,
106 <0x23c0000 0x1000>,
107 <0x23d0000 0x1000>,
108 <0x23e0000 0x1000>;
116 reg = <0x02490000 0x10000>;
134 snps,burst-map = <0x7>;
142 reg = <0x2600000 0x210000>;
191 ranges = <0x02900000 0x02900000 0x200000>;
197 reg = <0x02930000 0x20000>;
199 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
242 reg = <0x02a41000 0x1000>,
243 <0x02a42000 0x2000>;
255 reg = <0x02900800 0x800>;
262 ranges = <0x02900800 0x02900800 0x11800>;
268 reg = <0x0290f000 0x1000>;
319 reg = <0x2901000 0x100>;
333 reg = <0x2901100 0x100>;
347 reg = <0x2901200 0x100>;
361 reg = <0x2901300 0x100>;
375 reg = <0x2901400 0x100>;
389 reg = <0x2901500 0x100>;
403 reg = <0x2904000 0x100>;
416 reg = <0x2904100 0x100>;
429 reg = <0x2904200 0x100>;
442 reg = <0x2904300 0x100>;
455 reg = <0x2905000 0x100>;
468 reg = <0x2905100 0x100>;
481 reg = <0x2902000 0x200>;
489 reg = <0x2902200 0x200>;
497 reg = <0x2902400 0x200>;
505 reg = <0x2902600 0x200>;
513 reg = <0x290a000 0x200>;
521 reg = <0x290a200 0x200>;
528 reg = <0x2903000 0x100>;
535 reg = <0x2903100 0x100>;
542 reg = <0x2903200 0x100>;
549 reg = <0x2903300 0x100>;
557 reg = <0x2903800 0x100>;
565 reg = <0x2903900 0x100>;
573 reg = <0x2903a00 0x100>;
581 reg = <0x2903b00 0x100>;
589 reg = <0x2908000 0x100>;
599 reg = <0x2908100 0x100>;
605 reg = <0x2908200 0x200>;
612 reg = <0x290bb00 0x800>;
620 reg = <0x2910000 0x2000>;
629 reg = <0x2430000 0x17000>,
630 <0xc300000 0x4000>;
659 reg = <0x02c00000 0x10000>, /* MC-SID */
660 <0x02c10000 0x10000>, /* MC Broadcast*/
661 <0x02c20000 0x10000>, /* MC0 */
662 <0x02c30000 0x10000>, /* MC1 */
663 <0x02c40000 0x10000>, /* MC2 */
664 <0x02c50000 0x10000>, /* MC3 */
665 <0x02b80000 0x10000>, /* MC4 */
666 <0x02b90000 0x10000>, /* MC5 */
667 <0x02ba0000 0x10000>, /* MC6 */
668 <0x02bb0000 0x10000>, /* MC7 */
669 <0x01700000 0x10000>, /* MC8 */
670 <0x01710000 0x10000>, /* MC9 */
671 <0x01720000 0x10000>, /* MC10 */
672 <0x01730000 0x10000>, /* MC11 */
673 <0x01740000 0x10000>, /* MC12 */
674 <0x01750000 0x10000>, /* MC13 */
675 <0x01760000 0x10000>, /* MC14 */
676 <0x01770000 0x10000>; /* MC15 */
687 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
688 <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
689 <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
704 * Limit the DMA range for memory clients to [38:0].
706 dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
710 reg = <0x0 0x02c60000 0x0 0x90000>,
711 <0x0 0x01780000 0x0 0x80000>;
716 #interconnect-cells = <0>;
724 reg = <0x03010000 0x000e0000>;
725 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
740 reg = <0x03100000 0x40>;
752 reg = <0x03110000 0x40>;
764 reg = <0x03130000 0x40>;
776 reg = <0x03140000 0x40>;
788 reg = <0x03150000 0x40>;
800 reg = <0x03160000 0x10000>;
803 #size-cells = <0>;
817 reg = <0x03170000 0x40>;
829 reg = <0x03180000 0x10000>;
832 #size-cells = <0>;
847 reg = <0x03190000 0x10000>;
850 #size-cells = <0>;
855 pinctrl-0 = <&state_dpaux1_i2c>;
868 reg = <0x031b0000 0x10000>;
871 #size-cells = <0>;
876 pinctrl-0 = <&state_dpaux0_i2c>;
889 reg = <0x031c0000 0x10000>;
892 #size-cells = <0>;
897 pinctrl-0 = <&state_dpaux2_i2c>;
910 reg = <0x031e0000 0x10000>;
913 #size-cells = <0>;
918 pinctrl-0 = <&state_dpaux3_i2c>;
930 reg = <0x3270000 0x1000>;
933 #size-cells = <0>;
944 reg = <0x3300000 0x1000>;
947 #size-cells = <0>;
959 reg = <0x3280000 0x10000>;
971 reg = <0x3290000 0x10000>;
983 reg = <0x32a0000 0x10000>;
995 reg = <0x32c0000 0x10000>;
1007 reg = <0x32d0000 0x10000>;
1019 reg = <0x32e0000 0x10000>;
1031 reg = <0x32f0000 0x10000>;
1042 reg = <0x03400000 0x10000>;
1059 pinctrl-0 = <&sdmmc1_3v3>;
1062 <0x07>;
1064 <0x07>;
1065 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1067 <0x07>;
1068 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1069 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1070 nvidia,default-tap = <0x9>;
1071 nvidia,default-trim = <0x5>;
1081 reg = <0x03440000 0x10000>;
1098 pinctrl-0 = <&sdmmc3_3v3>;
1100 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
1101 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
1102 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
1104 <0x07>;
1105 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1107 <0x07>;
1108 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1109 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1110 nvidia,default-tap = <0x9>;
1111 nvidia,default-trim = <0x5>;
1121 reg = <0x03460000 0x10000>;
1136 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
1137 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
1138 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
1140 <0x0a>;
1141 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
1143 <0x0a>;
1144 nvidia,default-tap = <0x8>;
1145 nvidia,default-trim = <0x14>;
1158 reg = <0x3510000 0x10000>;
1177 reg = <0x03520000 0x1000>,
1178 <0x03540000 0x1000>;
1193 usb2-0 {
1196 #phy-cells = <0>;
1202 #phy-cells = <0>;
1208 #phy-cells = <0>;
1214 #phy-cells = <0>;
1221 usb3-0 {
1224 #phy-cells = <0>;
1230 #phy-cells = <0>;
1236 #phy-cells = <0>;
1242 #phy-cells = <0>;
1249 usb2-0 {
1265 usb3-0 {
1285 reg = <0x03550000 0x8000>,
1286 <0x03558000 0x1000>;
1307 reg = <0x03610000 0x40000>,
1308 <0x03600000 0x10000>;
1342 reg = <0x03820000 0x10000>;
1351 reg = <0x03881000 0x1000>,
1352 <0x03882000 0x2000>,
1353 <0x03884000 0x2000>,
1354 <0x03886000 0x2000>;
1362 reg = <0x03960000 0x10000>;
1371 reg = <0x03c00000 0xa0000>;
1389 reg = <0x03e10000 0x10000>;
1392 #phy-cells = <0>;
1397 reg = <0x03e20000 0x10000>;
1400 #phy-cells = <0>;
1405 reg = <0x03e30000 0x10000>;
1408 #phy-cells = <0>;
1413 reg = <0x03e40000 0x10000>;
1416 #phy-cells = <0>;
1421 reg = <0x03e50000 0x10000>;
1424 #phy-cells = <0>;
1429 reg = <0x03e60000 0x10000>;
1432 #phy-cells = <0>;
1437 reg = <0x03e70000 0x10000>;
1440 #phy-cells = <0>;
1445 reg = <0x03e80000 0x10000>;
1448 #phy-cells = <0>;
1453 reg = <0x03e90000 0x10000>;
1456 #phy-cells = <0>;
1461 reg = <0x03ea0000 0x10000>;
1464 #phy-cells = <0>;
1469 reg = <0x03eb0000 0x10000>;
1472 #phy-cells = <0>;
1477 reg = <0x03ec0000 0x10000>;
1480 #phy-cells = <0>;
1485 reg = <0x03ed0000 0x10000>;
1488 #phy-cells = <0>;
1493 reg = <0x03ee0000 0x10000>;
1496 #phy-cells = <0>;
1501 reg = <0x03ef0000 0x10000>;
1504 #phy-cells = <0>;
1509 reg = <0x03f00000 0x10000>;
1512 #phy-cells = <0>;
1517 reg = <0x03f10000 0x10000>;
1520 #phy-cells = <0>;
1525 reg = <0x03f20000 0x10000>;
1528 #phy-cells = <0>;
1533 reg = <0x03f30000 0x10000>;
1536 #phy-cells = <0>;
1541 reg = <0x03f40000 0x10000>;
1544 #phy-cells = <0>;
1549 reg = <0xb600000 0x1000>;
1559 reg = <0xbe00000 0x1000>;
1569 reg = <0x0c150000 0x90000>;
1575 * Shared interrupt 0 is routed only to AON/SPE, so
1584 reg = <0x0c240000 0x10000>;
1587 #size-cells = <0>;
1601 reg = <0x0c250000 0x10000>;
1604 #size-cells = <0>;
1611 dmas = <&gpcdma 0>, <&gpcdma 0>;
1618 reg = <0x0c280000 0x40>;
1630 reg = <0x0c290000 0x40>;
1642 reg = <0x0c2a0000 0x10000>;
1653 reg = <0xc2f0000 0x1000>,
1654 <0xc2f1000 0x1000>;
1668 reg = <0xc340000 0x10000>;
1679 reg = <0x0c360000 0x10000>,
1680 <0x0c370000 0x10000>,
1681 <0x0c380000 0x10000>,
1682 <0x0c390000 0x10000>,
1683 <0x0c3a0000 0x10000>;
1711 reg = <0xc600000 0x1000>;
1720 reg = <0xd600000 0x1000>;
1730 reg = <0x10000000 0x800000>;
1796 stream-match-mask = <0x7f80>;
1806 reg = <0x12000000 0x800000>,
1807 <0x11000000 0x800000>;
1874 stream-match-mask = <0x7f80>;
1884 reg = <0x13e00000 0x10000>,
1885 <0x13e10000 0x10000>;
1898 ranges = <0x15000000 0x15000000 0x01000000>;
1904 iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>,
1915 reg = <0x15140000 0x00040000>;
1929 nvidia,host1x-class = <0xf5>;
1934 reg = <0x15200000 0x00040000>;
1954 ranges = <0x15200000 0x15200000 0x40000>;
1958 reg = <0x15200000 0x10000>;
1971 nvidia,head = <0>;
1976 reg = <0x15210000 0x10000>;
1994 reg = <0x15220000 0x10000>;
2012 reg = <0x15230000 0x10000>;
2031 reg = <0x15340000 0x00040000>;
2048 reg = <0x15380000 0x40000>;
2064 reg = <0x15480000 0x00040000>;
2078 nvidia,host1x-class = <0xf0>;
2083 reg = <0x154c0000 0x40000>;
2097 nvidia,host1x-class = <0x21>;
2102 reg = <0x155c0000 0x10000>;
2130 #size-cells = <0>;
2136 reg = <0x155d0000 0x10000>;
2164 #size-cells = <0>;
2170 reg = <0x155e0000 0x10000>;
2198 #size-cells = <0>;
2204 reg = <0x155f0000 0x10000>;
2232 #size-cells = <0>;
2238 reg = <0x15a80000 0x00040000>;
2252 nvidia,host1x-class = <0x22>;
2257 reg = <0x15b00000 0x40000>;
2269 pinctrl-0 = <&state_dpaux0_aux>;
2276 nvidia,interface = <0>;
2281 reg = <0x15b40000 0x40000>;
2293 pinctrl-0 = <&state_dpaux1_aux>;
2305 reg = <0x15b80000 0x40000>;
2317 pinctrl-0 = <&state_dpaux2_aux>;
2329 reg = <0x15bc0000 0x40000>;
2341 pinctrl-0 = <&state_dpaux3_aux>;
2354 reg = <0x17000000 0x1000000>,
2355 <0x18000000 0x1000000>;
2380 interconnect-names = "dma-mem", "read-0-hp", "write-0",
2390 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
2391 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
2392 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2393 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
2416 interrupt-map-mask = <0 0 0 0>;
2417 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2425 bus-range = <0x0 0xff>;
2427 …ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 …
2428 …<0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB -…
2429 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2434 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>;
2435 iommu-map-mask = <0x0>;
2442 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
2443 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
2444 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2445 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
2468 interrupt-map-mask = <0 0 0 0>;
2469 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2477 bus-range = <0x0 0xff>;
2479 …ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 …
2480 …<0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB -…
2481 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2486 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>;
2487 iommu-map-mask = <0x0>;
2494 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
2495 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
2496 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2497 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
2520 interrupt-map-mask = <0 0 0 0>;
2521 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
2529 bus-range = <0x0 0xff>;
2531 …ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 …
2532 …<0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB +…
2533 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2538 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>;
2539 iommu-map-mask = <0x0>;
2546 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
2547 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
2548 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2549 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
2572 interrupt-map-mask = <0 0 0 0>;
2573 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
2581 bus-range = <0x0 0xff>;
2583 …ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 G…
2584 …<0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 6…
2585 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2590 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2591 iommu-map-mask = <0x0>;
2598 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
2599 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
2600 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2601 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
2610 linux,pci-domain = <0>;
2624 interrupt-map-mask = <0 0 0 0>;
2625 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2627 nvidia,bpmp = <&bpmp 0>;
2633 bus-range = <0x0 0xff>;
2635 …ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 G…
2636 …<0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 6…
2637 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2642 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2643 iommu-map-mask = <0x0>;
2650 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2651 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
2652 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2653 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
2665 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
2681 interrupt-map-mask = <0 0 0 0>;
2682 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2688 bus-range = <0x0 0xff>;
2690 …ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 G…
2691 …<0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 6…
2692 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2697 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2698 iommu-map-mask = <0x0>;
2705 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
2706 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2707 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
2708 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
2736 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2737 iommu-map-mask = <0x0>;
2744 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
2745 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2746 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */
2747 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
2766 nvidia,bpmp = <&bpmp 0>;
2775 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2776 iommu-map-mask = <0x0>;
2783 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2784 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2785 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
2786 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
2796 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
2817 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2818 iommu-map-mask = <0x0>;
2824 reg = <0x0 0x40000000 0x0 0x50000>;
2827 ranges = <0x0 0x0 0x40000000 0x50000>;
2831 reg = <0x4e000 0x1000>;
2837 reg = <0x4f000 0x1000>;
2862 #size-cells = <0>;
2875 #size-cells = <0>;
2877 cpu0_0: cpu@0 {
2880 reg = <0x000>;
2894 reg = <0x001>;
2908 reg = <0x100>;
2922 reg = <0x101>;
2936 reg = <0x200>;
2950 reg = <0x201>;
2964 reg = <0x300>;
2978 reg = <0x301>;
3095 assigned-clock-parents = <0>,
3108 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,