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Searched refs:TSC_IOASCR_G3_IO1_Pos (Results 1 – 25 of 81) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f058xx.h5597 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
5598 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
Dstm32f051x8.h5628 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
5629 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
Dstm32f071xb.h6181 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
6182 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
Dstm32f042x6.h9403 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
9404 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
Dstm32f048xx.h9367 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
9368 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
Dstm32f072xb.h9978 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
9979 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
Dstm32f091xc.h10635 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
10636 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
Dstm32f098xx.h10602 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
10603 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
Dstm32f078xx.h9948 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
9949 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l052xx.h6154 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
6155 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
Dstm32l062xx.h6291 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
6292 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
Dstm32l053xx.h6313 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
6314 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
Dstm32l072xx.h6450 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
6451 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
Dstm32l073xx.h6609 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
6610 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
Dstm32l083xx.h6746 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
6747 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
Dstm32l063xx.h6448 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
6449 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
Dstm32l082xx.h6587 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
6588 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h7415 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
7416 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
Dstm32f318xx.h7402 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
7403 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9298 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
9299 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h8637 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
8638 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
Dstm32u083xx.h9574 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
9575 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb1mxx.h8068 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
8069 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h7896 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
7897 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
Dstm32wb15xx.h8068 #define TSC_IOASCR_G3_IO1_Pos (8U) macro
8069 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */

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