1 /**
2   ******************************************************************************
3   * @file    stm32u083xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS STM32U083xx Device Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - Peripheral's registers declarations and bits definition
10   *           - Macros to access peripheral's registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * Copyright (c) 2023 STMicroelectronics.
16   * All rights reserved.
17   *
18   * This software is licensed under terms that can be found in the LICENSE file
19   * in the root directory of this software component.
20   * If no LICENSE file comes with this software, it is provided AS-IS.
21   *
22   ******************************************************************************
23   */
24 
25 /** @addtogroup CMSIS_Device
26   * @{
27   */
28 
29 /** @addtogroup stm32u083xx
30   * @{
31   */
32 
33 #ifndef STM32U083xx_H
34 #define STM32U083xx_H
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif /* __cplusplus */
39 
40 /** @addtogroup Configuration_section_for_CMSIS
41   * @{
42   */
43 
44 /**
45   * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
46    */
47 #define __CM0PLUS_REV             0 /*!< Core Revision r0p0                            */
48 #define __MPU_PRESENT             1 /*!< STM32U0xx  provides an MPU                    */
49 #define __VTOR_PRESENT            1 /*!< Vector  Table  Register supported             */
50 #define __NVIC_PRIO_BITS          2 /*!< STM32U0xx uses 2 Bits for the Priority Levels */
51 #define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used  */
52 
53 /**
54   * @}
55   */
56 
57 /** @addtogroup Peripheral_interrupt_number_definition
58   * @{
59   */
60 
61 /**
62  * @brief STM32U0XX Interrupt Number Definition, according to the selected device
63  *        in @ref Library_configuration_section
64  */
65 typedef enum
66 {
67 /******  Cortex-M Processor Exceptions Numbers *****************************************************************/
68   Reset_IRQn                  = -15,    /*!< -15 Reset Vector, invoked on Power up and warm reset              */
69   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
70   HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
71   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */
72   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */
73   SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */
74 /******  STM32 specific Interrupt Numbers **********************************************************************/
75   WWDG_IWDG_IRQn              = 0,      /*!< Window watchdog interrupt + Independent watchdog interrupt        */
76   PVD_PVM_IRQn                = 1,      /*!< PVD through EXTI Line detection Interrupt(EXTI lines 16/19/20/21) */
77   RTC_TAMP_IRQn               = 2,      /*!< RTC and TAMP interrupts (combined EXTI lines 20 & 21)             */
78   FLASH_ECC_IRQn              = 3,      /*!< FLASH global Interrupt + FLASH ECC interrupt                      */
79   RCC_CRS_IRQn                = 4,      /*!< RCC global Interrupt + CRS global interrupt                       */
80   EXTI0_1_IRQn                = 5,      /*!< EXTI Line0 & Line1 Interrupt                                      */
81   EXTI2_3_IRQn                = 6,      /*!< EXTI Line2 & Line3 Interrupt                                      */
82   EXTI4_15_IRQn               = 7,      /*!< EXTI Line4 to Line15 Interrupt                                    */
83   USB_DRD_FS_IRQn             = 8,      /*!< USB global interrupt (combined with EXTI 36)                      */
84   DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                          */
85   DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                           */
86   DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQn  = 11,     /*!< DMAMUX_OVR_IT + DMA1 channel 4 to 7 +  DMA2 channel 1 to 5        */
87   ADC_COMP1_2_IRQn            = 12,     /*!< ADC and COMP1/COMP2 interrupts (ADC combined with EXTI 17 & 18)   */
88   TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 break, update, trigger, commutation, error, direction change and index interrupts        */
89   TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare interrupt                                    */
90   TIM2_IRQn                   = 15,     /*!< TIM2 global Interrupt                                             */
91   TIM3_IRQn                   = 16,     /*!< TIM3 global Interrupt                                             */
92   TIM6_DAC_LPTIM1_IRQn        = 17,     /*!< TIM6 + LPTIM1 + DAC global interrupt (combined with EXTI 31)      */
93   TIM7_LPTIM2_IRQn            = 18,     /*!< TIM7 + LPTIM2 global interrupt (combined with EXTI 32)            */
94   TIM15_LPTIM3_IRQn           = 19,     /*!< TIM15 + LPTIM3 global interrupt (combined with EXTI 33)           */
95   TIM16_IRQn                  = 20,     /*!< TIM16 global interrupt                                            */
96   TSC_IRQn                    = 21,     /*!< TSC global interrupt                                              */
97   LCD_IRQn                    = 22,     /*!< LCD global interrupt                                              */
98   I2C1_IRQn                   = 23,     /*!< I2C1 global interrupt (combined with EXTI 23)                     */
99   I2C2_3_4_IRQn               = 24,     /*!< I2C2 + I2C3 global interrupt (combined with EXTI 22) + I2C4 global interrupt        */
100   SPI1_IRQn                   = 25,     /*!< SPI1/I2S1 global interrupt                                        */
101   SPI2_3_IRQn                 = 26,     /*!< SPI2 and SPI3 global interrupt                                    */
102   USART1_IRQn                 = 27,     /*!< USART1 global interrupt (combined with EXTI 25)                   */
103   USART2_LPUART2_IRQn         = 28,     /*!< USART2 global interrupt (combined with EXTI 26) + LPUART2 global interrupt (combined with EXTI lines 35)      */
104   USART3_LPUART1_IRQn         = 29,     /*!< USART3  (combined with EXTI 24) + LPUART1 global interrupt (combined with EXTI lines 28)                      */
105   USART4_LPUART3_IRQn         = 30,     /*!< USART4  global interrupt (combined with EXTI 20) + LPUART3 (combined with EXTI lines 34)                      */
106   RNG_CRYP_IRQn               = 31,     /*!< RNG + CRYPTO global interrupt                                     */
107 } IRQn_Type;
108 
109 /**
110   * @}
111   */
112 
113 #include "core_cm0plus.h"               /* Cortex-M0+ processor and core peripherals */
114 #include "system_stm32u0xx.h"
115 #include <stdint.h>
116 
117 /** @addtogroup Peripheral_registers_structures
118   * @{
119   */
120 /**
121   * @brief AES hardware accelerator
122   */
123 typedef struct
124 {
125   __IO uint32_t CR;          /*!< AES control register,                        Address offset: 0x00 */
126   __IO uint32_t SR;          /*!< AES status register,                         Address offset: 0x04 */
127   __IO uint32_t DINR;        /*!< AES data input register,                     Address offset: 0x08 */
128   __IO uint32_t DOUTR;       /*!< AES data output register,                    Address offset: 0x0C */
129   __IO uint32_t KEYR0;       /*!< AES key register 0,                          Address offset: 0x10 */
130   __IO uint32_t KEYR1;       /*!< AES key register 1,                          Address offset: 0x14 */
131   __IO uint32_t KEYR2;       /*!< AES key register 2,                          Address offset: 0x18 */
132   __IO uint32_t KEYR3;       /*!< AES key register 3,                          Address offset: 0x1C */
133   __IO uint32_t IVR0;        /*!< AES initialization vector register 0,        Address offset: 0x20 */
134   __IO uint32_t IVR1;        /*!< AES initialization vector register 1,        Address offset: 0x24 */
135   __IO uint32_t IVR2;        /*!< AES initialization vector register 2,        Address offset: 0x28 */
136   __IO uint32_t IVR3;        /*!< AES initialization vector register 3,        Address offset: 0x2C */
137   __IO uint32_t KEYR4;       /*!< AES key register 4,                          Address offset: 0x30 */
138   __IO uint32_t KEYR5;       /*!< AES key register 5,                          Address offset: 0x34 */
139   __IO uint32_t KEYR6;       /*!< AES key register 6,                          Address offset: 0x38 */
140   __IO uint32_t KEYR7;       /*!< AES key register 7,                          Address offset: 0x3C */
141   __IO uint32_t SUSP0R;      /*!< AES Suspend register 0,                      Address offset: 0x40 */
142   __IO uint32_t SUSP1R;      /*!< AES Suspend register 1,                      Address offset: 0x44 */
143   __IO uint32_t SUSP2R;      /*!< AES Suspend register 2,                      Address offset: 0x48 */
144   __IO uint32_t SUSP3R;      /*!< AES Suspend register 3,                      Address offset: 0x4C */
145   __IO uint32_t SUSP4R;      /*!< AES Suspend register 4,                      Address offset: 0x50 */
146   __IO uint32_t SUSP5R;      /*!< AES Suspend register 5,                      Address offset: 0x54 */
147   __IO uint32_t SUSP6R;      /*!< AES Suspend register 6,                      Address offset: 0x58 */
148   __IO uint32_t SUSP7R;      /*!< AES Suspend register 7,                      Address offset: 0x5C */
149       uint32_t RESERVED1[168];/*!< Reserved,                                   Address offset: 0x60 -- 0x2FC */
150   __IO uint32_t IER;          /*!< AES Interrupt Enable Register,              Address offset: 0x300 */
151   __IO uint32_t ISR;          /*!< AES Interrupt Status Register,              Address offset: 0x304 */
152   __IO uint32_t ICR;          /*!< AES Interrupt Clear Register,               Address offset: 0x308 */
153 } AES_TypeDef;
154 
155 /**
156   * @brief Analog to Digital Converter
157   */
158 
159 typedef struct
160 {
161   __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
162   __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
163   __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
164   __IO uint32_t CFGR1;        /*!< ADC configuration register 1,                  Address offset: 0x0C */
165   __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
166   __IO uint32_t SMPR;         /*!< ADC sampling time register,                    Address offset: 0x14 */
167        uint32_t RESERVED1;    /*!< Reserved,                                                      0x18 */
168        uint32_t RESERVED2;    /*!< Reserved,                                                      0x1C */
169   __IO uint32_t AWD1TR;       /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
170   __IO uint32_t AWD2TR;       /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
171   __IO uint32_t CHSELR;       /*!< ADC group regular sequencer register,          Address offset: 0x28 */
172   __IO uint32_t AWD3TR;       /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x2C */
173        uint32_t RESERVED3[4]; /*!< Reserved,                                               0x30 - 0x3C */
174   __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
175        uint32_t RESERVED4[23];/*!< Reserved,                                               0x44 - 0x9C */
176   __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 2 configuration register,  Address offset: 0xA0 */
177   __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 configuration register,  Address offset: 0xA4 */
178        uint32_t RESERVED5[3]; /*!< Reserved,                                               0xA8 - 0xB0 */
179   __IO uint32_t CALFACT;      /*!< ADC Calibration factor register,               Address offset: 0xB4 */
180 } ADC_TypeDef;
181 
182 typedef struct
183 {
184   __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC1 base address + 0x308 */
185 } ADC_Common_TypeDef;
186 
187 /**
188   * @brief Comparator
189   */
190 typedef struct
191 {
192   __IO uint32_t CSR;         /*!< COMP control and status register,                                                 Address offset: 0x00 */
193 } COMP_TypeDef;
194 
195 typedef struct
196 {
197   __IO uint32_t CSR_ODD;        /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */
198   __IO uint32_t CSR_EVEN;       /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */
199 } COMP_Common_TypeDef;
200 
201 /**
202   * @brief CRC calculation unit
203   */
204 typedef struct
205 {
206   __IO uint32_t DR;             /*!< CRC Data register,                           Address offset: 0x00 */
207   __IO uint32_t IDR;            /*!< CRC Independent data register,               Address offset: 0x04 */
208   __IO uint32_t CR;             /*!< CRC Control register,                        Address offset: 0x08 */
209        uint32_t RESERVED2;      /*!< Reserved,                                                    0x0C */
210   __IO uint32_t INIT;           /*!< Initial CRC value register,                  Address offset: 0x10 */
211   __IO uint32_t POL;            /*!< CRC polynomial register,                     Address offset: 0x14 */
212        uint32_t RESERVED3[246]; /*!< Reserved,                                                         */
213   __IO uint32_t HWCFGR;         /*!< CRC IP HWCFGR register,                     Address offset: 0x3F0 */
214   __IO uint32_t VERR;           /*!< CRC IP version register,                    Address offset: 0x3F4 */
215   __IO uint32_t PIDR;           /*!< CRC IP type identification register,        Address offset: 0x3F8 */
216   __IO uint32_t SIDR;           /*!< CRC IP map Size ID register,                Address offset: 0x3FC */
217 } CRC_TypeDef;
218 
219 /**
220   * @brief Clock Recovery System
221   */
222 typedef struct
223 {
224   __IO uint32_t CR;            /*!< CRS control register,               Address offset: 0x00 */
225   __IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */
226   __IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */
227   __IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
228 } CRS_TypeDef;
229 
230 /**
231   * @brief Digital to Analog Converter
232   */
233 typedef struct
234 {
235   __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */
236   __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */
237   __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
238   __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
239   __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
240   __IO uint32_t DHR12R2;     /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
241   __IO uint32_t DHR12L2;     /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
242   __IO uint32_t DHR8R2;      /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
243   __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
244   __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
245   __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
246   __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */
247   __IO uint32_t DOR2;        /*!< DAC channel2 data output register,                       Address offset: 0x30 */
248   __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */
249   __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */
250   __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */
251   __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
252   __IO uint32_t SHSR2;       /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
253   __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
254   __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
255 } DAC_TypeDef;
256 
257 /**
258   * @brief Debug MCU
259   */
260 
261 typedef struct
262 {
263   __IO uint32_t IDCODE;           /*!< MCU device ID code,                        Address offset: 0x00      */
264   __IO uint32_t CR;               /*!< Debug configuration register,              Address offset: 0x04      */
265   __IO uint32_t APBFZ1;           /*!< Debug APB freeze register 1,               Address offset: 0x08      */
266   __IO uint32_t APBFZ2;           /*!< Debug APB freeze register 2,               Address offset: 0x0C      */
267 } DBGMCU_TypeDef;
268 
269 /**
270   * @brief DMA Controller
271   */
272 typedef struct
273 {
274   __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
275   __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
276   __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
277   __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
278 } DMA_Channel_TypeDef;
279 
280 typedef struct
281 {
282   __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
283   __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
284 } DMA_TypeDef;
285 
286 /**
287   * @brief DMA Multiplexer
288   */
289 typedef struct
290 {
291   __IO uint32_t   CCR;       /*!< DMA Multiplexer Channel x Control Register    Address offset: 0x0004 * (channel x) */
292 }DMAMUX_Channel_TypeDef;
293 
294 typedef struct
295 {
296   __IO uint32_t   CSR;       /*!< DMA Channel Status Register                    Address offset: 0x0080   */
297   __IO uint32_t   CFR;       /*!< DMA Channel Clear Flag Register                Address offset: 0x0084   */
298 }DMAMUX_ChannelStatus_TypeDef;
299 
300 typedef struct
301 {
302   __IO uint32_t   RGCR;        /*!< DMA Request Generator x Control Register     Address offset: 0x0100 + 0x0004 * (Req Gen x) */
303 }DMAMUX_RequestGen_TypeDef;
304 
305 typedef struct
306 {
307   __IO uint32_t   RGSR;        /*!< DMA Request Generator Status Register        Address offset: 0x0140   */
308   __IO uint32_t   RGCFR;       /*!< DMA Request Generator Clear Flag Register    Address offset: 0x0144   */
309 }DMAMUX_RequestGenStatus_TypeDef;
310 
311 /**
312   * @brief Asynch Interrupt/Event Controller (EXTI)
313   */
314 typedef struct
315 {
316   __IO uint32_t RTSR1;          /*!< EXTI Rising Trigger Selection Register 1,        Address offset:   0x00 */
317   __IO uint32_t FTSR1;          /*!< EXTI Falling Trigger Selection Register 1,       Address offset:   0x04 */
318   __IO uint32_t SWIER1;         /*!< EXTI Software Interrupt event Register 1,        Address offset:   0x08 */
319   __IO uint32_t RPR1;           /*!< EXTI Rising Pending Register 1,                  Address offset:   0x0C */
320   __IO uint32_t FPR1;           /*!< EXTI Falling Pending Register 1,                 Address offset:   0x10 */
321        uint32_t RESERVED1[19];  /*!< Reserved 1,                                                0x14 -- 0x5C */
322   __IO uint32_t EXTICR[4];      /*!< EXIT External Interrupt Configuration Register,            0x60 -- 0x6C */
323        uint32_t RESERVED3[4];   /*!< Reserved 3,                                                0x70 -- 0x7C */
324   __IO uint32_t IMR1;           /*!< EXTI Interrupt Mask Register 1,                  Address offset:   0x80 */
325   __IO uint32_t EMR1;           /*!< EXTI Event Mask Register 1,                      Address offset:   0x84 */
326        uint32_t RESERVED4[2];   /*!< Reserved 4,                                                0x88 -- 0x8C */
327   __IO uint32_t IMR2;           /*!< EXTI Interrupt Mask Register 2,                  Address offset:   0x90 */
328   __IO uint32_t EMR2;           /*!< EXTI Event Mask Register 2,                      Address offset:   0x94 */
329 } EXTI_TypeDef;
330 
331 /**
332   * @brief FLASH Registers
333   */
334 typedef struct
335 {
336   __IO uint32_t ACR;           /*!< FLASH Access Control register,                     Address offset: 0x00 */
337        uint32_t RESERVED1;     /*!< Reserved1,                                         Address offset: 0x04 */
338   __IO uint32_t KEYR;          /*!< FLASH Key register,                                Address offset: 0x08 */
339   __IO uint32_t OPTKEYR;       /*!< FLASH Option Key register,                         Address offset: 0x0C */
340   __IO uint32_t SR;            /*!< FLASH Status register,                             Address offset: 0x10 */
341   __IO uint32_t CR;            /*!< FLASH Control register,                            Address offset: 0x14 */
342   __IO uint32_t ECCR;          /*!< FLASH ECC register,                                Address offset: 0x18 */
343        uint32_t RESERVED2;     /*!< Reserved2,                                         Address offset: 0x1C */
344   __IO uint32_t OPTR;          /*!< FLASH Option register,                             Address offset: 0x20 */
345        uint32_t RESERVED3[2];  /*!< Reserved3,                                                 0x24 -- 0x28 */
346   __IO uint32_t WRP1AR;        /*!< FLASH Bank WRP area A address register,            Address offset: 0x2C */
347   __IO uint32_t WRP1BR;        /*!< FLASH Bank WRP area B address register,            Address offset: 0x30 */
348        uint32_t RESERVED4[19]; /*!< Reserved4,                                                0x34 -- 0x7C */
349   __IO uint32_t SECR;          /*!< FLASH Security option register,                    Address offset: 0x80 */
350        uint32_t RESERVED5;     /*!< Reserved5,                                         Address offset: 0x84 */
351   __IO uint32_t OEM1KEYW0R;    /*!< FLASH OEM1 key register 1,                         Address offset: 0x88 */
352   __IO uint32_t OEM1KEYW1R;    /*!< FLASH OEM1 key register 2,                         Address offset: 0x8C */
353   __IO uint32_t OEM1KEYW2R;    /*!< FLASH OEM1 key register 3,                         Address offset: 0x90 */
354   __IO uint32_t OEM1KEYW3R;    /*!< FLASH OEM1 key register 4,                         Address offset: 0x94 */
355   __IO uint32_t OEM2KEYW0R;    /*!< FLASH OEM2 key register 5,                         Address offset: 0x98 */
356   __IO uint32_t OEM2KEYW1R;    /*!< FLASH OEM2 key register 6,                         Address offset: 0x9C */
357   __IO uint32_t OEM2KEYW2R;    /*!< FLASH OEM2 key register 7,                         Address offset: 0xA0 */
358   __IO uint32_t OEM2KEYW3R;    /*!< FLASH OEM2 key register 8,                         Address offset: 0xA4 */
359   __IO uint32_t OEMKEYSR;      /*!< FLASH OEM key status register,                     Address offset: 0xA8 */
360   __IO uint32_t HDPCR;         /*!< FLASH HDP control register,                        Address offset: 0xAC */
361   __IO uint32_t HDPEXTR;       /*!< FLASH HDP extension register,                      Address offset: 0xB0 */
362 } FLASH_TypeDef;
363 
364 /**
365   * @brief General Purpose I/O
366   */
367 typedef struct
368 {
369   __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
370   __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
371   __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
372   __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
373   __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
374   __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
375   __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
376   __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
377   __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
378   __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
379 } GPIO_TypeDef;
380 
381 /**
382   * @brief Instruction Cache
383   */
384 
385 typedef struct
386 {
387   __IO uint32_t CR;             /*!< ICACHE control register,               Address offset: 0x00 */
388   __IO uint32_t SR;             /*!< ICACHE status register,                Address offset: 0x04 */
389   __IO uint32_t IER;            /*!< ICACHE interrupt enable register,      Address offset: 0x08 */
390   __IO uint32_t FCR;            /*!< ICACHE Flag clear register,            Address offset: 0x0C */
391   __IO uint32_t HMONR;          /*!< ICACHE hit monitor register,           Address offset: 0x10 */
392   __IO uint32_t MMONR;          /*!< ICACHE miss monitor register,          Address offset: 0x14 */
393        uint32_t RESERVED1[2];   /*!< Reserved,                              Address offset: 0x018-0x01C */
394   __IO uint32_t CCR0;           /*!< ICACHE region 0 control register,      Address offset: 0x20 */
395   __IO uint32_t CCR1;           /*!< ICACHE region 1 control register,      Address offset: 0x24 */
396   __IO uint32_t CCR2;           /*!< ICACHE region 2 control register,      Address offset: 0x28 */
397   __IO uint32_t CCR3;           /*!< ICACHE region 3 control register,      Address offset: 0x2C */
398        uint32_t RESERVED2[240]; /*!< Reserved,                              Address offset: 0x30-0x3EC */
399   __IO uint32_t HWCFGR;         /*!< ICACHE HW configuration register,      Address offset: 0x3F0 */
400   __IO uint32_t VERR;           /*!< ICACHE version register,               Address offset: 0x3F4 */
401   __IO uint32_t IPIDR;          /*!< ICACHE IP identification register,     Address offset: 0x3F8 */
402   __IO uint32_t SIDR;           /*!< ICACHE size identification register,   Address offset: 0x3FC */
403 } ICACHE_TypeDef;
404 
405 /**
406   * @brief Inter-integrated Circuit Interface
407   */
408 typedef struct
409 {
410   __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
411   __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
412   __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
413   __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
414   __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
415   __IO uint32_t RESERVED;    /*!< Reserved,                          Address offset: 0x14 */
416   __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
417   __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
418   __IO uint32_t RESERVED0;   /*!< Reserved,                          Address offset: 0x20 */
419   __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
420   __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
421 } I2C_TypeDef;
422 
423 /**
424   * @brief Independent WATCHDOG
425   */
426 typedef struct
427 {
428   __IO uint32_t KR;          /*!< IWDG Key register,                Address offset: 0x00 */
429   __IO uint32_t PR;          /*!< IWDG Prescaler register,          Address offset: 0x04 */
430   __IO uint32_t RLR;         /*!< IWDG Reload register,             Address offset: 0x08 */
431   __IO uint32_t SR;          /*!< IWDG Status register,             Address offset: 0x0C */
432   __IO uint32_t WINR;        /*!< IWDG Window register,             Address offset: 0x10 */
433   __IO uint32_t EWCR;        /*!< IWDG wake-up interrupt register,  Address offset: 0x14 */
434 } IWDG_TypeDef;
435 
436 /**
437   * @brief LCD
438   */
439 
440 typedef struct
441 {
442   __IO uint32_t CR;          /*!< LCD control register,         Address offset: 0x00 */
443   __IO uint32_t FCR;         /*!< LCD frame control register,   Address offset: 0x04 */
444   __IO uint32_t SR;          /*!< LCD status register,          Address offset: 0x08 */
445   __IO uint32_t CLR;         /*!< LCD clear register,           Address offset: 0x0C */
446   uint32_t RESERVED;         /*!< Reserved,                     Address offset: 0x10 */
447   __IO uint32_t RAM[16];     /*!< LCD display memory,           Address offset: 0x14-0x50 */
448 } LCD_TypeDef;
449 
450 /**
451   * @brief LPTIMER
452   */
453 typedef struct
454 {
455   __IO uint32_t ISR;          /*!< LPTIM Interrupt and Status register,              Address offset: 0x00 */
456   __IO uint32_t ICR;          /*!< LPTIM Interrupt Clear register,                   Address offset: 0x04 */
457   __IO uint32_t DIER;         /*!< LPTIM Interrupt Enable register,                  Address offset: 0x08 */
458   __IO uint32_t CFGR;         /*!< LPTIM Configuration register,                     Address offset: 0x0C */
459   __IO uint32_t CR;           /*!< LPTIM Control register,                           Address offset: 0x10 */
460   __IO uint32_t CCR1;         /*!< LPTIM Capture/Compare register 1,                 Address offset: 0x14 */
461   __IO uint32_t ARR;          /*!< LPTIM Autoreload register,                        Address offset: 0x18 */
462   __IO uint32_t CNT;          /*!< LPTIM Counter register,                           Address offset: 0x1C */
463   __IO uint32_t RESERVED0;    /*!< Reserved,                                         Address offset: 0x20 */
464   __IO uint32_t CFGR2;        /*!< LPTIM Configuration register 2,                   Address offset: 0x24 */
465   __IO uint32_t RCR;          /*!< LPTIM Repetition register,                        Address offset: 0x28 */
466   __IO uint32_t CCMR1;        /*!< LPTIM Capture/Compare mode register 1,            Address offset: 0x2C */
467   __IO uint32_t CCMR2;        /*!< LPTIM Capture/Compare mode register 2,            Address offset: 0x30 */
468   __IO uint32_t CCR2;         /*!< LPTIM Capture/Compare register 2,                 Address offset: 0x34 */
469   __IO uint32_t CCR3;         /*!< LPTIM Capture/Compare register 3,                 Address offset: 0x38 */
470   __IO uint32_t CCR4;         /*!< LPTIM Capture/Compare register 4,                 Address offset: 0x3C */
471 } LPTIM_TypeDef;
472 
473 /**
474   * @brief Operational Amplifier (OPAMP)
475   */
476 typedef struct
477 {
478   __IO uint32_t CSR;         /*!< OPAMP control/status register,                     Address offset: 0x00 */
479   __IO uint32_t OTR;         /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */
480   __IO uint32_t LPOTR;       /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
481 } OPAMP_TypeDef;
482 
483 typedef struct
484 {
485   __IO uint32_t CSR;         /*!< OPAMP control/status register, used for bits common to
486                                   several OPAMP instances, Address offset: 0x00         */
487 } OPAMP_Common_TypeDef;
488 
489 
490 /**
491   * @brief Power Control
492   */
493 typedef struct
494 {
495   __IO uint32_t CR1;          /*!< PWR Power Control Register 1,                     Address offset: 0x00 */
496   __IO uint32_t CR2;          /*!< PWR Power Control Register 2,                     Address offset: 0x04 */
497   __IO uint32_t CR3;          /*!< PWR Power Control Register 3,                     Address offset: 0x08 */
498   __IO uint32_t CR4;          /*!< PWR Power Control Register 4,                     Address offset: 0x0C */
499   __IO uint32_t SR1;          /*!< PWR Power Status Register 1,                      Address offset: 0x10 */
500   __IO uint32_t SR2;          /*!< PWR Power Status Register 2,                      Address offset: 0x14 */
501   __IO uint32_t SCR;          /*!< PWR Power Status Reset Register,                  Address offset: 0x18 */
502        uint32_t RESERVED0;    /*!< Reserved,                                         Address offset: 0x1C */
503   __IO uint32_t PUCRA;        /*!< PWR Pull-Up Control Register of port A,           Address offset: 0x20 */
504   __IO uint32_t PDCRA;        /*!< PWR Pull-Down Control Register of port A,         Address offset: 0x24 */
505   __IO uint32_t PUCRB;        /*!< PWR Pull-Up Control Register of port B,           Address offset: 0x28 */
506   __IO uint32_t PDCRB;        /*!< PWR Pull-Down Control Register of port B,         Address offset: 0x2C */
507   __IO uint32_t PUCRC;        /*!< PWR Pull-Up Control Register of port C,           Address offset: 0x30 */
508   __IO uint32_t PDCRC;        /*!< PWR Pull-Down Control Register of port C,         Address offset: 0x34 */
509   __IO uint32_t PUCRD;        /*!< PWR Pull-Up Control Register of port D,           Address offset: 0x38 */
510   __IO uint32_t PDCRD;        /*!< PWR Pull-Down Control Register of port D,         Address offset: 0x3C */
511   __IO uint32_t PUCRE;        /*!< PWR Pull-Up Control Register of port E,           Address offset: 0x40 */
512   __IO uint32_t PDCRE;        /*!< PWR Pull-Down Control Register of port E,         Address offset: 0x44 */
513   __IO uint32_t PUCRF;        /*!< PWR Pull-Up Control Register of port F,           Address offset: 0x48 */
514   __IO uint32_t PDCRF;        /*!< PWR Pull-Down Control Register of port F,         Address offset: 0x4C */
515 } PWR_TypeDef;
516 
517 /**
518   * @brief Reset and Clock Control
519   */
520 
521 typedef struct
522 {
523   __IO uint32_t CR;             /*!< RCC Clock Sources Control Register,                                     Address offset: 0x00 */
524   __IO uint32_t ICSCR;          /*!< RCC Internal Clock Sources Calibration Register,                        Address offset: 0x04 */
525   __IO uint32_t CFGR;           /*!< RCC Regulated Domain Clocks Configuration Register,                     Address offset: 0x08 */
526   __IO uint32_t PLLCFGR;        /*!< RCC system PLL configuration register,                                  Address offset: 0x0C */
527        uint32_t RESERVED0[2];   /*!< Reserved,                                                               Address offset: 0x10 -- 0x14 */
528   __IO uint32_t CIER;           /*!< RCC Clock Interrupt Enable Register,                                    Address offset: 0x18 */
529   __IO uint32_t CIFR;           /*!< RCC Clock Interrupt Flag Register,                                      Address offset: 0x1C */
530   __IO uint32_t CICR;           /*!< RCC Clock Interrupt Clear Register,                                     Address offset: 0x20 */
531        uint32_t RESERVED1;      /*!< Reserved,                                                               Address offset: 0x24 */
532   __IO uint32_t AHBRSTR;        /*!< RCC AHB peripheral reset register,                                      Address offset: 0x28 */
533   __IO uint32_t IOPRSTR;        /*!< RCC AHB2 peripheral reset register,                                     Address offset: 0x2C */
534        uint32_t RESERVED2[2];   /*!< Reserved,                                                               Address offset: 0x30 -- 0x34 */
535   __IO uint32_t APBRSTR1;       /*!< RCC APB1 peripheral reset register,                                     Address offset: 0x38 */
536        uint32_t RESERVED3;      /*!< Reserved,                                                               Address offset: 0x3C */
537   __IO uint32_t APBRSTR2;       /*!< RCC APB2 peripheral reset register,                                     Address offset: 0x40 */
538        uint32_t RESERVED4;      /*!< Reserved,                                                               Address offset: 0x44 */
539   __IO uint32_t AHBENR;         /*!< RCC AHB peripheral clocks enable register,                              Address offset: 0x48 */
540   __IO uint32_t IOPENR;         /*!< RCC IO port enable register,                                            Address offset: 0x4C */
541   __IO uint32_t DBGCFGR;        /*!< RCC DBGCFGR control register,                                           Address offset: 0x50 */
542        uint32_t RESERVED5;      /*!< Reserved,                                                               Address offset: 0x54 */
543   __IO uint32_t APBENR1;        /*!< RCC APB1 peripherals clock enable register,                             Address offset: 0x58 */
544        uint32_t RESERVED6;      /*!< Reserved,                                                               Address offset: 0x5C */
545   __IO uint32_t APBENR2;        /*!< RCC APB2 peripherals clock enable register,                             Address offset: 0x60 */
546        uint32_t RESERVED7;      /*!< Reserved,                                                               Address offset: 0x64 */
547   __IO uint32_t AHBSMENR;       /*!< RCC AHB peripheral clocks enable in sleep mode register,                Address offset: 0x68 */
548   __IO uint32_t IOPSMENR;       /*!< RCC IO port peripheral clocks enable in sleep mode register,            Address offset: 0x6C */
549        uint32_t RESERVED8[2];   /*!< Reserved,                                                               Address offset: 0x70 -- 0x74 */
550   __IO uint32_t APBSMENR1;      /*!< RCC APB1 peripheral clocks enable in sleep mode register,               Address offset: 0x78 */
551        uint32_t RESERVED9;      /*!< Reserved,                                                               Address offset: 0x7C */
552   __IO uint32_t APBSMENR2;      /*!< RCC APB2 peripheral clocks enable in sleep mode register,               Address offset: 0x80 */
553        uint32_t RESERVED10;     /*!< Reserved,                                                               Address offset: 0x84 */
554   __IO uint32_t CCIPR;          /*!< RCC Peripherals Independent Clocks Configuration Register,              Address offset: 0x88 */
555        uint32_t RESERVED11;     /*!< Reserved,                                                               Address offset: 0x8C */
556   __IO uint32_t BDCR;           /*!< RCC backup domain control register,                                     Address offset: 0x90 */
557   __IO uint32_t CSR;            /*!< RCC clock control & status register,                                    Address offset: 0x94 */
558   __IO uint32_t CRRCR;          /*!< RCC clock recovery RC register,                                         Address offset: 0x98 */
559 } RCC_TypeDef;
560 
561 /**
562   * @brief RNG
563   */
564 
565 typedef struct
566 {
567   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
568   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
569   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
570   uint32_t RESERVED;
571   __IO uint32_t HTCR;  /*!< RNG health test configuration register, Address offset: 0x10 */
572 } RNG_TypeDef;
573 
574 /**
575   * @brief Real-Time Clock
576   */
577 typedef struct
578 {
579  __IO uint32_t TR;          /*!< RTC time register,                              Address offset: 0x00 */
580  __IO uint32_t DR;          /*!< RTC date register,                              Address offset: 0x04 */
581  __IO uint32_t SSR;         /*!< RTC sub second register,                        Address offset: 0x08 */
582  __IO uint32_t ICSR;        /*!< RTC initialization control and status register, Address offset: 0x0C */
583  __IO uint32_t PRER;        /*!< RTC prescaler register,                         Address offset: 0x10 */
584  __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                      Address offset: 0x14 */
585  __IO uint32_t CR;          /*!< RTC control register,                           Address offset: 0x18 */
586       uint32_t RESERVED0[2];/*!< Reserved,                                       Address offset: 0x20 */
587  __IO uint32_t WPR;         /*!< RTC write protection register,                  Address offset: 0x24 */
588  __IO uint32_t CALR;        /*!< RTC calibration register,                       Address offset: 0x28 */
589  __IO uint32_t SHIFTR;      /*!< RTC shift control register,                     Address offset: 0x2C */
590  __IO uint32_t TSTR;        /*!< RTC time stamp time register,                   Address offset: 0x30 */
591  __IO uint32_t TSDR;        /*!< RTC time stamp date register,                   Address offset: 0x34 */
592  __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,             Address offset: 0x38 */
593       uint32_t RESERVED1;   /*!< Reserved,                                       Address offset: 0x3C */
594  __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                           Address offset: 0x40 */
595  __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                Address offset: 0x44 */
596  __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                           Address offset: 0x48 */
597  __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                Address offset: 0x4C */
598  __IO uint32_t SR;          /*!< RTC Status register,                            Address offset: 0x50 */
599  __IO uint32_t MISR;        /*!< RTC masked interrupt status register,           Address offset: 0x54 */
600       uint32_t RESERVED2;   /*!< Reserved,                                       Address offset: 0x3C */
601  __IO uint32_t SCR;         /*!< RTC status Clear register,                      Address offset: 0x5C */
602       uint32_t RESERVED3[4];/*!< Reserved,                                       Address offset: 0x58 */
603  __IO uint32_t ALRABINR;    /*!< RTC alarm A binary mode register,               Address offset: 0x70 */
604  __IO uint32_t ALRBBINR;    /*!< RTC alarm B binary mode register,               Address offset: 0x74 */
605 } RTC_TypeDef;
606 
607 /**
608   * @brief Tamper and backup registers
609   */
610 typedef struct
611 {
612   __IO uint32_t CR1;            /*!< TAMP configuration register 1,            Address offset: 0x00 */
613   __IO uint32_t CR2;            /*!< TAMP configuration register 2,            Address offset: 0x04 */
614   __IO uint32_t CR3;            /*!< TAMP configuration register 3,            Address offset: 0x08 */
615   __IO uint32_t FLTCR;          /*!< TAMP filter control register,             Address offset: 0x0C */
616        uint32_t RESERVED1[7];   /*!< Reserved,                                 Address offset: 0x28 */
617   __IO uint32_t IER;            /*!< TAMP interrupt enable register,           Address offset: 0x2C */
618   __IO uint32_t SR;             /*!< TAMP status register,                     Address offset: 0x30 */
619   __IO uint32_t MISR;           /*!< TAMP masked interrupt status register,    Address offset: 0x34 */
620        uint32_t RESERVED2;      /*!< Reserved,                                 Address offset: 0x38 */
621   __IO uint32_t SCR;            /*!< TAMP status clear register,               Address offset: 0x3C */
622        uint32_t RESERVED4[48];  /*!< Reserved,                                 Address offset: 0x40 -- 0xFC */
623   __IO uint32_t BKP0R;          /*!< TAMP backup register 0,                   Address offset: 0x100 */
624   __IO uint32_t BKP1R;          /*!< TAMP backup register 1,                   Address offset: 0x104 */
625   __IO uint32_t BKP2R;          /*!< TAMP backup register 2,                   Address offset: 0x108 */
626   __IO uint32_t BKP3R;          /*!< TAMP backup register 3,                   Address offset: 0x10C */
627   __IO uint32_t BKP4R;          /*!< TAMP backup register 4,                   Address offset: 0x110 */
628   __IO uint32_t BKP5R;          /*!< TAMP backup register 5,                   Address offset: 0x114 */
629   __IO uint32_t BKP6R;          /*!< TAMP backup register 6,                   Address offset: 0x118 */
630   __IO uint32_t BKP7R;          /*!< TAMP backup register 7,                   Address offset: 0x11C */
631   __IO uint32_t BKP8R;          /*!< TAMP backup register 8,                   Address offset: 0x120 */
632 } TAMP_TypeDef;
633 
634 /**
635   * @brief System configuration controller
636   */
637 
638 typedef struct
639 {
640   __IO uint32_t CFGR1;          /*!< SYSCFG Control register,                      Address offset: 0x00 */
641        uint32_t RESERVED0[5];   /*!< Reserved                                               0x04 --0x14 */
642        uint32_t CFGR2;          /*!< SYSCFG Class B register,                      Address offset: 0x18 */
643   __IO uint32_t SCSR;           /*!< SYSCFG Backup Sram Erase Register,            Address offset: 0x1C */
644   __IO uint32_t SKR;            /*!< SYSCFG Backup Sram Key Register,              Address offset: 0x20 */
645   __IO uint32_t TSCCR;          /*!< SYSCFG TSC Comp Register,                     Address offset: 0x24 */
646        uint32_t RESERVED1[22];  /*!< Reserved                                               0x28 --0x2C */
647   __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register,        Address offset: 0x80 */
648 } SYSCFG_TypeDef;
649 
650 /**
651   * @brief Serial Peripheral Interface
652   */
653 
654 typedef struct
655 {
656   __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
657   __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
658   __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
659   __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
660   __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
661   __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
662   __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
663   __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
664   __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
665 } SPI_TypeDef;
666 
667 /**
668   * @brief TIM
669   */
670 
671 typedef struct
672 {
673   __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
674   __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
675   __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
676   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
677   __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
678   __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
679   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
680   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
681   __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
682   __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
683   __IO uint32_t PSC;         /*!< TIM prescaler register,                   Address offset: 0x28 */
684   __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
685   __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
686   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
687   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
688   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
689   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
690   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
691   __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
692   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
693   __IO uint32_t OR1;         /*!< TIM option register,                      Address offset: 0x50 */
694   __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
695   __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
696   __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
697   __IO uint32_t AF1;         /*!< TIM alternate function register 1,        Address offset: 0x60 */
698   __IO uint32_t AF2;         /*!< TIM alternate function register 2,        Address offset: 0x64 */
699   __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */
700 } TIM_TypeDef;
701 
702 /**
703   * @brief Touch Sensing Controller (TSC)
704   */
705 
706 typedef struct
707 {
708   __IO uint32_t CR;          /*!< TSC control register,                                     Address offset: 0x00 */
709   __IO uint32_t IER;         /*!< TSC interrupt enable register,                            Address offset: 0x04 */
710   __IO uint32_t ICR;         /*!< TSC interrupt clear register,                             Address offset: 0x08 */
711   __IO uint32_t ISR;         /*!< TSC interrupt status register,                            Address offset: 0x0C */
712   __IO uint32_t IOHCR;       /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
713   uint32_t      RESERVED1;   /*!< Reserved,                                                 Address offset: 0x14 */
714   __IO uint32_t IOASCR;      /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
715   uint32_t      RESERVED2;   /*!< Reserved,                                                 Address offset: 0x1C */
716   __IO uint32_t IOSCR;       /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
717   uint32_t      RESERVED3;   /*!< Reserved,                                                 Address offset: 0x24 */
718   __IO uint32_t IOCCR;       /*!< TSC I/O channel control register,                         Address offset: 0x28 */
719   uint32_t      RESERVED4;   /*!< Reserved,                                                 Address offset: 0x2C */
720   __IO uint32_t IOGCSR;      /*!< TSC I/O group control status register,                    Address offset: 0x30 */
721   __IO uint32_t IOGXCR[7];   /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */
722 } TSC_TypeDef;
723 
724 /**
725   * @brief Universal Synchronous Asynchronous Receiver Transmitter
726   */
727 
728 typedef struct
729 {
730   __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
731   __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
732   __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
733   __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
734   __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
735   __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
736   __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
737   __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
738   __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
739   __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
740   __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
741   __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */
742 } USART_TypeDef;
743 
744 /**
745   * @brief VREFBUF
746   */
747 typedef struct
748 {
749   __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
750   __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
751 } VREFBUF_TypeDef;
752 
753 /**
754   * @brief Window WATCHDOG
755   */
756 
757 typedef struct
758 {
759   __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
760   __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
761   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
762 } WWDG_TypeDef;
763 
764 /**
765   * @brief Universal Serial Bus Full Speed Dual Role Device
766   */
767 typedef struct
768 {
769   __IO uint32_t CHEP0R;          /*!< USB Channel/Endpoint 0 register,      Address offset: 0x00 */
770   __IO uint32_t CHEP1R;          /*!< USB Channel/Endpoint 1 register,      Address offset: 0x04 */
771   __IO uint32_t CHEP2R;          /*!< USB Channel/Endpoint 2 register,      Address offset: 0x08 */
772   __IO uint32_t CHEP3R;          /*!< USB Channel/Endpoint 3 register,      Address offset: 0x0C */
773   __IO uint32_t CHEP4R;          /*!< USB Channel/Endpoint 4 register,      Address offset: 0x10 */
774   __IO uint32_t CHEP5R;          /*!< USB Channel/Endpoint 5 register,      Address offset: 0x14 */
775   __IO uint32_t CHEP6R;          /*!< USB Channel/Endpoint 6 register,      Address offset: 0x18 */
776   __IO uint32_t CHEP7R;          /*!< USB Channel/Endpoint 7 register,      Address offset: 0x1C */
777   __IO uint32_t RESERVED0[8];    /*!< Reserved,                                                  */
778   __IO uint32_t CNTR;            /*!< Control register,                     Address offset: 0x40 */
779   __IO uint32_t ISTR;            /*!< Interrupt status register,            Address offset: 0x44 */
780   __IO uint32_t FNR;             /*!< Frame number register,                Address offset: 0x48 */
781   __IO uint32_t DADDR;           /*!< Device address register,              Address offset: 0x4C */
782   __IO uint32_t RESERVED1;       /*!< Reserved */
783   __IO uint32_t LPMCSR;          /*!< LPM Control and Status register,      Address offset: 0x54 */
784   __IO uint32_t BCDR;            /*!< Battery Charging detector register,   Address offset: 0x58 */
785 } USB_DRD_TypeDef;
786 
787 /**
788   * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table
789   */
790 typedef struct
791 {
792   __IO uint32_t TXBD;             /*!<Transmission buffer address*/
793   __IO uint32_t RXBD;             /*!<Reception buffer address */
794 } USB_DRD_PMABuffDescTypeDef;
795 
796 /*!< USB PMA SIZE */
797 #define USB_DRD_PMA_SIZE        (1024U)         /*!< USB PMA Size 1Kbyte */
798 
799 /**
800   * @}
801   */
802 
803 /* =========================================================================================================================== */
804 /* ================                          Device Specific Peripheral Address Map                           ================ */
805 /* =========================================================================================================================== */
806 
807 /*!< Device Electronic Signature */
808 #define PACKAGE_BASE          (0x1FFF6D00UL)        /*!< Package data register base address     */
809 #define UID_BASE              (0x1FFF6E50UL)        /*!< Unique device ID register base address */
810 #define FLASHSIZE_BASE        (0x1FFF6EA0UL)        /*!< Flash size data register base address  */
811 
812 /*!< Bootloader Firmware */
813 /************ Bootloader Exit Secure Memory Firmware *************/
814 #define BL_EXIT_SEC_MEM_BASE    (0x1FFF6000UL)
815 
816 /**
817   * @}
818   */
819 
820 /** @addtogroup STM32U0xx_Peripheral_memory_map
821   * @{
822   */
823 
824 #define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address */
825 #define SRAM1_BASE            (0x20000000UL)              /*!< SRAM1 base address */
826 #define SRAM1_SIZE_MAX        (0x00008000UL)              /*!< maximum SRAM1 size (up to 32 KBytes) */
827 #define BKPSRAM2_BASE         (SRAM1_BASE + 0x00008000UL) /*!< SRAM2 BKP(up to 8 KB) base address */
828 #define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address */
829 #define IOPORT_BASE           (0x50000000UL)              /*!< IOPORT base address */
830 
831 #define FLASH_SIZE_DEFAULT    0x40000U                    /*!< Flash memory default size */
832 
833 #define FLASH_SIZE            ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? FLASH_SIZE_DEFAULT : \
834                                ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? FLASH_SIZE_DEFAULT : \
835                                 (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U)))
836 
837 /* Internal Flash OTP Area */
838 #define FLASH_OTP_BASE          (0x1FFF6800UL)            /*!< FLASH OTP (one-time programmable) base address */
839 #define FLASH_OTP_SIZE          (0x400U)                  /*!< 1024 bytes OTP (one-time programmable)         */
840 
841 /* Flash system Area */
842 #define FLASH_SYSTEM_BASE_NS    (0x1FFF0000UL)            /*!< FLASH System non-secure base address  */
843 #define FLASH_SYSTEM_SIZE       (0x6800U)                 /*!< 26 Kbytes system Flash */
844 
845 /* Peripheral memory map */
846 #define APBPERIPH_BASE        PERIPH_BASE
847 #define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
848 
849 /*!< APB peripherals */
850 #define TIM2_BASE             (APBPERIPH_BASE + 0x0000UL)
851 #define TIM3_BASE             (APBPERIPH_BASE + 0x0400UL)
852 #define TIM6_BASE             (APBPERIPH_BASE + 0x1000UL)
853 #define TIM7_BASE             (APBPERIPH_BASE + 0x1400UL)
854 #define LCD_BASE              (APBPERIPH_BASE + 0x2400UL)
855 #define RTC_BASE              (APBPERIPH_BASE + 0x2800UL)
856 #define WWDG_BASE             (APBPERIPH_BASE + 0x2C00UL)
857 #define IWDG_BASE             (APBPERIPH_BASE + 0x3000UL)
858 #define SPI2_BASE             (APBPERIPH_BASE + 0x3800UL)
859 #define SPI3_BASE             (APBPERIPH_BASE + 0x3C00UL)
860 #define USART2_BASE           (APBPERIPH_BASE + 0x4400UL)
861 #define USART3_BASE           (APBPERIPH_BASE + 0x4800UL)
862 #define USART4_BASE           (APBPERIPH_BASE + 0x4C00UL)
863 #define I2C1_BASE             (APBPERIPH_BASE + 0x5400UL)
864 #define I2C2_BASE             (APBPERIPH_BASE + 0x5800UL)
865 #define USB_DRD_BASE          (APBPERIPH_BASE + 0x5C00UL)   /*USB FS*/
866 #define CRS_BASE              (APBPERIPH_BASE + 0x6C00UL)
867 #define PWR_BASE              (APBPERIPH_BASE + 0x7000UL)
868 #define DAC1_BASE             (APBPERIPH_BASE + 0x7400UL)
869 #define OPAMP1_BASE           (APBPERIPH_BASE + 0x7800UL)
870 #define LPTIM1_BASE           (APBPERIPH_BASE + 0x7C00UL)
871 #define LPUART1_BASE          (APBPERIPH_BASE + 0x8000UL)
872 #define LPUART2_BASE          (APBPERIPH_BASE + 0x8400UL)
873 #define I2C3_BASE             (APBPERIPH_BASE + 0x8800UL)
874 #define LPUART3_BASE          (APBPERIPH_BASE + 0x8C00UL)
875 #define LPTIM3_BASE           (APBPERIPH_BASE + 0x9000UL)
876 #define LPTIM2_BASE           (APBPERIPH_BASE + 0x9400UL)
877 #define USB_DRD_PMAADDR       (APBPERIPH_BASE + 0x9800UL)   /*USB RAM1*/
878 #define I2C4_BASE             (APBPERIPH_BASE + 0xA000UL)
879 #define TAMP_BASE             (APBPERIPH_BASE + 0xB000UL)   /*TAMPER (+ BKP Regs)*/
880 #define SYSCFG_BASE           (APBPERIPH_BASE + 0x10000UL)  /*SYSCFG IF + COMP*/
881 #define VREFBUF_BASE          (SYSCFG_BASE + 0x0030UL)
882 #define COMP1_BASE            (SYSCFG_BASE + 0x0200UL)
883 #define COMP2_BASE            (SYSCFG_BASE + 0x0204UL)
884 #define ADC1_BASE             (APBPERIPH_BASE + 0x12400UL)
885 #define ADC1_COMMON_BASE      (APBPERIPH_BASE + 0x12708UL)
886 #define TIM1_BASE             (APBPERIPH_BASE + 0x12C00UL)
887 #define SPI1_BASE             (APBPERIPH_BASE + 0x13000UL)
888 #define USART1_BASE           (APBPERIPH_BASE + 0x13800UL)
889 #define TIM15_BASE            (APBPERIPH_BASE + 0x14000UL)
890 #define TIM16_BASE            (APBPERIPH_BASE + 0x14400UL)
891 #define DBGMCU_BASE           (APBPERIPH_BASE + 0x15800UL)
892 
893 /*!< AHB peripherals */
894 #define DMA1_BASE             (AHBPERIPH_BASE + 0x0000UL)
895 
896 #define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008UL)
897 #define DMA1_Channel2_BASE    (DMA1_BASE + 0x001CUL)
898 #define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030UL)
899 #define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044UL)
900 #define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058UL)
901 #define DMA1_Channel6_BASE    (DMA1_BASE + 0x006CUL)
902 #define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080UL)
903 
904 #define DMA2_BASE             (AHBPERIPH_BASE + 0x0400UL)
905 
906 #define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008UL)
907 #define DMA2_Channel2_BASE    (DMA2_BASE + 0x001CUL)
908 #define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030UL)
909 #define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044UL)
910 #define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058UL)
911 
912 #define DMAMUX1_BASE           (AHBPERIPH_BASE + 0x0800UL)
913 
914 #define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)
915 #define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)
916 #define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)
917 #define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)
918 #define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)
919 #define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)
920 #define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)
921 #define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)
922 #define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)
923 #define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)
924 #define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)
925 #define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)
926 
927 #define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)
928 #define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)
929 #define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)
930 #define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)
931 
932 #define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)
933 #define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)
934 #define DMAMUX1_IdRegisters_BASE        (DMAMUX1_BASE + 0x000003EC)
935 
936 #define RCC_BASE              (AHBPERIPH_BASE + 0x1000UL)
937 #define EXTI_BASE             (AHBPERIPH_BASE + 0x1800UL) /* AIEC */
938 #define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000UL)
939 #define CRC_BASE              (AHBPERIPH_BASE + 0x3000UL)
940 #define TSC_BASE              (AHBPERIPH_BASE + 0x4000UL)
941 #define RNG_BASE              (AHBPERIPH_BASE + 0x5000UL)
942 #define AES_BASE              (AHBPERIPH_BASE + 0x6000UL)
943 
944 /*!< IOPORT (GPIO) memory map */
945 #define GPIOA_BASE            (IOPORT_BASE + 0x0000UL)
946 #define GPIOB_BASE            (IOPORT_BASE + 0x0400UL)
947 #define GPIOC_BASE            (IOPORT_BASE + 0x0800UL)
948 #define GPIOD_BASE            (IOPORT_BASE + 0x0C00UL)
949 #define GPIOE_BASE            (IOPORT_BASE + 0x1000UL)
950 #define GPIOF_BASE            (IOPORT_BASE + 0x1400UL)
951 
952 /**
953   * @}
954   */
955 
956 /** @addtogroup Peripheral_declaration
957   * @{
958   */
959 #define AES                 ((AES_TypeDef *) AES_BASE)
960 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
961 #define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
962 #define COMP1               ((COMP_TypeDef *) COMP1_BASE)
963 #define COMP2               ((COMP_TypeDef *) COMP2_BASE)
964 #define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP1_BASE)
965 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
966 #define CRS                 ((CRS_TypeDef *) CRS_BASE)
967 #define DAC1                ((DAC_TypeDef *) DAC1_BASE)
968 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
969 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
970 
971 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
972 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
973 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
974 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
975 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
976 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
977 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
978 
979 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
980 
981 #define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
982 #define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
983 #define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
984 #define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
985 #define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
986 
987 #define DMAMUX1             ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
988 
989 #define DMAMUX1_Channel0    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
990 #define DMAMUX1_Channel1    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
991 #define DMAMUX1_Channel2    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
992 #define DMAMUX1_Channel3    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
993 #define DMAMUX1_Channel4    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
994 #define DMAMUX1_Channel5    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
995 #define DMAMUX1_Channel6    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
996 
997 #define DMAMUX1_Channel7    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
998 #define DMAMUX1_Channel8    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
999 #define DMAMUX1_Channel9    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
1000 #define DMAMUX1_Channel10   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
1001 #define DMAMUX1_Channel11   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
1002 
1003 #define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
1004 #define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
1005 #define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
1006 #define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
1007 
1008 #define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
1009 #define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
1010 
1011 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
1012 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
1013 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
1014 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
1015 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
1016 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
1017 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
1018 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
1019 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
1020 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
1021 #define I2C3                ((I2C_TypeDef *) I2C3_BASE)
1022 #define I2C4                ((I2C_TypeDef *) I2C4_BASE)
1023 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
1024 #define LCD                 ((LCD_TypeDef *) LCD_BASE)
1025 #define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
1026 #define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
1027 #define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)
1028 #define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
1029 #define LPUART2             ((USART_TypeDef *) LPUART2_BASE)
1030 #define LPUART3             ((USART_TypeDef *) LPUART3_BASE)
1031 #define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
1032 #define OPAMP1_COMMON       ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
1033 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
1034 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
1035 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
1036 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
1037 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
1038 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
1039 #define SPI3                ((SPI_TypeDef *) SPI3_BASE)
1040 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
1041 #define TAMP                ((TAMP_TypeDef *) TAMP_BASE)
1042 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
1043 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
1044 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
1045 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
1046 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
1047 #define TIM15               ((TIM_TypeDef *) TIM15_BASE)
1048 #define TIM16               ((TIM_TypeDef *) TIM16_BASE)
1049 #define TSC                 ((TSC_TypeDef *) TSC_BASE)
1050 #define USART1              ((USART_TypeDef *) USART1_BASE)
1051 #define USART2              ((USART_TypeDef *) USART2_BASE)
1052 #define USART3              ((USART_TypeDef *) USART3_BASE)
1053 #define USART4              ((USART_TypeDef *) USART4_BASE)
1054 #define USB_DRD_FS          ((USB_DRD_TypeDef *) USB_DRD_BASE)
1055 #define USB_DRD_PMA_BUFF    ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR)
1056 #define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)
1057 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
1058 
1059 /**
1060   * @}
1061   */
1062 
1063 /** @addtogroup Exported_constants
1064   * @{
1065   */
1066 
1067   /** @addtogroup Hardware_Constant_Definition
1068     * @{
1069     */
1070 #define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
1071 
1072   /**
1073     * @}
1074     */
1075 
1076   /** @addtogroup Peripheral_Registers_Bits_Definition
1077   * @{
1078   */
1079 
1080 /******************************************************************************/
1081 /*                         Peripheral Registers_Bits_Definition               */
1082 /******************************************************************************/
1083 
1084 /******************************************************************************/
1085 /*                                                                            */
1086 /*                      Analog to Digital Converter (ADC)                     */
1087 /*                                                                            */
1088 /******************************************************************************/
1089 /********************  Bit definition for ADC_ISR register  *******************/
1090 #define ADC_ISR_ADRDY_Pos              (0U)
1091 #define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
1092 #define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
1093 #define ADC_ISR_EOSMP_Pos              (1U)
1094 #define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
1095 #define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
1096 #define ADC_ISR_EOC_Pos                (2U)
1097 #define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
1098 #define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
1099 #define ADC_ISR_EOS_Pos                (3U)
1100 #define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
1101 #define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
1102 #define ADC_ISR_OVR_Pos                (4U)
1103 #define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
1104 #define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
1105 #define ADC_ISR_AWD1_Pos               (7U)
1106 #define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
1107 #define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
1108 #define ADC_ISR_AWD2_Pos               (8U)
1109 #define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
1110 #define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
1111 #define ADC_ISR_AWD3_Pos               (9U)
1112 #define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
1113 #define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
1114 #define ADC_ISR_EOCAL_Pos              (11U)
1115 #define ADC_ISR_EOCAL_Msk              (0x1UL << ADC_ISR_EOCAL_Pos)            /*!< 0x00000800 */
1116 #define ADC_ISR_EOCAL                  ADC_ISR_EOCAL_Msk                       /*!< ADC end of calibration flag */
1117 #define ADC_ISR_CCRDY_Pos              (13U)
1118 #define ADC_ISR_CCRDY_Msk              (0x1UL << ADC_ISR_CCRDY_Pos)            /*!< 0x00002000 */
1119 #define ADC_ISR_CCRDY                  ADC_ISR_CCRDY_Msk                       /*!< ADC channel configuration ready flag */
1120 
1121 /* Legacy defines */
1122 #define ADC_ISR_EOSEQ           (ADC_ISR_EOS)
1123 
1124 /********************  Bit definition for ADC_IER register  *******************/
1125 #define ADC_IER_ADRDYIE_Pos            (0U)
1126 #define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
1127 #define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
1128 #define ADC_IER_EOSMPIE_Pos            (1U)
1129 #define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
1130 #define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
1131 #define ADC_IER_EOCIE_Pos              (2U)
1132 #define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
1133 #define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
1134 #define ADC_IER_EOSIE_Pos              (3U)
1135 #define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
1136 #define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
1137 #define ADC_IER_OVRIE_Pos              (4U)
1138 #define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
1139 #define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
1140 #define ADC_IER_AWD1IE_Pos             (7U)
1141 #define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
1142 #define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
1143 #define ADC_IER_AWD2IE_Pos             (8U)
1144 #define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
1145 #define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
1146 #define ADC_IER_AWD3IE_Pos             (9U)
1147 #define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
1148 #define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
1149 #define ADC_IER_EOCALIE_Pos            (11U)
1150 #define ADC_IER_EOCALIE_Msk            (0x1UL << ADC_IER_EOCALIE_Pos)          /*!< 0x00000800 */
1151 #define ADC_IER_EOCALIE                ADC_IER_EOCALIE_Msk                     /*!< ADC end of calibration interrupt */
1152 #define ADC_IER_CCRDYIE_Pos            (13U)
1153 #define ADC_IER_CCRDYIE_Msk            (0x1UL << ADC_IER_CCRDYIE_Pos)          /*!< 0x00002000 */
1154 #define ADC_IER_CCRDYIE                ADC_IER_CCRDYIE_Msk                     /*!< ADC channel configuration ready interrupt */
1155 
1156 /* Legacy defines */
1157 #define ADC_IER_EOSEQIE           (ADC_IER_EOSIE)
1158 
1159 /********************  Bit definition for ADC_CR register  ********************/
1160 #define ADC_CR_ADEN_Pos                (0U)
1161 #define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
1162 #define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
1163 #define ADC_CR_ADDIS_Pos               (1U)
1164 #define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
1165 #define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
1166 #define ADC_CR_ADSTART_Pos             (2U)
1167 #define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
1168 #define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
1169 #define ADC_CR_ADSTP_Pos               (4U)
1170 #define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
1171 #define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
1172 #define ADC_CR_ADVREGEN_Pos            (28U)
1173 #define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */
1174 #define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
1175 #define ADC_CR_ADCAL_Pos               (31U)
1176 #define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
1177 #define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
1178 
1179 /********************  Bit definition for ADC_CFGR1 register  *****************/
1180 #define ADC_CFGR1_DMAEN_Pos            (0U)
1181 #define ADC_CFGR1_DMAEN_Msk            (0x1UL << ADC_CFGR1_DMAEN_Pos)          /*!< 0x00000001 */
1182 #define ADC_CFGR1_DMAEN                ADC_CFGR1_DMAEN_Msk                     /*!< ADC DMA transfer enable */
1183 #define ADC_CFGR1_DMACFG_Pos           (1U)
1184 #define ADC_CFGR1_DMACFG_Msk           (0x1UL << ADC_CFGR1_DMACFG_Pos)         /*!< 0x00000002 */
1185 #define ADC_CFGR1_DMACFG               ADC_CFGR1_DMACFG_Msk                    /*!< ADC DMA transfer configuration */
1186 
1187 #define ADC_CFGR1_SCANDIR_Pos          (2U)
1188 #define ADC_CFGR1_SCANDIR_Msk          (0x1UL << ADC_CFGR1_SCANDIR_Pos)        /*!< 0x00000004 */
1189 #define ADC_CFGR1_SCANDIR              ADC_CFGR1_SCANDIR_Msk                   /*!< ADC group regular sequencer scan direction */
1190 
1191 #define ADC_CFGR1_RES_Pos              (3U)
1192 #define ADC_CFGR1_RES_Msk              (0x3UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000018 */
1193 #define ADC_CFGR1_RES                  ADC_CFGR1_RES_Msk                       /*!< ADC data resolution */
1194 #define ADC_CFGR1_RES_0                (0x1U << ADC_CFGR1_RES_Pos)             /*!< 0x00000008 */
1195 #define ADC_CFGR1_RES_1                (0x2U << ADC_CFGR1_RES_Pos)             /*!< 0x00000010 */
1196 
1197 #define ADC_CFGR1_ALIGN_Pos            (5U)
1198 #define ADC_CFGR1_ALIGN_Msk            (0x1UL << ADC_CFGR1_ALIGN_Pos)          /*!< 0x00000020 */
1199 #define ADC_CFGR1_ALIGN                ADC_CFGR1_ALIGN_Msk                     /*!< ADC data alignment */
1200 
1201 #define ADC_CFGR1_EXTSEL_Pos           (6U)
1202 #define ADC_CFGR1_EXTSEL_Msk           (0x7UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x000001C0 */
1203 #define ADC_CFGR1_EXTSEL               ADC_CFGR1_EXTSEL_Msk                    /*!< ADC group regular external trigger source */
1204 #define ADC_CFGR1_EXTSEL_0             (0x1UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000040 */
1205 #define ADC_CFGR1_EXTSEL_1             (0x2UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000080 */
1206 #define ADC_CFGR1_EXTSEL_2             (0x4UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000100 */
1207 
1208 #define ADC_CFGR1_EXTEN_Pos            (10U)
1209 #define ADC_CFGR1_EXTEN_Msk            (0x3UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000C00 */
1210 #define ADC_CFGR1_EXTEN                ADC_CFGR1_EXTEN_Msk                     /*!< ADC group regular external trigger polarity */
1211 #define ADC_CFGR1_EXTEN_0              (0x1UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000400 */
1212 #define ADC_CFGR1_EXTEN_1              (0x2UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000800 */
1213 
1214 #define ADC_CFGR1_OVRMOD_Pos           (12U)
1215 #define ADC_CFGR1_OVRMOD_Msk           (0x1UL << ADC_CFGR1_OVRMOD_Pos)         /*!< 0x00001000 */
1216 #define ADC_CFGR1_OVRMOD               ADC_CFGR1_OVRMOD_Msk                    /*!< ADC group regular overrun configuration */
1217 #define ADC_CFGR1_CONT_Pos             (13U)
1218 #define ADC_CFGR1_CONT_Msk             (0x1UL << ADC_CFGR1_CONT_Pos)           /*!< 0x00002000 */
1219 #define ADC_CFGR1_CONT                 ADC_CFGR1_CONT_Msk                      /*!< ADC group regular continuous conversion mode */
1220 #define ADC_CFGR1_WAIT_Pos             (14U)
1221 #define ADC_CFGR1_WAIT_Msk             (0x1UL << ADC_CFGR1_WAIT_Pos)           /*!< 0x00004000 */
1222 #define ADC_CFGR1_WAIT                 ADC_CFGR1_WAIT_Msk                      /*!< ADC low power auto wait */
1223 #define ADC_CFGR1_AUTOFF_Pos           (15U)
1224 #define ADC_CFGR1_AUTOFF_Msk           (0x1UL << ADC_CFGR1_AUTOFF_Pos)         /*!< 0x00008000 */
1225 #define ADC_CFGR1_AUTOFF               ADC_CFGR1_AUTOFF_Msk                    /*!< ADC low power auto power off */
1226 #define ADC_CFGR1_DISCEN_Pos           (16U)
1227 #define ADC_CFGR1_DISCEN_Msk           (0x1UL << ADC_CFGR1_DISCEN_Pos)         /*!< 0x00010000 */
1228 #define ADC_CFGR1_DISCEN               ADC_CFGR1_DISCEN_Msk                    /*!< ADC group regular sequencer discontinuous mode */
1229 #define ADC_CFGR1_CHSELRMOD_Pos        (21U)
1230 #define ADC_CFGR1_CHSELRMOD_Msk        (0x1UL << ADC_CFGR1_CHSELRMOD_Pos)      /*!< 0x00200000 */
1231 #define ADC_CFGR1_CHSELRMOD            ADC_CFGR1_CHSELRMOD_Msk                 /*!< ADC group regular sequencer mode */
1232 
1233 #define ADC_CFGR1_AWD1SGL_Pos          (22U)
1234 #define ADC_CFGR1_AWD1SGL_Msk          (0x1UL << ADC_CFGR1_AWD1SGL_Pos)        /*!< 0x00400000 */
1235 #define ADC_CFGR1_AWD1SGL              ADC_CFGR1_AWD1SGL_Msk                   /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1236 #define ADC_CFGR1_AWD1EN_Pos           (23U)
1237 #define ADC_CFGR1_AWD1EN_Msk           (0x1UL << ADC_CFGR1_AWD1EN_Pos)         /*!< 0x00800000 */
1238 #define ADC_CFGR1_AWD1EN               ADC_CFGR1_AWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1239 
1240 #define ADC_CFGR1_AWD1CH_Pos           (26U)
1241 #define ADC_CFGR1_AWD1CH_Msk           (0x1FUL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x7C000000 */
1242 #define ADC_CFGR1_AWD1CH               ADC_CFGR1_AWD1CH_Msk                    /*!< ADC analog watchdog 1 monitored channel selection */
1243 #define ADC_CFGR1_AWD1CH_0             (0x01UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x04000000 */
1244 #define ADC_CFGR1_AWD1CH_1             (0x02UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x08000000 */
1245 #define ADC_CFGR1_AWD1CH_2             (0x04UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x10000000 */
1246 #define ADC_CFGR1_AWD1CH_3             (0x08UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x20000000 */
1247 #define ADC_CFGR1_AWD1CH_4             (0x10UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x40000000 */
1248 
1249 /* Legacy defines */
1250 #define ADC_CFGR1_AUTDLY          (ADC_CFGR1_WAIT)
1251 
1252 /********************  Bit definition for ADC_CFGR2 register  *****************/
1253 #define ADC_CFGR2_OVSE_Pos             (0U)
1254 #define ADC_CFGR2_OVSE_Msk             (0x1UL << ADC_CFGR2_OVSE_Pos)           /*!< 0x00000001 */
1255 #define ADC_CFGR2_OVSE                 ADC_CFGR2_OVSE_Msk                      /*!< ADC oversampler enable on scope ADC group regular */
1256 
1257 #define ADC_CFGR2_OVSR_Pos             (2U)
1258 #define ADC_CFGR2_OVSR_Msk             (0x7UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x0000001C */
1259 #define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
1260 #define ADC_CFGR2_OVSR_0               (0x1UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000004 */
1261 #define ADC_CFGR2_OVSR_1               (0x2UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000008 */
1262 #define ADC_CFGR2_OVSR_2               (0x4UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000010 */
1263 
1264 #define ADC_CFGR2_OVSS_Pos             (5U)
1265 #define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
1266 #define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
1267 #define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
1268 #define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
1269 #define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
1270 #define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
1271 
1272 #define ADC_CFGR2_TOVS_Pos             (9U)
1273 #define ADC_CFGR2_TOVS_Msk             (0x1UL << ADC_CFGR2_TOVS_Pos)           /*!< 0x00000200 */
1274 #define ADC_CFGR2_TOVS                 ADC_CFGR2_TOVS_Msk                      /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1275 
1276 #define ADC_CFGR2_LFTRIG_Pos           (29U)
1277 #define ADC_CFGR2_LFTRIG_Msk           (0x1UL << ADC_CFGR2_LFTRIG_Pos)         /*!< 0x20000000 */
1278 #define ADC_CFGR2_LFTRIG               ADC_CFGR2_LFTRIG_Msk                    /*!< ADC low frequency trigger mode */
1279 
1280 #define ADC_CFGR2_CKMODE_Pos           (30U)
1281 #define ADC_CFGR2_CKMODE_Msk           (0x3UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0xC0000000 */
1282 #define ADC_CFGR2_CKMODE               ADC_CFGR2_CKMODE_Msk                    /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
1283 #define ADC_CFGR2_CKMODE_1             (0x2UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0x80000000 */
1284 #define ADC_CFGR2_CKMODE_0             (0x1UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0x40000000 */
1285 
1286 /********************  Bit definition for ADC_SMPR register  ******************/
1287 #define ADC_SMPR_SMP1_Pos              (0U)
1288 #define ADC_SMPR_SMP1_Msk              (0x7UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000007 */
1289 #define ADC_SMPR_SMP1                  ADC_SMPR_SMP1_Msk                       /*!< ADC group of channels sampling time 1 */
1290 #define ADC_SMPR_SMP1_0                (0x1UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000001 */
1291 #define ADC_SMPR_SMP1_1                (0x2UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000002 */
1292 #define ADC_SMPR_SMP1_2                (0x4UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000004 */
1293 
1294 #define ADC_SMPR_SMP2_Pos              (4U)
1295 #define ADC_SMPR_SMP2_Msk              (0x7UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000070 */
1296 #define ADC_SMPR_SMP2                  ADC_SMPR_SMP2_Msk                       /*!< ADC group of channels sampling time 2 */
1297 #define ADC_SMPR_SMP2_0                (0x1UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000010 */
1298 #define ADC_SMPR_SMP2_1                (0x2UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000020 */
1299 #define ADC_SMPR_SMP2_2                (0x4UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000040 */
1300 
1301 #define ADC_SMPR_SMPSEL_Pos            (8U)
1302 #define ADC_SMPR_SMPSEL_Msk            (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos)      /*!< 0x07FFFF00 */
1303 #define ADC_SMPR_SMPSEL                ADC_SMPR_SMPSEL_Msk                     /*!< ADC all channels sampling time selection */
1304 #define ADC_SMPR_SMPSEL0_Pos           (8U)
1305 #define ADC_SMPR_SMPSEL0_Msk           (0x1UL << ADC_SMPR_SMPSEL0_Pos)         /*!< 0x00000100 */
1306 #define ADC_SMPR_SMPSEL0               ADC_SMPR_SMPSEL0_Msk                    /*!< ADC channel 0 sampling time selection */
1307 #define ADC_SMPR_SMPSEL1_Pos           (9U)
1308 #define ADC_SMPR_SMPSEL1_Msk           (0x1UL << ADC_SMPR_SMPSEL1_Pos)         /*!< 0x00000200 */
1309 #define ADC_SMPR_SMPSEL1               ADC_SMPR_SMPSEL1_Msk                    /*!< ADC channel 1 sampling time selection */
1310 #define ADC_SMPR_SMPSEL2_Pos           (10U)
1311 #define ADC_SMPR_SMPSEL2_Msk           (0x1UL << ADC_SMPR_SMPSEL2_Pos)         /*!< 0x00000400 */
1312 #define ADC_SMPR_SMPSEL2               ADC_SMPR_SMPSEL2_Msk                    /*!< ADC channel 2 sampling time selection */
1313 #define ADC_SMPR_SMPSEL3_Pos           (11U)
1314 #define ADC_SMPR_SMPSEL3_Msk           (0x1UL << ADC_SMPR_SMPSEL3_Pos)         /*!< 0x00000800 */
1315 #define ADC_SMPR_SMPSEL3               ADC_SMPR_SMPSEL3_Msk                    /*!< ADC channel 3 sampling time selection */
1316 #define ADC_SMPR_SMPSEL4_Pos           (12U)
1317 #define ADC_SMPR_SMPSEL4_Msk           (0x1UL << ADC_SMPR_SMPSEL4_Pos)         /*!< 0x00001000 */
1318 #define ADC_SMPR_SMPSEL4               ADC_SMPR_SMPSEL4_Msk                    /*!< ADC channel 4 sampling time selection */
1319 #define ADC_SMPR_SMPSEL5_Pos           (13U)
1320 #define ADC_SMPR_SMPSEL5_Msk           (0x1UL << ADC_SMPR_SMPSEL5_Pos)         /*!< 0x00002000 */
1321 #define ADC_SMPR_SMPSEL5               ADC_SMPR_SMPSEL5_Msk                    /*!< ADC channel 5 sampling time selection */
1322 #define ADC_SMPR_SMPSEL6_Pos           (14U)
1323 #define ADC_SMPR_SMPSEL6_Msk           (0x1UL << ADC_SMPR_SMPSEL6_Pos)         /*!< 0x00004000 */
1324 #define ADC_SMPR_SMPSEL6               ADC_SMPR_SMPSEL6_Msk                    /*!< ADC channel 6 sampling time selection */
1325 #define ADC_SMPR_SMPSEL7_Pos           (15U)
1326 #define ADC_SMPR_SMPSEL7_Msk           (0x1UL << ADC_SMPR_SMPSEL7_Pos)         /*!< 0x00008000 */
1327 #define ADC_SMPR_SMPSEL7               ADC_SMPR_SMPSEL7_Msk                    /*!< ADC channel 7 sampling time selection */
1328 #define ADC_SMPR_SMPSEL8_Pos           (16U)
1329 #define ADC_SMPR_SMPSEL8_Msk           (0x1UL << ADC_SMPR_SMPSEL8_Pos)         /*!< 0x00010000 */
1330 #define ADC_SMPR_SMPSEL8               ADC_SMPR_SMPSEL8_Msk                    /*!< ADC channel 8 sampling time selection */
1331 #define ADC_SMPR_SMPSEL9_Pos           (17U)
1332 #define ADC_SMPR_SMPSEL9_Msk           (0x1UL << ADC_SMPR_SMPSEL9_Pos)         /*!< 0x00020000 */
1333 #define ADC_SMPR_SMPSEL9               ADC_SMPR_SMPSEL9_Msk                    /*!< ADC channel 9 sampling time selection */
1334 #define ADC_SMPR_SMPSEL10_Pos          (18U)
1335 #define ADC_SMPR_SMPSEL10_Msk          (0x1UL << ADC_SMPR_SMPSEL10_Pos)        /*!< 0x00040000 */
1336 #define ADC_SMPR_SMPSEL10              ADC_SMPR_SMPSEL10_Msk                   /*!< ADC channel 10 sampling time selection */
1337 #define ADC_SMPR_SMPSEL11_Pos          (19U)
1338 #define ADC_SMPR_SMPSEL11_Msk          (0x1UL << ADC_SMPR_SMPSEL11_Pos)        /*!< 0x00080000 */
1339 #define ADC_SMPR_SMPSEL11              ADC_SMPR_SMPSEL11_Msk                   /*!< ADC channel 11 sampling time selection */
1340 #define ADC_SMPR_SMPSEL12_Pos          (20U)
1341 #define ADC_SMPR_SMPSEL12_Msk          (0x1UL << ADC_SMPR_SMPSEL12_Pos)        /*!< 0x00100000 */
1342 #define ADC_SMPR_SMPSEL12              ADC_SMPR_SMPSEL12_Msk                   /*!< ADC channel 12 sampling time selection */
1343 #define ADC_SMPR_SMPSEL13_Pos          (21U)
1344 #define ADC_SMPR_SMPSEL13_Msk          (0x1UL << ADC_SMPR_SMPSEL13_Pos)        /*!< 0x00200000 */
1345 #define ADC_SMPR_SMPSEL13              ADC_SMPR_SMPSEL13_Msk                   /*!< ADC channel 13 sampling time selection */
1346 #define ADC_SMPR_SMPSEL14_Pos          (22U)
1347 #define ADC_SMPR_SMPSEL14_Msk          (0x1UL << ADC_SMPR_SMPSEL14_Pos)        /*!< 0x00400000 */
1348 #define ADC_SMPR_SMPSEL14              ADC_SMPR_SMPSEL14_Msk                   /*!< ADC channel 14 sampling time selection */
1349 #define ADC_SMPR_SMPSEL15_Pos          (23U)
1350 #define ADC_SMPR_SMPSEL15_Msk          (0x1UL << ADC_SMPR_SMPSEL15_Pos)        /*!< 0x00800000 */
1351 #define ADC_SMPR_SMPSEL15              ADC_SMPR_SMPSEL15_Msk                   /*!< ADC channel 15 sampling time selection */
1352 #define ADC_SMPR_SMPSEL16_Pos          (24U)
1353 #define ADC_SMPR_SMPSEL16_Msk          (0x1UL << ADC_SMPR_SMPSEL16_Pos)        /*!< 0x01000000 */
1354 #define ADC_SMPR_SMPSEL16              ADC_SMPR_SMPSEL16_Msk                   /*!< ADC channel 16 sampling time selection */
1355 #define ADC_SMPR_SMPSEL17_Pos          (25U)
1356 #define ADC_SMPR_SMPSEL17_Msk          (0x1UL << ADC_SMPR_SMPSEL17_Pos)        /*!< 0x02000000 */
1357 #define ADC_SMPR_SMPSEL17              ADC_SMPR_SMPSEL17_Msk                   /*!< ADC channel 17 sampling time selection */
1358 #define ADC_SMPR_SMPSEL18_Pos          (26U)
1359 #define ADC_SMPR_SMPSEL18_Msk          (0x1UL << ADC_SMPR_SMPSEL18_Pos)        /*!< 0x04000000 */
1360 #define ADC_SMPR_SMPSEL18              ADC_SMPR_SMPSEL18_Msk                   /*!< ADC channel 18 sampling time selection */
1361 #define ADC_SMPR_SMPSEL19_Pos          (27U)
1362 #define ADC_SMPR_SMPSEL19_Msk          (0x1UL << ADC_SMPR_SMPSEL19_Pos)        /*!< 0x08000000 */
1363 #define ADC_SMPR_SMPSEL19              ADC_SMPR_SMPSEL19_Msk                   /*!< ADC channel 19 sampling time selection */
1364 
1365 /********************  Bit definition for ADC_AWD1TR register  *******************/
1366 #define ADC_AWD1TR_LT1_Pos             (0U)
1367 #define ADC_AWD1TR_LT1_Msk             (0xFFFUL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000FFF */
1368 #define ADC_AWD1TR_LT1                 ADC_AWD1TR_LT1_Msk                      /*!< ADC analog watchdog 1 threshold low */
1369 #define ADC_AWD1TR_LT1_0               (0x001UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000001 */
1370 #define ADC_AWD1TR_LT1_1               (0x002UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000002 */
1371 #define ADC_AWD1TR_LT1_2               (0x004UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000004 */
1372 #define ADC_AWD1TR_LT1_3               (0x008UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000008 */
1373 #define ADC_AWD1TR_LT1_4               (0x010UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000010 */
1374 #define ADC_AWD1TR_LT1_5               (0x020UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000020 */
1375 #define ADC_AWD1TR_LT1_6               (0x040UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000040 */
1376 #define ADC_AWD1TR_LT1_7               (0x080UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000080 */
1377 #define ADC_AWD1TR_LT1_8               (0x100UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000100 */
1378 #define ADC_AWD1TR_LT1_9               (0x200UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000200 */
1379 #define ADC_AWD1TR_LT1_10              (0x400UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000400 */
1380 #define ADC_AWD1TR_LT1_11              (0x800UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000800 */
1381 
1382 #define ADC_AWD1TR_HT1_Pos             (16U)
1383 #define ADC_AWD1TR_HT1_Msk             (0xFFFUL << ADC_AWD1TR_HT1_Pos)         /*!< 0x0FFF0000 */
1384 #define ADC_AWD1TR_HT1                 ADC_AWD1TR_HT1_Msk                      /*!< ADC Analog watchdog 1 threshold high */
1385 #define ADC_AWD1TR_HT1_0               (0x001UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00010000 */
1386 #define ADC_AWD1TR_HT1_1               (0x002UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00020000 */
1387 #define ADC_AWD1TR_HT1_2               (0x004UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00040000 */
1388 #define ADC_AWD1TR_HT1_3               (0x008UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00080000 */
1389 #define ADC_AWD1TR_HT1_4               (0x010UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00100000 */
1390 #define ADC_AWD1TR_HT1_5               (0x020UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00200000 */
1391 #define ADC_AWD1TR_HT1_6               (0x040UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00400000 */
1392 #define ADC_AWD1TR_HT1_7               (0x080UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00800000 */
1393 #define ADC_AWD1TR_HT1_8               (0x100UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x01000000 */
1394 #define ADC_AWD1TR_HT1_9               (0x200UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x02000000 */
1395 #define ADC_AWD1TR_HT1_10              (0x400UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x04000000 */
1396 #define ADC_AWD1TR_HT1_11              (0x800UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x08000000 */
1397 
1398 /********************  Bit definition for ADC_AWD2TR register  *******************/
1399 #define ADC_AWD2TR_LT2_Pos             (0U)
1400 #define ADC_AWD2TR_LT2_Msk             (0xFFFUL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000FFF */
1401 #define ADC_AWD2TR_LT2                 ADC_AWD2TR_LT2_Msk                      /*!< ADC analog watchdog 2 threshold low */
1402 #define ADC_AWD2TR_LT2_0               (0x001UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000001 */
1403 #define ADC_AWD2TR_LT2_1               (0x002UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000002 */
1404 #define ADC_AWD2TR_LT2_2               (0x004UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000004 */
1405 #define ADC_AWD2TR_LT2_3               (0x008UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000008 */
1406 #define ADC_AWD2TR_LT2_4               (0x010UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000010 */
1407 #define ADC_AWD2TR_LT2_5               (0x020UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000020 */
1408 #define ADC_AWD2TR_LT2_6               (0x040UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000040 */
1409 #define ADC_AWD2TR_LT2_7               (0x080UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000080 */
1410 #define ADC_AWD2TR_LT2_8               (0x100UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000100 */
1411 #define ADC_AWD2TR_LT2_9               (0x200UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000200 */
1412 #define ADC_AWD2TR_LT2_10              (0x400UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000400 */
1413 #define ADC_AWD2TR_LT2_11              (0x800UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000800 */
1414 
1415 #define ADC_AWD2TR_HT2_Pos             (16U)
1416 #define ADC_AWD2TR_HT2_Msk             (0xFFFUL << ADC_AWD2TR_HT2_Pos)         /*!< 0x0FFF0000 */
1417 #define ADC_AWD2TR_HT2                 ADC_AWD2TR_HT2_Msk                      /*!< ADC analog watchdog 2 threshold high */
1418 #define ADC_AWD2TR_HT2_0               (0x001UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00010000 */
1419 #define ADC_AWD2TR_HT2_1               (0x002UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00020000 */
1420 #define ADC_AWD2TR_HT2_2               (0x004UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00040000 */
1421 #define ADC_AWD2TR_HT2_3               (0x008UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00080000 */
1422 #define ADC_AWD2TR_HT2_4               (0x010UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00100000 */
1423 #define ADC_AWD2TR_HT2_5               (0x020UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00200000 */
1424 #define ADC_AWD2TR_HT2_6               (0x040UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00400000 */
1425 #define ADC_AWD2TR_HT2_7               (0x080UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00800000 */
1426 #define ADC_AWD2TR_HT2_8               (0x100UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x01000000 */
1427 #define ADC_AWD2TR_HT2_9               (0x200UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x02000000 */
1428 #define ADC_AWD2TR_HT2_10              (0x400UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x04000000 */
1429 #define ADC_AWD2TR_HT2_11              (0x800UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x08000000 */
1430 
1431 /********************  Bit definition for ADC_CHSELR register  ****************/
1432 #define ADC_CHSELR_CHSEL_Pos           (0U)
1433 #define ADC_CHSELR_CHSEL_Msk           (0x7FFFFFUL << ADC_CHSELR_CHSEL_Pos)    /*!< 0x0007FFFFF */
1434 #define ADC_CHSELR_CHSEL               ADC_CHSELR_CHSEL_Msk                    /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
1435 #define ADC_CHSELR_CHSEL22_Pos         (22U)
1436 #define ADC_CHSELR_CHSEL22_Msk         (0x1UL << ADC_CHSELR_CHSEL22_Pos)       /*!< 0x00400000 */
1437 #define ADC_CHSELR_CHSEL22             ADC_CHSELR_CHSEL22_Msk                  /*!< ADC group regular sequencer channel 22, available when ADC_CFGR1_CHSELRMOD is reset */
1438 #define ADC_CHSELR_CHSEL21_Pos         (21U)
1439 #define ADC_CHSELR_CHSEL21_Msk         (0x1UL << ADC_CHSELR_CHSEL21_Pos)       /*!< 0x00200000 */
1440 #define ADC_CHSELR_CHSEL21             ADC_CHSELR_CHSEL21_Msk                  /*!< ADC group regular sequencer channel 21, available when ADC_CFGR1_CHSELRMOD is reset */
1441 #define ADC_CHSELR_CHSEL20_Pos         (20U)
1442 #define ADC_CHSELR_CHSEL20_Msk         (0x1UL << ADC_CHSELR_CHSEL20_Pos)       /*!< 0x00100000 */
1443 #define ADC_CHSELR_CHSEL20             ADC_CHSELR_CHSEL20_Msk                  /*!< ADC group regular sequencer channel 20, available when ADC_CFGR1_CHSELRMOD is reset */
1444 #define ADC_CHSELR_CHSEL19_Pos         (19U)
1445 #define ADC_CHSELR_CHSEL19_Msk         (0x1UL << ADC_CHSELR_CHSEL19_Pos)       /*!< 0x00080000 */
1446 #define ADC_CHSELR_CHSEL19             ADC_CHSELR_CHSEL19_Msk                  /*!< ADC group regular sequencer channel 19, available when ADC_CFGR1_CHSELRMOD is reset */
1447 #define ADC_CHSELR_CHSEL18_Pos         (18U)
1448 #define ADC_CHSELR_CHSEL18_Msk         (0x1UL << ADC_CHSELR_CHSEL18_Pos)       /*!< 0x00040000 */
1449 #define ADC_CHSELR_CHSEL18             ADC_CHSELR_CHSEL18_Msk                  /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
1450 #define ADC_CHSELR_CHSEL17_Pos         (17U)
1451 #define ADC_CHSELR_CHSEL17_Msk         (0x1UL << ADC_CHSELR_CHSEL17_Pos)       /*!< 0x00020000 */
1452 #define ADC_CHSELR_CHSEL17             ADC_CHSELR_CHSEL17_Msk                  /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
1453 #define ADC_CHSELR_CHSEL16_Pos         (16U)
1454 #define ADC_CHSELR_CHSEL16_Msk         (0x1UL << ADC_CHSELR_CHSEL16_Pos)       /*!< 0x00010000 */
1455 #define ADC_CHSELR_CHSEL16             ADC_CHSELR_CHSEL16_Msk                  /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
1456 #define ADC_CHSELR_CHSEL15_Pos         (15U)
1457 #define ADC_CHSELR_CHSEL15_Msk         (0x1UL << ADC_CHSELR_CHSEL15_Pos)       /*!< 0x00008000 */
1458 #define ADC_CHSELR_CHSEL15             ADC_CHSELR_CHSEL15_Msk                  /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
1459 #define ADC_CHSELR_CHSEL14_Pos         (14U)
1460 #define ADC_CHSELR_CHSEL14_Msk         (0x1UL << ADC_CHSELR_CHSEL14_Pos)       /*!< 0x00004000 */
1461 #define ADC_CHSELR_CHSEL14             ADC_CHSELR_CHSEL14_Msk                  /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
1462 #define ADC_CHSELR_CHSEL13_Pos         (13U)
1463 #define ADC_CHSELR_CHSEL13_Msk         (0x1UL << ADC_CHSELR_CHSEL13_Pos)       /*!< 0x00002000 */
1464 #define ADC_CHSELR_CHSEL13             ADC_CHSELR_CHSEL13_Msk                  /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
1465 #define ADC_CHSELR_CHSEL12_Pos         (12U)
1466 #define ADC_CHSELR_CHSEL12_Msk         (0x1UL << ADC_CHSELR_CHSEL12_Pos)       /*!< 0x00001000 */
1467 #define ADC_CHSELR_CHSEL12             ADC_CHSELR_CHSEL12_Msk                  /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
1468 #define ADC_CHSELR_CHSEL11_Pos         (11U)
1469 #define ADC_CHSELR_CHSEL11_Msk         (0x1UL << ADC_CHSELR_CHSEL11_Pos)       /*!< 0x00000800 */
1470 #define ADC_CHSELR_CHSEL11             ADC_CHSELR_CHSEL11_Msk                  /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
1471 #define ADC_CHSELR_CHSEL10_Pos         (10U)
1472 #define ADC_CHSELR_CHSEL10_Msk         (0x1UL << ADC_CHSELR_CHSEL10_Pos)       /*!< 0x00000400 */
1473 #define ADC_CHSELR_CHSEL10             ADC_CHSELR_CHSEL10_Msk                  /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
1474 #define ADC_CHSELR_CHSEL9_Pos          (9U)
1475 #define ADC_CHSELR_CHSEL9_Msk          (0x1UL << ADC_CHSELR_CHSEL9_Pos)        /*!< 0x00000200 */
1476 #define ADC_CHSELR_CHSEL9              ADC_CHSELR_CHSEL9_Msk                   /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
1477 #define ADC_CHSELR_CHSEL8_Pos          (8U)
1478 #define ADC_CHSELR_CHSEL8_Msk          (0x1UL << ADC_CHSELR_CHSEL8_Pos)        /*!< 0x00000100 */
1479 #define ADC_CHSELR_CHSEL8              ADC_CHSELR_CHSEL8_Msk                   /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
1480 #define ADC_CHSELR_CHSEL7_Pos          (7U)
1481 #define ADC_CHSELR_CHSEL7_Msk          (0x1UL << ADC_CHSELR_CHSEL7_Pos)        /*!< 0x00000080 */
1482 #define ADC_CHSELR_CHSEL7              ADC_CHSELR_CHSEL7_Msk                   /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
1483 #define ADC_CHSELR_CHSEL6_Pos          (6U)
1484 #define ADC_CHSELR_CHSEL6_Msk          (0x1UL << ADC_CHSELR_CHSEL6_Pos)        /*!< 0x00000040 */
1485 #define ADC_CHSELR_CHSEL6              ADC_CHSELR_CHSEL6_Msk                   /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
1486 #define ADC_CHSELR_CHSEL5_Pos          (5U)
1487 #define ADC_CHSELR_CHSEL5_Msk          (0x1UL << ADC_CHSELR_CHSEL5_Pos)        /*!< 0x00000020 */
1488 #define ADC_CHSELR_CHSEL5              ADC_CHSELR_CHSEL5_Msk                   /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
1489 #define ADC_CHSELR_CHSEL4_Pos          (4U)
1490 #define ADC_CHSELR_CHSEL4_Msk          (0x1UL << ADC_CHSELR_CHSEL4_Pos)        /*!< 0x00000010 */
1491 #define ADC_CHSELR_CHSEL4              ADC_CHSELR_CHSEL4_Msk                   /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
1492 #define ADC_CHSELR_CHSEL3_Pos          (3U)
1493 #define ADC_CHSELR_CHSEL3_Msk          (0x1UL << ADC_CHSELR_CHSEL3_Pos)        /*!< 0x00000008 */
1494 #define ADC_CHSELR_CHSEL3              ADC_CHSELR_CHSEL3_Msk                   /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
1495 #define ADC_CHSELR_CHSEL2_Pos          (2U)
1496 #define ADC_CHSELR_CHSEL2_Msk          (0x1UL << ADC_CHSELR_CHSEL2_Pos)        /*!< 0x00000004 */
1497 #define ADC_CHSELR_CHSEL2              ADC_CHSELR_CHSEL2_Msk                   /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
1498 #define ADC_CHSELR_CHSEL1_Pos          (1U)
1499 #define ADC_CHSELR_CHSEL1_Msk          (0x1UL << ADC_CHSELR_CHSEL1_Pos)        /*!< 0x00000002 */
1500 #define ADC_CHSELR_CHSEL1              ADC_CHSELR_CHSEL1_Msk                   /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
1501 #define ADC_CHSELR_CHSEL0_Pos          (0U)
1502 #define ADC_CHSELR_CHSEL0_Msk          (0x1UL << ADC_CHSELR_CHSEL0_Pos)        /*!< 0x00000001 */
1503 #define ADC_CHSELR_CHSEL0              ADC_CHSELR_CHSEL0_Msk                   /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
1504 
1505 #define ADC_CHSELR_SQ_ALL_Pos          (0U)
1506 #define ADC_CHSELR_SQ_ALL_Msk          (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */
1507 #define ADC_CHSELR_SQ_ALL              ADC_CHSELR_SQ_ALL_Msk                   /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */
1508 
1509 #define ADC_CHSELR_SQ8_Pos             (28U)
1510 #define ADC_CHSELR_SQ8_Msk             (0xFUL << ADC_CHSELR_SQ8_Pos)           /*!< 0xF0000000 */
1511 #define ADC_CHSELR_SQ8                 ADC_CHSELR_SQ8_Msk                      /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */
1512 #define ADC_CHSELR_SQ8_0               (0x1UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x10000000 */
1513 #define ADC_CHSELR_SQ8_1               (0x2UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x20000000 */
1514 #define ADC_CHSELR_SQ8_2               (0x4UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x40000000 */
1515 #define ADC_CHSELR_SQ8_3               (0x8UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x80000000 */
1516 
1517 #define ADC_CHSELR_SQ7_Pos             (24U)
1518 #define ADC_CHSELR_SQ7_Msk             (0xFUL << ADC_CHSELR_SQ7_Pos)           /*!< 0x0F000000 */
1519 #define ADC_CHSELR_SQ7                 ADC_CHSELR_SQ7_Msk                      /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */
1520 #define ADC_CHSELR_SQ7_0               (0x1UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x01000000 */
1521 #define ADC_CHSELR_SQ7_1               (0x2UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x02000000 */
1522 #define ADC_CHSELR_SQ7_2               (0x4UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x04000000 */
1523 #define ADC_CHSELR_SQ7_3               (0x8UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x08000000 */
1524 
1525 #define ADC_CHSELR_SQ6_Pos             (20U)
1526 #define ADC_CHSELR_SQ6_Msk             (0xFUL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00F00000 */
1527 #define ADC_CHSELR_SQ6                 ADC_CHSELR_SQ6_Msk                      /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */
1528 #define ADC_CHSELR_SQ6_0               (0x1UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00100000 */
1529 #define ADC_CHSELR_SQ6_1               (0x2UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00200000 */
1530 #define ADC_CHSELR_SQ6_2               (0x4UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00400000 */
1531 #define ADC_CHSELR_SQ6_3               (0x8UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00800000 */
1532 
1533 #define ADC_CHSELR_SQ5_Pos             (16U)
1534 #define ADC_CHSELR_SQ5_Msk             (0xFUL << ADC_CHSELR_SQ5_Pos)           /*!< 0x000F0000 */
1535 #define ADC_CHSELR_SQ5                 ADC_CHSELR_SQ5_Msk                      /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */
1536 #define ADC_CHSELR_SQ5_0               (0x1UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00010000 */
1537 #define ADC_CHSELR_SQ5_1               (0x2UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00020000 */
1538 #define ADC_CHSELR_SQ5_2               (0x4UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00040000 */
1539 #define ADC_CHSELR_SQ5_3               (0x8UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00080000 */
1540 
1541 #define ADC_CHSELR_SQ4_Pos             (12U)
1542 #define ADC_CHSELR_SQ4_Msk             (0xFUL << ADC_CHSELR_SQ4_Pos)           /*!< 0x0000F000 */
1543 #define ADC_CHSELR_SQ4                 ADC_CHSELR_SQ4_Msk                      /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */
1544 #define ADC_CHSELR_SQ4_0               (0x1UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00001000 */
1545 #define ADC_CHSELR_SQ4_1               (0x2UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00002000 */
1546 #define ADC_CHSELR_SQ4_2               (0x4UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00004000 */
1547 #define ADC_CHSELR_SQ4_3               (0x8UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00008000 */
1548 
1549 #define ADC_CHSELR_SQ3_Pos             (8U)
1550 #define ADC_CHSELR_SQ3_Msk             (0xFUL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000F00 */
1551 #define ADC_CHSELR_SQ3                 ADC_CHSELR_SQ3_Msk                      /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */
1552 #define ADC_CHSELR_SQ3_0               (0x1UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000100 */
1553 #define ADC_CHSELR_SQ3_1               (0x2UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000200 */
1554 #define ADC_CHSELR_SQ3_2               (0x4UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000400 */
1555 #define ADC_CHSELR_SQ3_3               (0x8UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000800 */
1556 
1557 #define ADC_CHSELR_SQ2_Pos             (4U)
1558 #define ADC_CHSELR_SQ2_Msk             (0xFUL << ADC_CHSELR_SQ2_Pos)           /*!< 0x000000F0 */
1559 #define ADC_CHSELR_SQ2                 ADC_CHSELR_SQ2_Msk                      /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */
1560 #define ADC_CHSELR_SQ2_0               (0x1UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000010 */
1561 #define ADC_CHSELR_SQ2_1               (0x2UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000020 */
1562 #define ADC_CHSELR_SQ2_2               (0x4UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000040 */
1563 #define ADC_CHSELR_SQ2_3               (0x8UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000080 */
1564 
1565 #define ADC_CHSELR_SQ1_Pos             (0U)
1566 #define ADC_CHSELR_SQ1_Msk             (0xFUL << ADC_CHSELR_SQ1_Pos)           /*!< 0x0000000F */
1567 #define ADC_CHSELR_SQ1                 ADC_CHSELR_SQ1_Msk                      /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */
1568 #define ADC_CHSELR_SQ1_0               (0x1UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000001 */
1569 #define ADC_CHSELR_SQ1_1               (0x2UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000002 */
1570 #define ADC_CHSELR_SQ1_2               (0x4UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000004 */
1571 #define ADC_CHSELR_SQ1_3               (0x8UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000008 */
1572 
1573 /********************  Bit definition for ADC_AWD3TR register  *******************/
1574 #define ADC_AWD3TR_LT3_Pos             (0U)
1575 #define ADC_AWD3TR_LT3_Msk             (0xFFFUL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000FFF */
1576 #define ADC_AWD3TR_LT3                 ADC_AWD3TR_LT3_Msk                      /*!< ADC analog watchdog 3 threshold low */
1577 #define ADC_AWD3TR_LT3_0               (0x001UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000001 */
1578 #define ADC_AWD3TR_LT3_1               (0x002UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000002 */
1579 #define ADC_AWD3TR_LT3_2               (0x004UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000004 */
1580 #define ADC_AWD3TR_LT3_3               (0x008UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000008 */
1581 #define ADC_AWD3TR_LT3_4               (0x010UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000010 */
1582 #define ADC_AWD3TR_LT3_5               (0x020UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000020 */
1583 #define ADC_AWD3TR_LT3_6               (0x040UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000040 */
1584 #define ADC_AWD3TR_LT3_7               (0x080UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000080 */
1585 #define ADC_AWD3TR_LT3_8               (0x100UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000100 */
1586 #define ADC_AWD3TR_LT3_9               (0x200UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000200 */
1587 #define ADC_AWD3TR_LT3_10              (0x400UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000400 */
1588 #define ADC_AWD3TR_LT3_11              (0x800UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000800 */
1589 
1590 #define ADC_AWD3TR_HT3_Pos             (16U)
1591 #define ADC_AWD3TR_HT3_Msk             (0xFFFUL << ADC_AWD3TR_HT3_Pos)         /*!< 0x0FFF0000 */
1592 #define ADC_AWD3TR_HT3                 ADC_AWD3TR_HT3_Msk                      /*!< ADC analog watchdog 3 threshold high */
1593 #define ADC_AWD3TR_HT3_0               (0x001UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00010000 */
1594 #define ADC_AWD3TR_HT3_1               (0x002UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00020000 */
1595 #define ADC_AWD3TR_HT3_2               (0x004UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00040000 */
1596 #define ADC_AWD3TR_HT3_3               (0x008UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00080000 */
1597 #define ADC_AWD3TR_HT3_4               (0x010UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00100000 */
1598 #define ADC_AWD3TR_HT3_5               (0x020UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00200000 */
1599 #define ADC_AWD3TR_HT3_6               (0x040UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00400000 */
1600 #define ADC_AWD3TR_HT3_7               (0x080UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00800000 */
1601 #define ADC_AWD3TR_HT3_8               (0x100UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x01000000 */
1602 #define ADC_AWD3TR_HT3_9               (0x200UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x02000000 */
1603 #define ADC_AWD3TR_HT3_10              (0x400UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x04000000 */
1604 #define ADC_AWD3TR_HT3_11              (0x800UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x08000000 */
1605 
1606 /********************  Bit definition for ADC_DR register  ********************/
1607 #define ADC_DR_DATA_Pos                (0U)
1608 #define ADC_DR_DATA_Msk                (0xFFFFUL << ADC_DR_DATA_Pos)           /*!< 0x0000FFFF */
1609 #define ADC_DR_DATA                    ADC_DR_DATA_Msk                         /*!< ADC group regular conversion data */
1610 #define ADC_DR_DATA_0                  (0x0001UL << ADC_DR_DATA_Pos)           /*!< 0x00000001 */
1611 #define ADC_DR_DATA_1                  (0x0002UL << ADC_DR_DATA_Pos)           /*!< 0x00000002 */
1612 #define ADC_DR_DATA_2                  (0x0004UL << ADC_DR_DATA_Pos)           /*!< 0x00000004 */
1613 #define ADC_DR_DATA_3                  (0x0008UL << ADC_DR_DATA_Pos)           /*!< 0x00000008 */
1614 #define ADC_DR_DATA_4                  (0x0010UL << ADC_DR_DATA_Pos)           /*!< 0x00000010 */
1615 #define ADC_DR_DATA_5                  (0x0020UL << ADC_DR_DATA_Pos)           /*!< 0x00000020 */
1616 #define ADC_DR_DATA_6                  (0x0040UL << ADC_DR_DATA_Pos)           /*!< 0x00000040 */
1617 #define ADC_DR_DATA_7                  (0x0080UL << ADC_DR_DATA_Pos)           /*!< 0x00000080 */
1618 #define ADC_DR_DATA_8                  (0x0100UL << ADC_DR_DATA_Pos)           /*!< 0x00000100 */
1619 #define ADC_DR_DATA_9                  (0x0200UL << ADC_DR_DATA_Pos)           /*!< 0x00000200 */
1620 #define ADC_DR_DATA_10                 (0x0400UL << ADC_DR_DATA_Pos)           /*!< 0x00000400 */
1621 #define ADC_DR_DATA_11                 (0x0800UL << ADC_DR_DATA_Pos)           /*!< 0x00000800 */
1622 #define ADC_DR_DATA_12                 (0x1000UL << ADC_DR_DATA_Pos)           /*!< 0x00001000 */
1623 #define ADC_DR_DATA_13                 (0x2000UL << ADC_DR_DATA_Pos)           /*!< 0x00002000 */
1624 #define ADC_DR_DATA_14                 (0x4000UL << ADC_DR_DATA_Pos)           /*!< 0x00004000 */
1625 #define ADC_DR_DATA_15                 (0x8000UL << ADC_DR_DATA_Pos)           /*!< 0x00008000 */
1626 
1627 /********************  Bit definition for ADC_AWD2CR register  ****************/
1628 #define ADC_AWD2CR_AWD2CH_Pos          (0U)
1629 #define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x0007FFFF */
1630 #define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
1631 #define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
1632 #define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
1633 #define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
1634 #define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
1635 #define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
1636 #define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
1637 #define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
1638 #define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
1639 #define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
1640 #define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
1641 #define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
1642 #define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
1643 #define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
1644 #define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
1645 #define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
1646 #define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
1647 #define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
1648 #define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
1649 #define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */
1650 
1651 /********************  Bit definition for ADC_AWD3CR register  ****************/
1652 #define ADC_AWD3CR_AWD3CH_Pos          (0U)
1653 #define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x0007FFFF */
1654 #define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
1655 #define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
1656 #define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
1657 #define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
1658 #define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
1659 #define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
1660 #define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
1661 #define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
1662 #define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
1663 #define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
1664 #define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
1665 #define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
1666 #define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
1667 #define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
1668 #define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
1669 #define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
1670 #define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
1671 #define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
1672 #define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
1673 #define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */
1674 
1675 /********************  Bit definition for ADC_CALFACT register  ***************/
1676 #define ADC_CALFACT_CALFACT_Pos        (0U)
1677 #define ADC_CALFACT_CALFACT_Msk        (0x7FUL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x0000007F */
1678 #define ADC_CALFACT_CALFACT            ADC_CALFACT_CALFACT_Msk                 /*!< ADC calibration factor in single-ended mode */
1679 #define ADC_CALFACT_CALFACT_0          (0x01UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000001 */
1680 #define ADC_CALFACT_CALFACT_1          (0x02UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000002 */
1681 #define ADC_CALFACT_CALFACT_2          (0x04UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000004 */
1682 #define ADC_CALFACT_CALFACT_3          (0x08UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000008 */
1683 #define ADC_CALFACT_CALFACT_4          (0x10UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000010 */
1684 #define ADC_CALFACT_CALFACT_5          (0x20UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000020 */
1685 #define ADC_CALFACT_CALFACT_6          (0x40UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000040 */
1686 
1687 /*************************  ADC Common registers  *****************************/
1688 /********************  Bit definition for ADC_CCR register  *******************/
1689 #define ADC_CCR_PRESC_Pos              (18U)
1690 #define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */
1691 #define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
1692 #define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */
1693 #define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */
1694 #define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */
1695 #define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */
1696 
1697 #define ADC_CCR_VREFEN_Pos             (22U)
1698 #define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
1699 #define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
1700 #define ADC_CCR_TSEN_Pos               (23U)
1701 #define ADC_CCR_TSEN_Msk               (0x1UL << ADC_CCR_TSEN_Pos)             /*!< 0x00800000 */
1702 #define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
1703 #define ADC_CCR_VBATEN_Pos             (24U)
1704 #define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)           /*!< 0x01000000 */
1705 #define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to VBATEN sensor enable */
1706 
1707 
1708 /******************************************************************************/
1709 /*                                                                            */
1710 /*                       Advanced Encryption Standard (AES)                   */
1711 /*                                                                            */
1712 /******************************************************************************/
1713 /*******************  Bit definition for AES_CR register  *********************/
1714 #define AES_CR_EN_Pos                       (0U)
1715 #define AES_CR_EN_Msk                       (0x1UL << AES_CR_EN_Pos)                /*!< 0x00000001 */
1716 #define AES_CR_EN                           AES_CR_EN_Msk                           /*!< AES Enable */
1717 #define AES_CR_DATATYPE_Pos                 (1U)
1718 #define AES_CR_DATATYPE_Msk                 (0x3UL << AES_CR_DATATYPE_Pos)          /*!< 0x00000006 */
1719 #define AES_CR_DATATYPE                     AES_CR_DATATYPE_Msk                     /*!< Data type selection */
1720 #define AES_CR_DATATYPE_0                   (0x1UL << AES_CR_DATATYPE_Pos)          /*!< 0x00000002 */
1721 #define AES_CR_DATATYPE_1                   (0x2UL << AES_CR_DATATYPE_Pos)          /*!< 0x00000004 */
1722 #define AES_CR_MODE_Pos                     (3U)
1723 #define AES_CR_MODE_Msk                     (0x3UL << AES_CR_MODE_Pos)              /*!< 0x00000018 */
1724 #define AES_CR_MODE                         AES_CR_MODE_Msk                         /*!< AES Mode Of Operation */
1725 #define AES_CR_MODE_0                       (0x1UL << AES_CR_MODE_Pos)              /*!< 0x00000008 */
1726 #define AES_CR_MODE_1                       (0x2UL << AES_CR_MODE_Pos)              /*!< 0x00000010 */
1727 #define AES_CR_CHMOD_Pos                    (5U)
1728 #define AES_CR_CHMOD_Msk                    (0x803UL << AES_CR_CHMOD_Pos)           /*!< 0x00010060 */
1729 #define AES_CR_CHMOD                        AES_CR_CHMOD_Msk                        /*!< AES Chaining Mode */
1730 #define AES_CR_CHMOD_0                      (0x001UL << AES_CR_CHMOD_Pos)           /*!< 0x00000020 */
1731 #define AES_CR_CHMOD_1                      (0x002UL << AES_CR_CHMOD_Pos)           /*!< 0x00000040 */
1732 #define AES_CR_CHMOD_2                      (0x800UL << AES_CR_CHMOD_Pos)           /*!< 0x00010000 */
1733 #define AES_CR_CCFC_Pos                     (7U)
1734 #define AES_CR_CCFC_Msk                     (0x1UL << AES_CR_CCFC_Pos)              /*!< 0x00000080 */
1735 #define AES_CR_CCFC                         AES_CR_CCFC_Msk                         /*!< Computation Complete Flag Clear */
1736 #define AES_CR_ERRC_Pos                     (8U)
1737 #define AES_CR_ERRC_Msk                     (0x1UL << AES_CR_ERRC_Pos)              /*!< 0x00000100 */
1738 #define AES_CR_ERRC                         AES_CR_ERRC_Msk                         /*!< Error Clear */
1739 #define AES_CR_CCFIE_Pos                    (9U)
1740 #define AES_CR_CCFIE_Msk                    (0x1UL << AES_CR_CCFIE_Pos)             /*!< 0x00000200 */
1741 #define AES_CR_CCFIE                        AES_CR_CCFIE_Msk                        /*!< Computation Complete Flag Interrupt Enable */
1742 #define AES_CR_ERRIE_Pos                    (10U)
1743 #define AES_CR_ERRIE_Msk                    (0x1UL << AES_CR_ERRIE_Pos)             /*!< 0x00000400 */
1744 #define AES_CR_ERRIE                         AES_CR_ERRIE_Msk                       /*!< Error Interrupt Enable */
1745 #define AES_CR_DMAINEN_Pos                  (11U)
1746 #define AES_CR_DMAINEN_Msk                  (0x1UL << AES_CR_DMAINEN_Pos)           /*!< 0x00000800 */
1747 #define AES_CR_DMAINEN                      AES_CR_DMAINEN_Msk                      /*!< Enable data input phase DMA management  */
1748 #define AES_CR_DMAOUTEN_Pos                 (12U)
1749 #define AES_CR_DMAOUTEN_Msk                 (0x1UL << AES_CR_DMAOUTEN_Pos)          /*!< 0x00001000 */
1750 #define AES_CR_DMAOUTEN                     AES_CR_DMAOUTEN_Msk                     /*!< Enable data output phase DMA management */
1751 #define AES_CR_GCMPH_Pos                    (13U)
1752 #define AES_CR_GCMPH_Msk                    (0x3UL << AES_CR_GCMPH_Pos)             /*!< 0x00006000 */
1753 #define AES_CR_GCMPH                        AES_CR_GCMPH_Msk                        /*!< GCM Phase */
1754 #define AES_CR_GCMPH_0                      (0x1UL << AES_CR_GCMPH_Pos)             /*!< 0x00002000 */
1755 #define AES_CR_GCMPH_1                      (0x2UL << AES_CR_GCMPH_Pos)             /*!< 0x00004000 */
1756 #define AES_CR_KEYSIZE_Pos                  (18U)
1757 #define AES_CR_KEYSIZE_Msk                  (0x1UL << AES_CR_KEYSIZE_Pos)           /*!< 0x00040000 */
1758 #define AES_CR_KEYSIZE                      AES_CR_KEYSIZE_Msk                      /*!< Key size selection */
1759 #define AES_CR_NPBLB_Pos                    (20U)
1760 #define AES_CR_NPBLB_Msk                    (0xFUL << AES_CR_NPBLB_Pos)             /*!< 0x00F00000 */
1761 #define AES_CR_NPBLB                        AES_CR_NPBLB_Msk                        /*!< Number of padding bytes in payload last block */
1762 #define AES_CR_NPBLB_0                      (0x1UL << AES_CR_NPBLB_Pos)             /*!< 0x00100000 */
1763 #define AES_CR_NPBLB_1                      (0x2UL << AES_CR_NPBLB_Pos)             /*!< 0x00200000 */
1764 #define AES_CR_NPBLB_2                      (0x4UL << AES_CR_NPBLB_Pos)             /*!< 0x00400000 */
1765 #define AES_CR_NPBLB_3                      (0x8UL << AES_CR_NPBLB_Pos)             /*!< 0x00800000 */
1766 #define AES_CR_IPRST_Pos                    (31U)
1767 #define AES_CR_IPRST_Msk                    (0x1UL << AES_CR_IPRST_Pos)             /*!< 0x80000000 */
1768 #define AES_CR_IPRST                        AES_CR_IPRST_Msk                        /*!< AES IP software reset */
1769 
1770 /*******************  Bit definition for AES_SR register  *********************/
1771 #define AES_SR_CCF_Pos                      (0U)
1772 #define AES_SR_CCF_Msk                      (0x1UL << AES_SR_CCF_Pos)               /*!< 0x00000001 */
1773 #define AES_SR_CCF                          AES_SR_CCF_Msk                          /*!< Computation Complete Flag */
1774 #define AES_SR_RDERR_Pos                    (1U)
1775 #define AES_SR_RDERR_Msk                    (0x1UL << AES_SR_RDERR_Pos)             /*!< 0x00000002 */
1776 #define AES_SR_RDERR                        AES_SR_RDERR_Msk                        /*!< Read Error Flag */
1777 #define AES_SR_WRERR_Pos                    (2U)
1778 #define AES_SR_WRERR_Msk                    (0x1UL << AES_SR_WRERR_Pos)             /*!< 0x00000004 */
1779 #define AES_SR_WRERR                        AES_SR_WRERR_Msk                        /*!< Write Error Flag */
1780 #define AES_SR_BUSY_Pos                     (3U)
1781 #define AES_SR_BUSY_Msk                     (0x1UL << AES_SR_BUSY_Pos)              /*!< 0x00000008 */
1782 #define AES_SR_BUSY                         AES_SR_BUSY_Msk                         /*!< Busy Flag */
1783 #define AES_SR_KEYVALID_Pos                 (7U)
1784 #define AES_SR_KEYVALID_Msk                 (0x1UL << AES_SR_KEYVALID_Pos)          /*!< 0x00000080 */
1785 #define AES_SR_KEYVALID                     AES_SR_KEYVALID_Msk                     /*!< Key Valid Flag */
1786 
1787 /*******************  Bit definition for AES_DINR register  *******************/
1788 #define AES_DINR_Pos                        (0U)
1789 #define AES_DINR_Msk                        (0xFFFFFFFFUL << AES_DINR_Pos)          /*!< 0xFFFFFFFF */
1790 #define AES_DINR                            AES_DINR_Msk                            /*!< AES Data Input Register */
1791 
1792 /*******************  Bit definition for AES_DOUTR register  ******************/
1793 #define AES_DOUTR_Pos                       (0U)
1794 #define AES_DOUTR_Msk                       (0xFFFFFFFFUL << AES_DOUTR_Pos)         /*!< 0xFFFFFFFF */
1795 #define AES_DOUTR                           AES_DOUTR_Msk                           /*!< AES Data Output Register */
1796 
1797 /*******************  Bit definition for AES_KEYR0 register  ******************/
1798 #define AES_KEYR0_Pos                       (0U)
1799 #define AES_KEYR0_Msk                       (0xFFFFFFFFUL << AES_KEYR0_Pos)         /*!< 0xFFFFFFFF */
1800 #define AES_KEYR0                           AES_KEYR0_Msk                           /*!< AES Key Register 0 */
1801 
1802 /*******************  Bit definition for AES_KEYR1 register  ******************/
1803 #define AES_KEYR1_Pos                       (0U)
1804 #define AES_KEYR1_Msk                       (0xFFFFFFFFUL << AES_KEYR1_Pos)         /*!< 0xFFFFFFFF */
1805 #define AES_KEYR1                           AES_KEYR1_Msk                           /*!< AES Key Register 1 */
1806 
1807 /*******************  Bit definition for AES_KEYR2 register  ******************/
1808 #define AES_KEYR2_Pos                       (0U)
1809 #define AES_KEYR2_Msk                       (0xFFFFFFFFUL << AES_KEYR2_Pos)         /*!< 0xFFFFFFFF */
1810 #define AES_KEYR2                           AES_KEYR2_Msk                           /*!< AES Key Register 2 */
1811 
1812 /*******************  Bit definition for AES_KEYR3 register  ******************/
1813 #define AES_KEYR3_Pos                       (0U)
1814 #define AES_KEYR3_Msk                       (0xFFFFFFFFUL << AES_KEYR3_Pos)         /*!< 0xFFFFFFFF */
1815 #define AES_KEYR3                           AES_KEYR3_Msk                           /*!< AES Key Register 3 */
1816 
1817 /*******************  Bit definition for AES_KEYR4 register  ******************/
1818 #define AES_KEYR4_Pos                       (0U)
1819 #define AES_KEYR4_Msk                       (0xFFFFFFFFUL << AES_KEYR4_Pos)         /*!< 0xFFFFFFFF */
1820 #define AES_KEYR4                           AES_KEYR4_Msk                           /*!< AES Key Register 4 */
1821 
1822 /*******************  Bit definition for AES_KEYR5 register  ******************/
1823 #define AES_KEYR5_Pos                       (0U)
1824 #define AES_KEYR5_Msk                       (0xFFFFFFFFUL << AES_KEYR5_Pos)         /*!< 0xFFFFFFFF */
1825 #define AES_KEYR5                           AES_KEYR5_Msk                           /*!< AES Key Register 5 */
1826 
1827 /*******************  Bit definition for AES_KEYR6 register  ******************/
1828 #define AES_KEYR6_Pos                       (0U)
1829 #define AES_KEYR6_Msk                       (0xFFFFFFFFUL << AES_KEYR6_Pos)         /*!< 0xFFFFFFFF */
1830 #define AES_KEYR6                           AES_KEYR6_Msk                           /*!< AES Key Register 6 */
1831 
1832 /*******************  Bit definition for AES_KEYR7 register  ******************/
1833 #define AES_KEYR7_Pos                       (0U)
1834 #define AES_KEYR7_Msk                       (0xFFFFFFFFUL << AES_KEYR7_Pos)         /*!< 0xFFFFFFFF */
1835 #define AES_KEYR7                           AES_KEYR7_Msk                           /*!< AES Key Register 7 */
1836 
1837 /*******************  Bit definition for AES_IVR0 register   ******************/
1838 #define AES_IVR0_Pos                        (0U)
1839 #define AES_IVR0_Msk                        (0xFFFFFFFFUL << AES_IVR0_Pos)          /*!< 0xFFFFFFFF */
1840 #define AES_IVR0                            AES_IVR0_Msk                            /*!< AES Initialization Vector Register 0 */
1841 
1842 /*******************  Bit definition for AES_IVR1 register   ******************/
1843 #define AES_IVR1_Pos                        (0U)
1844 #define AES_IVR1_Msk                        (0xFFFFFFFFUL << AES_IVR1_Pos)          /*!< 0xFFFFFFFF */
1845 #define AES_IVR1                            AES_IVR1_Msk                            /*!< AES Initialization Vector Register 1 */
1846 
1847 /*******************  Bit definition for AES_IVR2 register   ******************/
1848 #define AES_IVR2_Pos                        (0U)
1849 #define AES_IVR2_Msk                        (0xFFFFFFFFUL << AES_IVR2_Pos)          /*!< 0xFFFFFFFF */
1850 #define AES_IVR2                            AES_IVR2_Msk                            /*!< AES Initialization Vector Register 2 */
1851 
1852 /*******************  Bit definition for AES_IVR3 register   ******************/
1853 #define AES_IVR3_Pos                        (0U)
1854 #define AES_IVR3_Msk                        (0xFFFFFFFFUL << AES_IVR3_Pos)          /*!< 0xFFFFFFFF */
1855 #define AES_IVR3                            AES_IVR3_Msk                            /*!< AES Initialization Vector Register 3 */
1856 
1857 /*******************  Bit definition for AES_SUSP0R register  ******************/
1858 #define AES_SUSP0R_Pos                      (0U)
1859 #define AES_SUSP0R_Msk                      (0xFFFFFFFFUL << AES_SUSP0R_Pos)        /*!< 0xFFFFFFFF */
1860 #define AES_SUSP0R                          AES_SUSP0R_Msk                          /*!< AES Suspend registers 0 */
1861 
1862 /*******************  Bit definition for AES_SUSP1R register  ******************/
1863 #define AES_SUSP1R_Pos                      (0U)
1864 #define AES_SUSP1R_Msk                      (0xFFFFFFFFUL << AES_SUSP1R_Pos)        /*!< 0xFFFFFFFF */
1865 #define AES_SUSP1R                          AES_SUSP1R_Msk                          /*!< AES Suspend registers 1 */
1866 
1867 /*******************  Bit definition for AES_SUSP2R register  ******************/
1868 #define AES_SUSP2R_Pos                      (0U)
1869 #define AES_SUSP2R_Msk                      (0xFFFFFFFFUL << AES_SUSP2R_Pos)        /*!< 0xFFFFFFFF */
1870 #define AES_SUSP2R                          AES_SUSP2R_Msk                          /*!< AES Suspend registers 2 */
1871 
1872 /*******************  Bit definition for AES_SUSP3R register  ******************/
1873 #define AES_SUSP3R_Pos                      (0U)
1874 #define AES_SUSP3R_Msk                      (0xFFFFFFFFUL << AES_SUSP3R_Pos)        /*!< 0xFFFFFFFF */
1875 #define AES_SUSP3R                          AES_SUSP3R_Msk                          /*!< AES Suspend registers 3 */
1876 
1877 /*******************  Bit definition for AES_SUSP4R register  ******************/
1878 #define AES_SUSP4R_Pos                      (0U)
1879 #define AES_SUSP4R_Msk                      (0xFFFFFFFFUL << AES_SUSP4R_Pos)        /*!< 0xFFFFFFFF */
1880 #define AES_SUSP4R                          AES_SUSP4R_Msk                          /*!< AES Suspend registers 4 */
1881 
1882 /*******************  Bit definition for AES_SUSP5R register  ******************/
1883 #define AES_SUSP5R_Pos                      (0U)
1884 #define AES_SUSP5R_Msk                      (0xFFFFFFFFUL << AES_SUSP5R_Pos)        /*!< 0xFFFFFFFF */
1885 #define AES_SUSP5R                          AES_SUSP5R_Msk                          /*!< AES Suspend registers 5 */
1886 
1887 /*******************  Bit definition for AES_SUSP6R register  ******************/
1888 #define AES_SUSP6R_Pos                      (0U)
1889 #define AES_SUSP6R_Msk                      (0xFFFFFFFFUL << AES_SUSP6R_Pos)        /*!< 0xFFFFFFFF */
1890 #define AES_SUSP6R                          AES_SUSP6R_Msk                          /*!< AES Suspend registers 6 */
1891 
1892 /*******************  Bit definition for AES_SUSP7R register  ******************/
1893 #define AES_SUSP7R_Pos                      (0U)
1894 #define AES_SUSP7R_Msk                      (0xFFFFFFFFUL << AES_SUSP7R_Pos)        /*!< 0xFFFFFFFF */
1895 #define AES_SUSP7R                          AES_SUSP7R_Msk                          /*!< AES Suspend registers 7 */
1896 
1897 /*******************  Bit definition for AES_IER register     ******************/
1898 #define AES_IER_CCFIE_Pos                   (0U)
1899 #define AES_IER_CCFIE_Msk                   (0x1UL << AES_IER_CCFIE_Pos)            /*!< 0x00000001 */
1900 #define AES_IER_CCFIE                       AES_IER_CCFIE_Msk                       /*!< Computation complete flag interrupt enable */
1901 #define AES_IER_RWEIE_Pos                   (1U)
1902 #define AES_IER_RWEIE_Msk                   (0x1UL << AES_IER_RWEIE_Pos)            /*!< 0x00000002 */
1903 #define AES_IER_RWEIE                       AES_IER_RWEIE_Msk                       /*!< Read or write error Interrupt Enable */
1904 #define AES_IER_KEIE_Pos                    (2U)
1905 #define AES_IER_KEIE_Msk                    (0x1UL << AES_IER_KEIE_Pos)             /*!< 0x00000004 */
1906 #define AES_IER_KEIE                        AES_IER_KEIE_Msk                        /*!< Key error interrupt enable */
1907 
1908 /*******************  Bit definition for AES_ISR register     ******************/
1909 #define AES_ISR_CCF_Pos                     (0U)
1910 #define AES_ISR_CCF_Msk                     (0x1UL << AES_ISR_CCF_Pos)              /*!< 0x00000001 */
1911 #define AES_ISR_CCF                         AES_ISR_CCF_Msk                         /*!< Computation complete flag */
1912 #define AES_ISR_RWEIF_Pos                   (1U)
1913 #define AES_ISR_RWEIF_Msk                   (0x1UL << AES_ISR_RWEIF_Pos)            /*!< 0x00000002 */
1914 #define AES_ISR_RWEIF                       AES_ISR_RWEIF_Msk                       /*!< Read or write error Interrupt flag */
1915 #define AES_ISR_KEIF_Pos                    (2U)
1916 #define AES_ISR_KEIF_Msk                    (0x1UL << AES_ISR_KEIF_Pos)             /*!< 0x00000004 */
1917 #define AES_ISR_KEIF                        AES_ISR_KEIF_Msk                        /*!< Key error interrupt flag */
1918 
1919 /*******************  Bit definition for AES_ICR register     ******************/
1920 #define AES_ICR_CCF_Pos                     (0U)
1921 #define AES_ICR_CCF_Msk                     (0x1UL << AES_ICR_CCF_Pos)              /*!< 0x00000001 */
1922 #define AES_ICR_CCF                         AES_ICR_CCF_Msk                         /*!< Computation complete flag clear */
1923 #define AES_ICR_RWEIF_Pos                   (1U)
1924 #define AES_ICR_RWEIF_Msk                   (0x1UL << AES_ICR_RWEIF_Pos)            /*!< 0x00000002 */
1925 #define AES_ICR_RWEIF                       AES_ICR_RWEIF_Msk                       /*!< Read or write error Interrupt flag clear */
1926 #define AES_ICR_KEIF_Pos                    (2U)
1927 #define AES_ICR_KEIF_Msk                    (0x1UL << AES_ICR_KEIF_Pos)             /*!< 0x00000004 */
1928 #define AES_ICR_KEIF                        AES_ICR_KEIF_Msk                        /*!< Key error interrupt flag clear */
1929 
1930 /******************************************************************************/
1931 /*                                                                            */
1932 /*                          CRC calculation unit                              */
1933 /*                                                                            */
1934 /******************************************************************************/
1935 /*******************  Bit definition for CRC_DR register  *********************/
1936 #define CRC_DR_DR_Pos            (0U)
1937 #define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */
1938 #define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
1939 
1940 /*******************  Bit definition for CRC_IDR register  ********************/
1941 #define CRC_IDR_IDR_Pos          (0U)
1942 #define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */
1943 #define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */
1944 
1945 /********************  Bit definition for CRC_CR register  ********************/
1946 #define CRC_CR_RESET_Pos         (0U)
1947 #define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                 /*!< 0x00000001 */
1948 #define CRC_CR_RESET             CRC_CR_RESET_Msk                            /*!< RESET the CRC computation unit bit */
1949 #define CRC_CR_POLYSIZE_Pos      (3U)
1950 #define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000018 */
1951 #define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                         /*!< Polynomial size bits */
1952 #define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000008 */
1953 #define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000010 */
1954 #define CRC_CR_REV_IN_Pos        (5U)
1955 #define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000060 */
1956 #define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                           /*!< REV_IN Reverse Input Data bits */
1957 #define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000020 */
1958 #define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000040 */
1959 #define CRC_CR_REV_OUT_Pos       (7U)
1960 #define CRC_CR_REV_OUT_Msk       (0x3UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000180 */
1961 #define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                          /*!< REV_OUT Reverse Output Data bits */
1962 #define CRC_CR_REV_OUT_0         (0x1UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000080 */
1963 #define CRC_CR_REV_OUT_1         (0x2UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000100 */
1964 #define CRC_CR_RTYPE_IN_Pos      (9U)
1965 #define CRC_CR_RTYPE_IN_Msk      (0x1UL << CRC_CR_RTYPE_IN_Pos)              /*!< 0x00000200 */
1966 #define CRC_CR_RTYPE_IN          CRC_CR_RTYPE_IN_Msk                         /*!< Reverse type input */
1967 #define CRC_CR_RTYPE_OUT_Pos     (10U)
1968 #define CRC_CR_RTYPE_OUT_Msk     (0x1UL << CRC_CR_RTYPE_OUT_Pos)             /*!< 0x00000400 */
1969 #define CRC_CR_RTYPE_OUT         CRC_CR_RTYPE_OUT_Msk                        /*!< Reverse type output*/
1970 
1971 
1972 /*******************  Bit definition for CRC_INIT register  *******************/
1973 #define CRC_INIT_INIT_Pos        (0U)
1974 #define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */
1975 #define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
1976 
1977 /*******************  Bit definition for CRC_POL register  ********************/
1978 #define CRC_POL_POL_Pos          (0U)
1979 #define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */
1980 #define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
1981 /******************************************************************************/
1982 /*                                                                            */
1983 /*                          CRS Clock Recovery System                         */
1984 /******************************************************************************/
1985 
1986 /*******************  Bit definition for CRS_CR register  *********************/
1987 #define CRS_CR_SYNCOKIE_Pos       (0U)
1988 #define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */
1989 #define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */
1990 #define CRS_CR_SYNCWARNIE_Pos     (1U)
1991 #define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */
1992 #define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */
1993 #define CRS_CR_ERRIE_Pos          (2U)
1994 #define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */
1995 #define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */
1996 #define CRS_CR_ESYNCIE_Pos        (3U)
1997 #define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */
1998 #define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */
1999 #define CRS_CR_CEN_Pos            (5U)
2000 #define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */
2001 #define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */
2002 #define CRS_CR_AUTOTRIMEN_Pos     (6U)
2003 #define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */
2004 #define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */
2005 #define CRS_CR_SWSYNC_Pos         (7U)
2006 #define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */
2007 #define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */
2008 #define CRS_CR_TRIM_Pos           (8U)
2009 #define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */
2010 #define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */
2011 
2012 /*******************  Bit definition for CRS_CFGR register  *********************/
2013 #define CRS_CFGR_RELOAD_Pos       (0U)
2014 #define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */
2015 #define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */
2016 #define CRS_CFGR_FELIM_Pos        (16U)
2017 #define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */
2018 #define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */
2019 
2020 #define CRS_CFGR_SYNCDIV_Pos      (24U)
2021 #define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */
2022 #define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */
2023 #define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
2024 #define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
2025 #define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
2026 
2027 #define CRS_CFGR_SYNCSRC_Pos      (28U)
2028 #define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */
2029 #define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */
2030 #define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
2031 #define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
2032 
2033 #define CRS_CFGR_SYNCPOL_Pos      (31U)
2034 #define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */
2035 #define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */
2036 
2037 /*******************  Bit definition for CRS_ISR register  *********************/
2038 #define CRS_ISR_SYNCOKF_Pos       (0U)
2039 #define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */
2040 #define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */
2041 #define CRS_ISR_SYNCWARNF_Pos     (1U)
2042 #define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */
2043 #define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */
2044 #define CRS_ISR_ERRF_Pos          (2U)
2045 #define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */
2046 #define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */
2047 #define CRS_ISR_ESYNCF_Pos        (3U)
2048 #define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */
2049 #define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */
2050 #define CRS_ISR_SYNCERR_Pos       (8U)
2051 #define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */
2052 #define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */
2053 #define CRS_ISR_SYNCMISS_Pos      (9U)
2054 #define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */
2055 #define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */
2056 #define CRS_ISR_TRIMOVF_Pos       (10U)
2057 #define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */
2058 #define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */
2059 #define CRS_ISR_FEDIR_Pos         (15U)
2060 #define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */
2061 #define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */
2062 #define CRS_ISR_FECAP_Pos         (16U)
2063 #define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */
2064 #define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */
2065 
2066 /*******************  Bit definition for CRS_ICR register  *********************/
2067 #define CRS_ICR_SYNCOKC_Pos       (0U)
2068 #define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */
2069 #define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */
2070 #define CRS_ICR_SYNCWARNC_Pos     (1U)
2071 #define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */
2072 #define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */
2073 #define CRS_ICR_ERRC_Pos          (2U)
2074 #define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */
2075 #define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */
2076 #define CRS_ICR_ESYNCC_Pos        (3U)
2077 #define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */
2078 #define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */
2079 /******************************************************************************/
2080 /*                                                                            */
2081 /*                      Digital to Analog Converter                           */
2082 /*                                                                            */
2083 /******************************************************************************/
2084 /********************  Bit definition for DAC_CR register  ********************/
2085 #define DAC_CR_EN1_Pos              (0U)
2086 #define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */
2087 #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
2088 #define DAC_CR_TEN1_Pos             (1U)
2089 #define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */
2090 #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
2091 
2092 #define DAC_CR_TSEL1_Pos            (2U)
2093 #define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */
2094 #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
2095 #define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */
2096 #define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
2097 #define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
2098 #define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
2099 
2100 
2101 #define DAC_CR_WAVE1_Pos            (6U)
2102 #define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */
2103 #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
2104 #define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
2105 #define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
2106 
2107 #define DAC_CR_MAMP1_Pos            (8U)
2108 #define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */
2109 #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
2110 #define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
2111 #define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
2112 #define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
2113 #define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
2114 
2115 #define DAC_CR_DMAEN1_Pos           (12U)
2116 #define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */
2117 #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
2118 #define DAC_CR_DMAUDRIE1_Pos        (13U)
2119 #define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */
2120 #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
2121 #define DAC_CR_CEN1_Pos             (14U)
2122 #define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */
2123 #define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
2124 
2125 #define DAC_CR_EN2_Pos              (16U)
2126 #define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */
2127 #define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
2128 #define DAC_CR_TEN2_Pos             (17U)
2129 #define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */
2130 #define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
2131 
2132 #define DAC_CR_TSEL2_Pos            (18U)
2133 #define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */
2134 #define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
2135 #define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */
2136 #define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
2137 #define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
2138 #define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
2139 
2140 
2141 #define DAC_CR_WAVE2_Pos            (22U)
2142 #define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */
2143 #define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
2144 #define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
2145 #define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
2146 
2147 #define DAC_CR_MAMP2_Pos            (24U)
2148 #define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */
2149 #define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
2150 #define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
2151 #define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
2152 #define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
2153 #define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
2154 
2155 #define DAC_CR_DMAEN2_Pos           (28U)
2156 #define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */
2157 #define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
2158 #define DAC_CR_DMAUDRIE2_Pos        (29U)
2159 #define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */
2160 #define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
2161 #define DAC_CR_CEN2_Pos             (30U)
2162 #define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */
2163 #define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
2164 
2165 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
2166 #define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
2167 #define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */
2168 #define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
2169 #define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
2170 #define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */
2171 #define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
2172 
2173 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
2174 #define DAC_DHR12R1_DACC1DHR_Pos    (0U)
2175 #define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */
2176 #define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
2177 
2178 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
2179 #define DAC_DHR12L1_DACC1DHR_Pos    (4U)
2180 #define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
2181 #define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
2182 
2183 /******************  Bit definition for DAC_DHR8R1 register  ******************/
2184 #define DAC_DHR8R1_DACC1DHR_Pos     (0U)
2185 #define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */
2186 #define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
2187 
2188 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
2189 #define DAC_DHR12R2_DACC2DHR_Pos    (0U)
2190 #define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */
2191 #define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
2192 
2193 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
2194 #define DAC_DHR12L2_DACC2DHR_Pos    (4U)
2195 #define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */
2196 #define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
2197 
2198 /******************  Bit definition for DAC_DHR8R2 register  ******************/
2199 #define DAC_DHR8R2_DACC2DHR_Pos     (0U)
2200 #define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */
2201 #define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
2202 
2203 /*****************  Bit definition for DAC_DHR12RD register  ******************/
2204 #define DAC_DHR12RD_DACC1DHR_Pos    (0U)
2205 #define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */
2206 #define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
2207 #define DAC_DHR12RD_DACC2DHR_Pos    (16U)
2208 #define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */
2209 #define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
2210 
2211 /*****************  Bit definition for DAC_DHR12LD register  ******************/
2212 #define DAC_DHR12LD_DACC1DHR_Pos    (4U)
2213 #define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
2214 #define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
2215 #define DAC_DHR12LD_DACC2DHR_Pos    (20U)
2216 #define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */
2217 #define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
2218 
2219 /******************  Bit definition for DAC_DHR8RD register  ******************/
2220 #define DAC_DHR8RD_DACC1DHR_Pos     (0U)
2221 #define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */
2222 #define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
2223 #define DAC_DHR8RD_DACC2DHR_Pos     (8U)
2224 #define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */
2225 #define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
2226 
2227 /*******************  Bit definition for DAC_DOR1 register  *******************/
2228 #define DAC_DOR1_DACC1DOR_Pos       (0U)
2229 #define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */
2230 #define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
2231 
2232 /*******************  Bit definition for DAC_DOR2 register  *******************/
2233 #define DAC_DOR2_DACC2DOR_Pos       (0U)
2234 #define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */
2235 #define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
2236 
2237 /********************  Bit definition for DAC_SR register  ********************/
2238 #define DAC_SR_DMAUDR1_Pos          (13U)
2239 #define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */
2240 #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
2241 #define DAC_SR_CAL_FLAG1_Pos        (14U)
2242 #define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */
2243 #define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
2244 #define DAC_SR_BWST1_Pos            (15U)
2245 #define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */
2246 #define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
2247 
2248 #define DAC_SR_DMAUDR2_Pos          (29U)
2249 #define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */
2250 #define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
2251 #define DAC_SR_CAL_FLAG2_Pos        (30U)
2252 #define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */
2253 #define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
2254 #define DAC_SR_BWST2_Pos            (31U)
2255 #define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */
2256 #define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
2257 
2258 /*******************  Bit definition for DAC_CCR register  ********************/
2259 #define DAC_CCR_OTRIM1_Pos          (0U)
2260 #define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */
2261 #define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
2262 #define DAC_CCR_OTRIM2_Pos          (16U)
2263 #define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */
2264 #define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
2265 
2266 /*******************  Bit definition for DAC_MCR register  *******************/
2267 #define DAC_MCR_MODE1_Pos           (0U)
2268 #define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */
2269 #define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
2270 #define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */
2271 #define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */
2272 #define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */
2273 
2274 #define DAC_MCR_MODE2_Pos           (16U)
2275 #define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */
2276 #define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
2277 #define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */
2278 #define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */
2279 #define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */
2280 
2281 /******************  Bit definition for DAC_SHSR1 register  ******************/
2282 #define DAC_SHSR1_TSAMPLE1_Pos      (0U)
2283 #define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */
2284 #define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
2285 
2286 /******************  Bit definition for DAC_SHSR2 register  ******************/
2287 #define DAC_SHSR2_TSAMPLE2_Pos      (0U)
2288 #define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */
2289 #define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
2290 
2291 /******************  Bit definition for DAC_SHHR register  ******************/
2292 #define DAC_SHHR_THOLD1_Pos         (0U)
2293 #define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */
2294 #define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
2295 #define DAC_SHHR_THOLD2_Pos         (16U)
2296 #define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */
2297 #define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
2298 
2299 /******************  Bit definition for DAC_SHRR register  ******************/
2300 #define DAC_SHRR_TREFRESH1_Pos      (0U)
2301 #define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */
2302 #define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
2303 #define DAC_SHRR_TREFRESH2_Pos      (16U)
2304 #define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */
2305 #define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
2306 
2307 /******************************************************************************/
2308 /*                                                                            */
2309 /*                           DMA Controller (DMA)                             */
2310 /*                                                                            */
2311 /******************************************************************************/
2312 
2313 /*******************  Bit definition for DMA_ISR register  ********************/
2314 #define DMA_ISR_GIF1_Pos       (0U)
2315 #define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                     /*!< 0x00000001 */
2316 #define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
2317 #define DMA_ISR_TCIF1_Pos      (1U)
2318 #define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                    /*!< 0x00000002 */
2319 #define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
2320 #define DMA_ISR_HTIF1_Pos      (2U)
2321 #define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                    /*!< 0x00000004 */
2322 #define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
2323 #define DMA_ISR_TEIF1_Pos      (3U)
2324 #define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                    /*!< 0x00000008 */
2325 #define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
2326 #define DMA_ISR_GIF2_Pos       (4U)
2327 #define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                     /*!< 0x00000010 */
2328 #define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
2329 #define DMA_ISR_TCIF2_Pos      (5U)
2330 #define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                    /*!< 0x00000020 */
2331 #define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
2332 #define DMA_ISR_HTIF2_Pos      (6U)
2333 #define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                    /*!< 0x00000040 */
2334 #define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
2335 #define DMA_ISR_TEIF2_Pos      (7U)
2336 #define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                    /*!< 0x00000080 */
2337 #define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
2338 #define DMA_ISR_GIF3_Pos       (8U)
2339 #define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                     /*!< 0x00000100 */
2340 #define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
2341 #define DMA_ISR_TCIF3_Pos      (9U)
2342 #define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                    /*!< 0x00000200 */
2343 #define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
2344 #define DMA_ISR_HTIF3_Pos      (10U)
2345 #define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                    /*!< 0x00000400 */
2346 #define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
2347 #define DMA_ISR_TEIF3_Pos      (11U)
2348 #define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                    /*!< 0x00000800 */
2349 #define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 4 Transfer Error flag */
2350 #define DMA_ISR_GIF4_Pos       (12U)
2351 #define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                     /*!< 0x00001000 */
2352 #define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
2353 #define DMA_ISR_TCIF4_Pos      (13U)
2354 #define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                    /*!< 0x00002000 */
2355 #define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
2356 #define DMA_ISR_HTIF4_Pos      (14U)
2357 #define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                    /*!< 0x00004000 */
2358 #define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
2359 #define DMA_ISR_TEIF4_Pos      (15U)
2360 #define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                    /*!< 0x00008000 */
2361 #define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
2362 #define DMA_ISR_GIF5_Pos       (16U)
2363 #define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                     /*!< 0x00010000 */
2364 #define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
2365 #define DMA_ISR_TCIF5_Pos      (17U)
2366 #define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                    /*!< 0x00020000 */
2367 #define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
2368 #define DMA_ISR_HTIF5_Pos      (18U)
2369 #define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                    /*!< 0x00040000 */
2370 #define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
2371 #define DMA_ISR_TEIF5_Pos      (19U)
2372 #define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                    /*!< 0x00080000 */
2373 #define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
2374 #define DMA_ISR_GIF6_Pos       (20U)
2375 #define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                     /*!< 0x00100000 */
2376 #define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
2377 #define DMA_ISR_TCIF6_Pos      (21U)
2378 #define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                    /*!< 0x00200000 */
2379 #define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
2380 #define DMA_ISR_HTIF6_Pos      (22U)
2381 #define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                    /*!< 0x00400000 */
2382 #define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
2383 #define DMA_ISR_TEIF6_Pos      (23U)
2384 #define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                    /*!< 0x00800000 */
2385 #define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
2386 #define DMA_ISR_GIF7_Pos       (24U)
2387 #define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                     /*!< 0x01000000 */
2388 #define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
2389 #define DMA_ISR_TCIF7_Pos      (25U)
2390 #define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                    /*!< 0x02000000 */
2391 #define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
2392 #define DMA_ISR_HTIF7_Pos      (26U)
2393 #define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                    /*!< 0x04000000 */
2394 #define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
2395 #define DMA_ISR_TEIF7_Pos      (27U)
2396 #define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                    /*!< 0x08000000 */
2397 #define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
2398 
2399 /*******************  Bit definition for DMA_IFCR register  *******************/
2400 #define DMA_IFCR_CGIF1_Pos     (0U)
2401 #define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                   /*!< 0x00000001 */
2402 #define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clearr */
2403 #define DMA_IFCR_CTCIF1_Pos    (1U)
2404 #define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                  /*!< 0x00000002 */
2405 #define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
2406 #define DMA_IFCR_CHTIF1_Pos    (2U)
2407 #define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                  /*!< 0x00000004 */
2408 #define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
2409 #define DMA_IFCR_CTEIF1_Pos    (3U)
2410 #define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                  /*!< 0x00000008 */
2411 #define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
2412 #define DMA_IFCR_CGIF2_Pos     (4U)
2413 #define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                   /*!< 0x00000010 */
2414 #define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
2415 #define DMA_IFCR_CTCIF2_Pos    (5U)
2416 #define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                  /*!< 0x00000020 */
2417 #define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
2418 #define DMA_IFCR_CHTIF2_Pos    (6U)
2419 #define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                  /*!< 0x00000040 */
2420 #define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
2421 #define DMA_IFCR_CTEIF2_Pos    (7U)
2422 #define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                  /*!< 0x00000080 */
2423 #define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
2424 #define DMA_IFCR_CGIF3_Pos     (8U)
2425 #define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                   /*!< 0x00000100 */
2426 #define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
2427 #define DMA_IFCR_CTCIF3_Pos    (9U)
2428 #define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                  /*!< 0x00000200 */
2429 #define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
2430 #define DMA_IFCR_CHTIF3_Pos    (10U)
2431 #define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                  /*!< 0x00000400 */
2432 #define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
2433 #define DMA_IFCR_CTEIF3_Pos    (11U)
2434 #define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                  /*!< 0x00000800 */
2435 #define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
2436 #define DMA_IFCR_CGIF4_Pos     (12U)
2437 #define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                   /*!< 0x00001000 */
2438 #define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
2439 #define DMA_IFCR_CTCIF4_Pos    (13U)
2440 #define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                  /*!< 0x00002000 */
2441 #define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
2442 #define DMA_IFCR_CHTIF4_Pos    (14U)
2443 #define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                  /*!< 0x00004000 */
2444 #define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
2445 #define DMA_IFCR_CTEIF4_Pos    (15U)
2446 #define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                  /*!< 0x00008000 */
2447 #define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
2448 #define DMA_IFCR_CGIF5_Pos     (16U)
2449 #define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                   /*!< 0x00010000 */
2450 #define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
2451 #define DMA_IFCR_CTCIF5_Pos    (17U)
2452 #define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                  /*!< 0x00020000 */
2453 #define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
2454 #define DMA_IFCR_CHTIF5_Pos    (18U)
2455 #define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                  /*!< 0x00040000 */
2456 #define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
2457 #define DMA_IFCR_CTEIF5_Pos    (19U)
2458 #define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                  /*!< 0x00080000 */
2459 #define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
2460 #define DMA_IFCR_CGIF6_Pos     (20U)
2461 #define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                   /*!< 0x00100000 */
2462 #define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
2463 #define DMA_IFCR_CTCIF6_Pos    (21U)
2464 #define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                  /*!< 0x00200000 */
2465 #define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
2466 #define DMA_IFCR_CHTIF6_Pos    (22U)
2467 #define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                  /*!< 0x00400000 */
2468 #define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
2469 #define DMA_IFCR_CTEIF6_Pos    (23U)
2470 #define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                  /*!< 0x00800000 */
2471 #define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
2472 #define DMA_IFCR_CGIF7_Pos     (24U)
2473 #define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                   /*!< 0x01000000 */
2474 #define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
2475 #define DMA_IFCR_CTCIF7_Pos    (25U)
2476 #define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                  /*!< 0x02000000 */
2477 #define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
2478 #define DMA_IFCR_CHTIF7_Pos    (26U)
2479 #define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                  /*!< 0x04000000 */
2480 #define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
2481 #define DMA_IFCR_CTEIF7_Pos    (27U)
2482 #define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                  /*!< 0x08000000 */
2483 #define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
2484 
2485 /*******************  Bit definition for DMA_CCR register  ********************/
2486 #define DMA_CCR_EN_Pos         (0U)
2487 #define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                       /*!< 0x00000001 */
2488 #define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
2489 #define DMA_CCR_TCIE_Pos       (1U)
2490 #define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                     /*!< 0x00000002 */
2491 #define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
2492 #define DMA_CCR_HTIE_Pos       (2U)
2493 #define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                     /*!< 0x00000004 */
2494 #define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
2495 #define DMA_CCR_TEIE_Pos       (3U)
2496 #define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                     /*!< 0x00000008 */
2497 #define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
2498 #define DMA_CCR_DIR_Pos        (4U)
2499 #define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                      /*!< 0x00000010 */
2500 #define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
2501 #define DMA_CCR_CIRC_Pos       (5U)
2502 #define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                     /*!< 0x00000020 */
2503 #define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
2504 #define DMA_CCR_PINC_Pos       (6U)
2505 #define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                     /*!< 0x00000040 */
2506 #define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
2507 #define DMA_CCR_MINC_Pos       (7U)
2508 #define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                     /*!< 0x00000080 */
2509 #define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
2510 
2511 #define DMA_CCR_PSIZE_Pos      (8U)
2512 #define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000300 */
2513 #define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
2514 #define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000100 */
2515 #define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000200 */
2516 
2517 #define DMA_CCR_MSIZE_Pos      (10U)
2518 #define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000C00 */
2519 #define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
2520 #define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000400 */
2521 #define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000800 */
2522 
2523 #define DMA_CCR_PL_Pos         (12U)
2524 #define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                       /*!< 0x00003000 */
2525 #define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
2526 #define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                       /*!< 0x00001000 */
2527 #define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
2528 
2529 #define DMA_CCR_MEM2MEM_Pos    (14U)
2530 #define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                  /*!< 0x00004000 */
2531 #define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
2532 
2533 /******************  Bit definition for DMA_CNDTR register  *******************/
2534 #define DMA_CNDTR_NDT_Pos      (0U)
2535 #define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                 /*!< 0x0000FFFF */
2536 #define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
2537 
2538 /******************  Bit definition for DMA_CPAR register  ********************/
2539 #define DMA_CPAR_PA_Pos        (0U)
2540 #define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)               /*!< 0xFFFFFFFF */
2541 #define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
2542 
2543 /******************  Bit definition for DMA_CMAR register  ********************/
2544 #define DMA_CMAR_MA_Pos        (0U)
2545 #define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)               /*!< 0xFFFFFFFF */
2546 #define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
2547 
2548 /******************************************************************************/
2549 /*                                                                            */
2550 /*                             DMAMUX Controller                              */
2551 /*                                                                            */
2552 /******************************************************************************/
2553 /********************  Bits definition for DMAMUX_CxCR register  **************/
2554 #define DMAMUX_CxCR_DMAREQ_ID_Pos              (0U)
2555 #define DMAMUX_CxCR_DMAREQ_ID_Msk              (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */
2556 #define DMAMUX_CxCR_DMAREQ_ID                  DMAMUX_CxCR_DMAREQ_ID_Msk             /*!< DMA Request ID   */
2557 #define DMAMUX_CxCR_DMAREQ_ID_0                (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
2558 #define DMAMUX_CxCR_DMAREQ_ID_1                (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
2559 #define DMAMUX_CxCR_DMAREQ_ID_2                (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
2560 #define DMAMUX_CxCR_DMAREQ_ID_3                (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
2561 #define DMAMUX_CxCR_DMAREQ_ID_4                (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
2562 #define DMAMUX_CxCR_DMAREQ_ID_5                (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
2563 #define DMAMUX_CxCR_DMAREQ_ID_6                (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
2564 #define DMAMUX_CxCR_DMAREQ_ID_7                (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
2565 #define DMAMUX_CxCR_SOIE_Pos                   (8U)
2566 #define DMAMUX_CxCR_SOIE_Msk                   (0x1UL << DMAMUX_CxCR_SOIE_Pos)  /*!< 0x00000100 */
2567 #define DMAMUX_CxCR_SOIE                       DMAMUX_CxCR_SOIE_Msk             /*!< Synchro overrun interrupt enable     */
2568 #define DMAMUX_CxCR_EGE_Pos                    (9U)
2569 #define DMAMUX_CxCR_EGE_Msk                    (0x1UL << DMAMUX_CxCR_EGE_Pos)   /*!< 0x00000200 */
2570 #define DMAMUX_CxCR_EGE                        DMAMUX_CxCR_EGE_Msk              /*!< Event generation interrupt enable    */
2571 #define DMAMUX_CxCR_SE_Pos                     (16U)
2572 #define DMAMUX_CxCR_SE_Msk                     (0x1UL << DMAMUX_CxCR_SE_Pos)    /*!< 0x00010000 */
2573 #define DMAMUX_CxCR_SE                         DMAMUX_CxCR_SE_Msk               /*!< Synchronization enable               */
2574 #define DMAMUX_CxCR_SPOL_Pos                   (17U)
2575 #define DMAMUX_CxCR_SPOL_Msk                   (0x3UL << DMAMUX_CxCR_SPOL_Pos)  /*!< 0x00060000 */
2576 #define DMAMUX_CxCR_SPOL                       DMAMUX_CxCR_SPOL_Msk             /*!< Synchronization polarity             */
2577 #define DMAMUX_CxCR_SPOL_0                     (0x1UL << DMAMUX_CxCR_SPOL_Pos)  /*!< 0x00020000 */
2578 #define DMAMUX_CxCR_SPOL_1                     (0x2UL << DMAMUX_CxCR_SPOL_Pos)  /*!< 0x00040000 */
2579 #define DMAMUX_CxCR_NBREQ_Pos                  (19U)
2580 #define DMAMUX_CxCR_NBREQ_Msk                  (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
2581 #define DMAMUX_CxCR_NBREQ                      DMAMUX_CxCR_NBREQ_Msk             /*!< Number of request                    */
2582 #define DMAMUX_CxCR_NBREQ_0                    (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
2583 #define DMAMUX_CxCR_NBREQ_1                    (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
2584 #define DMAMUX_CxCR_NBREQ_2                    (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
2585 #define DMAMUX_CxCR_NBREQ_3                    (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
2586 #define DMAMUX_CxCR_NBREQ_4                    (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
2587 #define DMAMUX_CxCR_SYNC_ID_Pos                (24U)
2588 #define DMAMUX_CxCR_SYNC_ID_Msk                (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
2589 #define DMAMUX_CxCR_SYNC_ID                    DMAMUX_CxCR_SYNC_ID_Msk             /*!< Synchronization ID                   */
2590 #define DMAMUX_CxCR_SYNC_ID_0                  (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
2591 #define DMAMUX_CxCR_SYNC_ID_1                  (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
2592 #define DMAMUX_CxCR_SYNC_ID_2                  (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
2593 #define DMAMUX_CxCR_SYNC_ID_3                  (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
2594 #define DMAMUX_CxCR_SYNC_ID_4                  (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
2595 
2596 /*******************  Bits definition for DMAMUX_CSR register  **************/
2597 #define DMAMUX_CSR_SOF0_Pos                          (0U)
2598 #define DMAMUX_CSR_SOF0_Msk                          (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */
2599 #define DMAMUX_CSR_SOF0                              DMAMUX_CSR_SOF0_Msk
2600 #define DMAMUX_CSR_SOF1_Pos                          (1U)
2601 #define DMAMUX_CSR_SOF1_Msk                          (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */
2602 #define DMAMUX_CSR_SOF1                              DMAMUX_CSR_SOF1_Msk
2603 #define DMAMUX_CSR_SOF2_Pos                          (2U)
2604 #define DMAMUX_CSR_SOF2_Msk                          (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */
2605 #define DMAMUX_CSR_SOF2                              DMAMUX_CSR_SOF2_Msk
2606 #define DMAMUX_CSR_SOF3_Pos                          (3U)
2607 #define DMAMUX_CSR_SOF3_Msk                          (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */
2608 #define DMAMUX_CSR_SOF3                              DMAMUX_CSR_SOF3_Msk
2609 #define DMAMUX_CSR_SOF4_Pos                          (4U)
2610 #define DMAMUX_CSR_SOF4_Msk                          (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */
2611 #define DMAMUX_CSR_SOF4                              DMAMUX_CSR_SOF4_Msk
2612 #define DMAMUX_CSR_SOF5_Pos                          (5U)
2613 #define DMAMUX_CSR_SOF5_Msk                          (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */
2614 #define DMAMUX_CSR_SOF5                              DMAMUX_CSR_SOF5_Msk
2615 #define DMAMUX_CSR_SOF6_Pos                          (6U)
2616 #define DMAMUX_CSR_SOF6_Msk                          (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */
2617 #define DMAMUX_CSR_SOF6                              DMAMUX_CSR_SOF6_Msk
2618 #define DMAMUX_CSR_SOF7_Pos                          (7U)
2619 #define DMAMUX_CSR_SOF7_Msk                          (0x1UL << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */
2620 #define DMAMUX_CSR_SOF7                              DMAMUX_CSR_SOF7_Msk
2621 #define DMAMUX_CSR_SOF8_Pos                          (8U)
2622 #define DMAMUX_CSR_SOF8_Msk                          (0x1UL << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */
2623 #define DMAMUX_CSR_SOF8                              DMAMUX_CSR_SOF8_Msk
2624 #define DMAMUX_CSR_SOF9_Pos                          (9U)
2625 #define DMAMUX_CSR_SOF9_Msk                          (0x1UL << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */
2626 #define DMAMUX_CSR_SOF9                              DMAMUX_CSR_SOF9_Msk
2627 #define DMAMUX_CSR_SOF10_Pos                         (10U)
2628 #define DMAMUX_CSR_SOF10_Msk                         (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */
2629 #define DMAMUX_CSR_SOF10                             DMAMUX_CSR_SOF10_Msk
2630 #define DMAMUX_CSR_SOF11_Pos                         (11U)
2631 #define DMAMUX_CSR_SOF11_Msk                         (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */
2632 #define DMAMUX_CSR_SOF11                              DMAMUX_CSR_SOF11_Msk
2633 
2634 /********************  Bits definition for DMAMUX_CFR register  **************/
2635 #define DMAMUX_CFR_CSOF0_Pos                         (0U)
2636 #define DMAMUX_CFR_CSOF0_Msk                         (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
2637 #define DMAMUX_CFR_CSOF0                             DMAMUX_CFR_CSOF0_Msk
2638 #define DMAMUX_CFR_CSOF1_Pos                         (1U)
2639 #define DMAMUX_CFR_CSOF1_Msk                         (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
2640 #define DMAMUX_CFR_CSOF1                             DMAMUX_CFR_CSOF1_Msk
2641 #define DMAMUX_CFR_CSOF2_Pos                         (2U)
2642 #define DMAMUX_CFR_CSOF2_Msk                         (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
2643 #define DMAMUX_CFR_CSOF2                             DMAMUX_CFR_CSOF2_Msk
2644 #define DMAMUX_CFR_CSOF3_Pos                         (3U)
2645 #define DMAMUX_CFR_CSOF3_Msk                         (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
2646 #define DMAMUX_CFR_CSOF3                             DMAMUX_CFR_CSOF3_Msk
2647 #define DMAMUX_CFR_CSOF4_Pos                         (4U)
2648 #define DMAMUX_CFR_CSOF4_Msk                         (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
2649 #define DMAMUX_CFR_CSOF4                             DMAMUX_CFR_CSOF4_Msk
2650 #define DMAMUX_CFR_CSOF5_Pos                         (5U)
2651 #define DMAMUX_CFR_CSOF5_Msk                         (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
2652 #define DMAMUX_CFR_CSOF5                             DMAMUX_CFR_CSOF5_Msk
2653 #define DMAMUX_CFR_CSOF6_Pos                         (6U)
2654 #define DMAMUX_CFR_CSOF6_Msk                         (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
2655 #define DMAMUX_CFR_CSOF6                             DMAMUX_CFR_CSOF6_Msk
2656 #define DMAMUX_CFR_CSOF7_Pos                         (7U)
2657 #define DMAMUX_CFR_CSOF7_Msk                         (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */
2658 #define DMAMUX_CFR_CSOF7                             DMAMUX_CFR_CSOF7_Msk
2659 #define DMAMUX_CFR_CSOF8_Pos                         (8U)
2660 #define DMAMUX_CFR_CSOF8_Msk                         (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */
2661 #define DMAMUX_CFR_CSOF8                             DMAMUX_CFR_CSOF8_Msk
2662 #define DMAMUX_CFR_CSOF9_Pos                         (9U)
2663 #define DMAMUX_CFR_CSOF9_Msk                         (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */
2664 #define DMAMUX_CFR_CSOF9                             DMAMUX_CFR_CSOF9_Msk
2665 #define DMAMUX_CFR_CSOF10_Pos                        (10U)
2666 #define DMAMUX_CFR_CSOF10_Msk                        (0x1UL << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */
2667 #define DMAMUX_CFR_CSOF10                            DMAMUX_CFR_CSOF10_Msk
2668 #define DMAMUX_CFR_CSOF11_Pos                        (11U)
2669 #define DMAMUX_CFR_CSOF11_Msk                        (0x1UL << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */
2670 #define DMAMUX_CFR_CSOF11                            DMAMUX_CFR_CSOF11_Msk
2671 
2672 /********************  Bits definition for DMAMUX_RGxCR register  ************/
2673 #define DMAMUX_RGxCR_SIG_ID_Pos                (0U)
2674 #define DMAMUX_RGxCR_SIG_ID_Msk                (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
2675 #define DMAMUX_RGxCR_SIG_ID                    DMAMUX_RGxCR_SIG_ID_Msk             /*!< Signal ID                         */
2676 #define DMAMUX_RGxCR_SIG_ID_0                  (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
2677 #define DMAMUX_RGxCR_SIG_ID_1                  (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
2678 #define DMAMUX_RGxCR_SIG_ID_2                  (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
2679 #define DMAMUX_RGxCR_SIG_ID_3                  (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
2680 #define DMAMUX_RGxCR_SIG_ID_4                  (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
2681 #define DMAMUX_RGxCR_OIE_Pos                   (8U)
2682 #define DMAMUX_RGxCR_OIE_Msk                   (0x1UL << DMAMUX_RGxCR_OIE_Pos)  /*!< 0x00000100 */
2683 #define DMAMUX_RGxCR_OIE                       DMAMUX_RGxCR_OIE_Msk             /*!< Overrun interrupt enable             */
2684 #define DMAMUX_RGxCR_GE_Pos                    (16U)
2685 #define DMAMUX_RGxCR_GE_Msk                    (0x1UL << DMAMUX_RGxCR_GE_Pos)   /*!< 0x00010000 */
2686 #define DMAMUX_RGxCR_GE                        DMAMUX_RGxCR_GE_Msk              /*!< Generation enable                    */
2687 #define DMAMUX_RGxCR_GPOL_Pos                  (17U)
2688 #define DMAMUX_RGxCR_GPOL_Msk                  (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
2689 #define DMAMUX_RGxCR_GPOL                      DMAMUX_RGxCR_GPOL_Msk            /*!< Generation polarity                  */
2690 #define DMAMUX_RGxCR_GPOL_0                    (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
2691 #define DMAMUX_RGxCR_GPOL_1                    (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
2692 #define DMAMUX_RGxCR_GNBREQ_Pos                (19U)
2693 #define DMAMUX_RGxCR_GNBREQ_Msk                (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
2694 #define DMAMUX_RGxCR_GNBREQ                    DMAMUX_RGxCR_GNBREQ_Msk             /*!< Number of request                 */
2695 #define DMAMUX_RGxCR_GNBREQ_0                  (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
2696 #define DMAMUX_RGxCR_GNBREQ_1                  (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
2697 #define DMAMUX_RGxCR_GNBREQ_2                  (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
2698 #define DMAMUX_RGxCR_GNBREQ_3                  (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
2699 #define DMAMUX_RGxCR_GNBREQ_4                  (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
2700 
2701 /********************  Bits definition for DMAMUX_RGSR register  **************/
2702 #define DMAMUX_RGSR_OF0_Pos                    (0U)
2703 #define DMAMUX_RGSR_OF0_Msk                    (0x1UL << DMAMUX_RGSR_OF0_Pos)   /*!< 0x00000001 */
2704 #define DMAMUX_RGSR_OF0                        DMAMUX_RGSR_OF0_Msk              /*!< Overrun flag 0                       */
2705 #define DMAMUX_RGSR_OF1_Pos                    (1U)
2706 #define DMAMUX_RGSR_OF1_Msk                    (0x1UL << DMAMUX_RGSR_OF1_Pos)   /*!< 0x00000002 */
2707 #define DMAMUX_RGSR_OF1                        DMAMUX_RGSR_OF1_Msk              /*!< Overrun flag 1                       */
2708 #define DMAMUX_RGSR_OF2_Pos                    (2U)
2709 #define DMAMUX_RGSR_OF2_Msk                    (0x1UL << DMAMUX_RGSR_OF2_Pos)   /*!< 0x00000004 */
2710 #define DMAMUX_RGSR_OF2                        DMAMUX_RGSR_OF2_Msk              /*!< Overrun flag 2                       */
2711 #define DMAMUX_RGSR_OF3_Pos                    (3U)
2712 #define DMAMUX_RGSR_OF3_Msk                    (0x1UL << DMAMUX_RGSR_OF3_Pos)   /*!< 0x00000008 */
2713 #define DMAMUX_RGSR_OF3                        DMAMUX_RGSR_OF3_Msk              /*!< Overrun flag 3                       */
2714 
2715 /********************  Bits definition for DMAMUX_RGCFR register  **************/
2716 #define DMAMUX_RGCFR_COF0_Pos                  (0U)
2717 #define DMAMUX_RGCFR_COF0_Msk                  (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
2718 #define DMAMUX_RGCFR_COF0                      DMAMUX_RGCFR_COF0_Msk            /*!< Clear Overrun flag 0                 */
2719 #define DMAMUX_RGCFR_COF1_Pos                  (1U)
2720 #define DMAMUX_RGCFR_COF1_Msk                  (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
2721 #define DMAMUX_RGCFR_COF1                      DMAMUX_RGCFR_COF1_Msk            /*!< Clear Overrun flag 1                 */
2722 #define DMAMUX_RGCFR_COF2_Pos                  (2U)
2723 #define DMAMUX_RGCFR_COF2_Msk                  (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
2724 #define DMAMUX_RGCFR_COF2                      DMAMUX_RGCFR_COF2_Msk            /*!< Clear Overrun flag 2                 */
2725 #define DMAMUX_RGCFR_COF3_Pos                  (3U)
2726 #define DMAMUX_RGCFR_COF3_Msk                  (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
2727 #define DMAMUX_RGCFR_COF3                      DMAMUX_RGCFR_COF3_Msk            /*!< Clear Overrun flag 3                 */
2728 
2729 /*****************  Bits definition for DMAMUX_IPHW_CFGR2 register  ************/
2730 #define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos       (0U)
2731 #define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk       (0xFFUL << DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos) /*!< 0x000000FF */
2732 #define DMAMUX_IPHW_CFGR2_NB_EXT_REQ           DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk /*!< Number of external request sources   */
2733 
2734 /*****************  Bits definition for DMAMUX_IPHW_CFGR1 register  ************/
2735 #define DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos       (0U)
2736 #define DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk       (0xFFUL << DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos) /*!< 0x000000FF */
2737 #define DMAMUX_IPHW_CFGR1_NB_STREAMS           DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk /*!< Number of DMA streams                */
2738 
2739 #define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos    (8U)
2740 #define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk    (0xFFUL << DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos) /*!< 0x0000FF00 */
2741 #define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ        DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk /*!< Number of peripheral requests     */
2742 
2743 #define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos     (16U)
2744 #define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk     (0xFFUL << DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos) /*!< 0x00FF0000 */
2745 #define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG         DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk /*!< Number of synchronization triggers */
2746 
2747 #define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos       (24U)
2748 #define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk       (0xFFUL << DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos) /*!< 0xFF000000 */
2749 #define DMAMUX_IPHW_CFGR1_NB_REQ_GEN           DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk /*!< Number of request generation blocks  */
2750 
2751 /******************************************************************************/
2752 /*                                                                            */
2753 /*                    External Interrupt/Event Controller                     */
2754 /*                                                                            */
2755 /******************************************************************************/
2756 /******************  Bit definition for EXTI_RTSR1 register  *******************/
2757 #define EXTI_RTSR1_TR_Pos          (0U)
2758 #define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */
2759 #define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */
2760 #define EXTI_RTSR1_TR0_Pos         (0U)
2761 #define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */
2762 #define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */
2763 #define EXTI_RTSR1_TR1_Pos         (1U)
2764 #define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */
2765 #define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */
2766 #define EXTI_RTSR1_TR2_Pos         (2U)
2767 #define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */
2768 #define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */
2769 #define EXTI_RTSR1_TR3_Pos         (3U)
2770 #define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */
2771 #define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */
2772 #define EXTI_RTSR1_TR4_Pos         (4U)
2773 #define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */
2774 #define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */
2775 #define EXTI_RTSR1_TR5_Pos         (5U)
2776 #define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */
2777 #define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */
2778 #define EXTI_RTSR1_TR6_Pos         (6U)
2779 #define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */
2780 #define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */
2781 #define EXTI_RTSR1_TR7_Pos         (7U)
2782 #define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */
2783 #define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */
2784 #define EXTI_RTSR1_TR8_Pos         (8U)
2785 #define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */
2786 #define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */
2787 #define EXTI_RTSR1_TR9_Pos         (9U)
2788 #define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */
2789 #define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */
2790 #define EXTI_RTSR1_TR10_Pos        (10U)
2791 #define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */
2792 #define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */
2793 #define EXTI_RTSR1_TR11_Pos        (11U)
2794 #define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */
2795 #define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */
2796 #define EXTI_RTSR1_TR12_Pos        (12U)
2797 #define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */
2798 #define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */
2799 #define EXTI_RTSR1_TR13_Pos        (13U)
2800 #define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */
2801 #define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */
2802 #define EXTI_RTSR1_TR14_Pos        (14U)
2803 #define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */
2804 #define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */
2805 #define EXTI_RTSR1_TR15_Pos        (15U)
2806 #define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */
2807 #define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */
2808 #define EXTI_RTSR1_TR16_Pos        (16U)
2809 #define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */
2810 #define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */
2811 #define EXTI_RTSR1_TR17_Pos        (17U)
2812 #define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */
2813 #define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */
2814 #define EXTI_RTSR1_TR18_Pos        (18U)
2815 #define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */
2816 #define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */
2817 #define EXTI_RTSR1_TR19_Pos        (19U)
2818 #define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */
2819 #define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */
2820 #define EXTI_RTSR1_TR20_Pos        (20U)
2821 #define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */
2822 #define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */
2823 #define EXTI_RTSR1_TR21_Pos        (21U)
2824 #define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */
2825 #define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */
2826 
2827 /******************  Bit definition for EXTI_FTSR1 register  *******************/
2828 #define EXTI_FTSR1_TR_Pos          (0U)
2829 #define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */
2830 #define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */
2831 #define EXTI_FTSR1_TR0_Pos         (0U)
2832 #define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */
2833 #define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */
2834 #define EXTI_FTSR1_TR1_Pos         (1U)
2835 #define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */
2836 #define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */
2837 #define EXTI_FTSR1_TR2_Pos         (2U)
2838 #define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */
2839 #define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */
2840 #define EXTI_FTSR1_TR3_Pos         (3U)
2841 #define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */
2842 #define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */
2843 #define EXTI_FTSR1_TR4_Pos         (4U)
2844 #define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */
2845 #define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */
2846 #define EXTI_FTSR1_TR5_Pos         (5U)
2847 #define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */
2848 #define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */
2849 #define EXTI_FTSR1_TR6_Pos         (6U)
2850 #define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */
2851 #define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */
2852 #define EXTI_FTSR1_TR7_Pos         (7U)
2853 #define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */
2854 #define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */
2855 #define EXTI_FTSR1_TR8_Pos         (8U)
2856 #define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */
2857 #define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */
2858 #define EXTI_FTSR1_TR9_Pos         (9U)
2859 #define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */
2860 #define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */
2861 #define EXTI_FTSR1_TR10_Pos        (10U)
2862 #define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */
2863 #define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */
2864 #define EXTI_FTSR1_TR11_Pos        (11U)
2865 #define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */
2866 #define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */
2867 #define EXTI_FTSR1_TR12_Pos        (12U)
2868 #define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */
2869 #define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */
2870 #define EXTI_FTSR1_TR13_Pos        (13U)
2871 #define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */
2872 #define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */
2873 #define EXTI_FTSR1_TR14_Pos        (14U)
2874 #define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */
2875 #define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */
2876 #define EXTI_FTSR1_TR15_Pos        (15U)
2877 #define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */
2878 #define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */
2879 #define EXTI_FTSR1_TR16_Pos        (16U)
2880 #define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */
2881 #define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */
2882 #define EXTI_FTSR1_TR17_Pos        (17U)
2883 #define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */
2884 #define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */
2885 #define EXTI_FTSR1_TR18_Pos        (18U)
2886 #define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */
2887 #define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */
2888 #define EXTI_FTSR1_TR19_Pos        (19U)
2889 #define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */
2890 #define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */
2891 #define EXTI_FTSR1_TR20_Pos        (20U)
2892 #define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */
2893 #define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */
2894 #define EXTI_FTSR1_TR21_Pos        (21U)
2895 #define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */
2896 #define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */
2897 
2898 /******************  Bit definition for EXTI_SWIER1 register  ******************/
2899 #define EXTI_SWIER1_SWIER0_Pos     (0U)
2900 #define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */
2901 #define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */
2902 #define EXTI_SWIER1_SWIER1_Pos     (1U)
2903 #define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */
2904 #define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */
2905 #define EXTI_SWIER1_SWIER2_Pos     (2U)
2906 #define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */
2907 #define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */
2908 #define EXTI_SWIER1_SWIER3_Pos     (3U)
2909 #define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */
2910 #define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */
2911 #define EXTI_SWIER1_SWIER4_Pos     (4U)
2912 #define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */
2913 #define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */
2914 #define EXTI_SWIER1_SWIER5_Pos     (5U)
2915 #define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */
2916 #define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */
2917 #define EXTI_SWIER1_SWIER6_Pos     (6U)
2918 #define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */
2919 #define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */
2920 #define EXTI_SWIER1_SWIER7_Pos     (7U)
2921 #define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */
2922 #define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */
2923 #define EXTI_SWIER1_SWIER8_Pos     (8U)
2924 #define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */
2925 #define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */
2926 #define EXTI_SWIER1_SWIER9_Pos     (9U)
2927 #define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */
2928 #define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */
2929 #define EXTI_SWIER1_SWIER10_Pos    (10U)
2930 #define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */
2931 #define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */
2932 #define EXTI_SWIER1_SWIER11_Pos    (11U)
2933 #define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */
2934 #define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */
2935 #define EXTI_SWIER1_SWIER12_Pos    (12U)
2936 #define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */
2937 #define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */
2938 #define EXTI_SWIER1_SWIER13_Pos    (13U)
2939 #define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */
2940 #define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */
2941 #define EXTI_SWIER1_SWIER14_Pos    (14U)
2942 #define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */
2943 #define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */
2944 #define EXTI_SWIER1_SWIER15_Pos    (15U)
2945 #define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */
2946 #define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */
2947 #define EXTI_SWIER1_SWIER16_Pos    (16U)
2948 #define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */
2949 #define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */
2950 #define EXTI_SWIER1_SWIER17_Pos    (17U)
2951 #define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */
2952 #define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */
2953 #define EXTI_SWIER1_SWIER18_Pos    (18U)
2954 #define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */
2955 #define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */
2956 #define EXTI_SWIER1_SWIER19_Pos    (19U)
2957 #define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */
2958 #define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */
2959 #define EXTI_SWIER1_SWIER20_Pos    (20U)
2960 #define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */
2961 #define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */
2962 #define EXTI_SWIER1_SWIER21_Pos    (21U)
2963 #define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */
2964 #define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */
2965 
2966 /*******************  Bit definition for EXTI_RPR1 register  ******************/
2967 #define EXTI_RPR1_RPIF0_Pos          (0U)
2968 #define EXTI_RPR1_RPIF0_Msk          (0x1UL << EXTI_RPR1_RPIF0_Pos)            /*!< 0x00000001 */
2969 #define EXTI_RPR1_RPIF0              EXTI_RPR1_RPIF0_Msk                       /*!< Rising Pending Interrupt Flag on line 0 */
2970 #define EXTI_RPR1_RPIF1_Pos          (1U)
2971 #define EXTI_RPR1_RPIF1_Msk          (0x1UL << EXTI_RPR1_RPIF1_Pos)            /*!< 0x00000002 */
2972 #define EXTI_RPR1_RPIF1              EXTI_RPR1_RPIF1_Msk                       /*!< Rising Pending Interrupt Flag on line 1 */
2973 #define EXTI_RPR1_RPIF2_Pos          (2U)
2974 #define EXTI_RPR1_RPIF2_Msk          (0x1UL << EXTI_RPR1_RPIF2_Pos)            /*!< 0x00000004 */
2975 #define EXTI_RPR1_RPIF2              EXTI_RPR1_RPIF2_Msk                       /*!< Rising Pending Interrupt Flag on line 2 */
2976 #define EXTI_RPR1_RPIF3_Pos          (3U)
2977 #define EXTI_RPR1_RPIF3_Msk          (0x1UL << EXTI_RPR1_RPIF3_Pos)            /*!< 0x00000008 */
2978 #define EXTI_RPR1_RPIF3              EXTI_RPR1_RPIF3_Msk                       /*!< Rising Pending Interrupt Flag on line 3 */
2979 #define EXTI_RPR1_RPIF4_Pos          (4U)
2980 #define EXTI_RPR1_RPIF4_Msk          (0x1UL << EXTI_RPR1_RPIF4_Pos)            /*!< 0x00000010 */
2981 #define EXTI_RPR1_RPIF4              EXTI_RPR1_RPIF4_Msk                       /*!< Rising Pending Interrupt Flag on line 4 */
2982 #define EXTI_RPR1_RPIF5_Pos          (5U)
2983 #define EXTI_RPR1_RPIF5_Msk          (0x1UL << EXTI_RPR1_RPIF5_Pos)            /*!< 0x00000020 */
2984 #define EXTI_RPR1_RPIF5              EXTI_RPR1_RPIF5_Msk                       /*!< Rising Pending Interrupt Flag on line 5 */
2985 #define EXTI_RPR1_RPIF6_Pos          (6U)
2986 #define EXTI_RPR1_RPIF6_Msk          (0x1UL << EXTI_RPR1_RPIF6_Pos)            /*!< 0x00000040 */
2987 #define EXTI_RPR1_RPIF6              EXTI_RPR1_RPIF6_Msk                       /*!< Rising Pending Interrupt Flag on line 6 */
2988 #define EXTI_RPR1_RPIF7_Pos          (7U)
2989 #define EXTI_RPR1_RPIF7_Msk          (0x1UL << EXTI_RPR1_RPIF7_Pos)            /*!< 0x00000080 */
2990 #define EXTI_RPR1_RPIF7              EXTI_RPR1_RPIF7_Msk                       /*!< Rising Pending Interrupt Flag on line 7 */
2991 #define EXTI_RPR1_RPIF8_Pos          (8U)
2992 #define EXTI_RPR1_RPIF8_Msk          (0x1UL << EXTI_RPR1_RPIF8_Pos)            /*!< 0x00000100 */
2993 #define EXTI_RPR1_RPIF8              EXTI_RPR1_RPIF8_Msk                       /*!< Rising Pending Interrupt Flag on line 8 */
2994 #define EXTI_RPR1_RPIF9_Pos          (9U)
2995 #define EXTI_RPR1_RPIF9_Msk          (0x1UL << EXTI_RPR1_RPIF9_Pos)            /*!< 0x00000200 */
2996 #define EXTI_RPR1_RPIF9              EXTI_RPR1_RPIF9_Msk                       /*!< Rising Pending Interrupt Flag on line 9 */
2997 #define EXTI_RPR1_RPIF10_Pos         (10U)
2998 #define EXTI_RPR1_RPIF10_Msk         (0x1UL << EXTI_RPR1_RPIF10_Pos)           /*!< 0x00000400 */
2999 #define EXTI_RPR1_RPIF10             EXTI_RPR1_RPIF10_Msk                      /*!< Rising Pending Interrupt Flag on line 10 */
3000 #define EXTI_RPR1_RPIF11_Pos         (11U)
3001 #define EXTI_RPR1_RPIF11_Msk         (0x1UL << EXTI_RPR1_RPIF11_Pos)           /*!< 0x00000800 */
3002 #define EXTI_RPR1_RPIF11             EXTI_RPR1_RPIF11_Msk                      /*!< Rising Pending Interrupt Flag on line 11 */
3003 #define EXTI_RPR1_RPIF12_Pos         (12U)
3004 #define EXTI_RPR1_RPIF12_Msk         (0x1UL << EXTI_RPR1_RPIF12_Pos)           /*!< 0x00001000 */
3005 #define EXTI_RPR1_RPIF12             EXTI_RPR1_RPIF12_Msk                      /*!< Rising Pending Interrupt Flag on line 12 */
3006 #define EXTI_RPR1_RPIF13_Pos         (13U)
3007 #define EXTI_RPR1_RPIF13_Msk         (0x1UL << EXTI_RPR1_RPIF13_Pos)           /*!< 0x00002000 */
3008 #define EXTI_RPR1_RPIF13             EXTI_RPR1_RPIF13_Msk                      /*!< Rising Pending Interrupt Flag on line 13 */
3009 #define EXTI_RPR1_RPIF14_Pos         (14U)
3010 #define EXTI_RPR1_RPIF14_Msk         (0x1UL << EXTI_RPR1_RPIF14_Pos)           /*!< 0x00004000 */
3011 #define EXTI_RPR1_RPIF14             EXTI_RPR1_RPIF14_Msk                      /*!< Rising Pending Interrupt Flag on line 14 */
3012 #define EXTI_RPR1_RPIF15_Pos         (15U)
3013 #define EXTI_RPR1_RPIF15_Msk         (0x1UL << EXTI_RPR1_RPIF15_Pos)           /*!< 0x00008000 */
3014 #define EXTI_RPR1_RPIF15             EXTI_RPR1_RPIF15_Msk                      /*!< Rising Pending Interrupt Flag on line 15 */
3015 #define EXTI_RPR1_RPIF16_Pos         (16U)
3016 #define EXTI_RPR1_RPIF16_Msk         (0x1UL << EXTI_RPR1_RPIF16_Pos)           /*!< 0x00010000 */
3017 #define EXTI_RPR1_RPIF16             EXTI_RPR1_RPIF16_Msk                      /*!< Rising Pending Interrupt Flag on line 16 */
3018 #define EXTI_RPR1_RPIF17_Pos         (17U)
3019 #define EXTI_RPR1_RPIF17_Msk         (0x1UL << EXTI_RPR1_RPIF17_Pos)           /*!< 0x00020000 */
3020 #define EXTI_RPR1_RPIF17             EXTI_RPR1_RPIF17_Msk                      /*!< Rising Pending Interrupt Flag on line 17 */
3021 #define EXTI_RPR1_RPIF18_Pos         (18U)
3022 #define EXTI_RPR1_RPIF18_Msk         (0x1UL << EXTI_RPR1_RPIF18_Pos)           /*!< 0x00040000 */
3023 #define EXTI_RPR1_RPIF18             EXTI_RPR1_RPIF18_Msk                      /*!< Rising Pending Interrupt Flag on line 18 */
3024 #define EXTI_RPR1_RPIF19_Pos         (19U)
3025 #define EXTI_RPR1_RPIF19_Msk         (0x1UL << EXTI_RPR1_RPIF19_Pos)           /*!< 0x00080000 */
3026 #define EXTI_RPR1_RPIF19             EXTI_RPR1_RPIF19_Msk                      /*!< Rising Pending Interrupt Flag on line 19 */
3027 #define EXTI_RPR1_RPIF20_Pos         (20U)
3028 #define EXTI_RPR1_RPIF20_Msk         (0x1UL << EXTI_RPR1_RPIF20_Pos)           /*!< 0x00100000 */
3029 #define EXTI_RPR1_RPIF20             EXTI_RPR1_RPIF20_Msk                      /*!< Rising Pending Interrupt Flag on line 20 */
3030 #define EXTI_RPR1_RPIF21_Pos         (21U)
3031 #define EXTI_RPR1_RPIF21_Msk         (0x1UL << EXTI_RPR1_RPIF21_Pos)           /*!< 0x00200000 */
3032 #define EXTI_RPR1_RPIF21             EXTI_RPR1_RPIF21_Msk                      /*!< Rising Pending Interrupt Flag on line 21 */
3033 
3034 /*******************  Bit definition for EXTI_FPR1 register  ******************/
3035 #define EXTI_FPR1_FPIF0_Pos          (0U)
3036 #define EXTI_FPR1_FPIF0_Msk          (0x1UL << EXTI_FPR1_FPIF0_Pos)            /*!< 0x00000001 */
3037 #define EXTI_FPR1_FPIF0              EXTI_FPR1_FPIF0_Msk                       /*!< Falling Pending Interrupt Flag on line 0 */
3038 #define EXTI_FPR1_FPIF1_Pos          (1U)
3039 #define EXTI_FPR1_FPIF1_Msk          (0x1UL << EXTI_FPR1_FPIF1_Pos)            /*!< 0x00000002 */
3040 #define EXTI_FPR1_FPIF1              EXTI_FPR1_FPIF1_Msk                       /*!< Falling Pending Interrupt Flag on line 1 */
3041 #define EXTI_FPR1_FPIF2_Pos          (2U)
3042 #define EXTI_FPR1_FPIF2_Msk          (0x1UL << EXTI_FPR1_FPIF2_Pos)            /*!< 0x00000004 */
3043 #define EXTI_FPR1_FPIF2              EXTI_FPR1_FPIF2_Msk                       /*!< Falling Pending Interrupt Flag on line 2 */
3044 #define EXTI_FPR1_FPIF3_Pos          (3U)
3045 #define EXTI_FPR1_FPIF3_Msk          (0x1UL << EXTI_FPR1_FPIF3_Pos)            /*!< 0x00000008 */
3046 #define EXTI_FPR1_FPIF3              EXTI_FPR1_FPIF3_Msk                       /*!< Falling Pending Interrupt Flag on line 3 */
3047 #define EXTI_FPR1_FPIF4_Pos          (4U)
3048 #define EXTI_FPR1_FPIF4_Msk          (0x1UL << EXTI_FPR1_FPIF4_Pos)            /*!< 0x00000010 */
3049 #define EXTI_FPR1_FPIF4              EXTI_FPR1_FPIF4_Msk                       /*!< Falling Pending Interrupt Flag on line 4 */
3050 #define EXTI_FPR1_FPIF5_Pos          (5U)
3051 #define EXTI_FPR1_FPIF5_Msk          (0x1UL << EXTI_FPR1_FPIF5_Pos)            /*!< 0x00000020 */
3052 #define EXTI_FPR1_FPIF5              EXTI_FPR1_FPIF5_Msk                       /*!< Falling Pending Interrupt Flag on line 5 */
3053 #define EXTI_FPR1_FPIF6_Pos          (6U)
3054 #define EXTI_FPR1_FPIF6_Msk          (0x1UL << EXTI_FPR1_FPIF6_Pos)            /*!< 0x00000040 */
3055 #define EXTI_FPR1_FPIF6              EXTI_FPR1_FPIF6_Msk                       /*!< Falling Pending Interrupt Flag on line 6 */
3056 #define EXTI_FPR1_FPIF7_Pos          (7U)
3057 #define EXTI_FPR1_FPIF7_Msk           (0x1UL << EXTI_FPR1_FPIF7_Pos)            /*!< 0x00000080 */
3058 #define EXTI_FPR1_FPIF7              EXTI_FPR1_FPIF7_Msk                       /*!< Falling Pending Interrupt Flag on line 7 */
3059 #define EXTI_FPR1_FPIF8_Pos          (8U)
3060 #define EXTI_FPR1_FPIF8_Msk          (0x1UL << EXTI_FPR1_FPIF8_Pos)            /*!< 0x00000100 */
3061 #define EXTI_FPR1_FPIF8              EXTI_FPR1_FPIF8_Msk                       /*!< Falling Pending Interrupt Flag on line 8 */
3062 #define EXTI_FPR1_FPIF9_Pos          (9U)
3063 #define EXTI_FPR1_FPIF9_Msk          (0x1UL << EXTI_FPR1_FPIF9_Pos)            /*!< 0x00000200 */
3064 #define EXTI_FPR1_FPIF9              EXTI_FPR1_FPIF9_Msk                       /*!< Falling Pending Interrupt Flag on line 9 */
3065 #define EXTI_FPR1_FPIF10_Pos         (10U)
3066 #define EXTI_FPR1_FPIF10_Msk         (0x1UL << EXTI_FPR1_FPIF10_Pos)           /*!< 0x00000400 */
3067 #define EXTI_FPR1_FPIF10             EXTI_FPR1_FPIF10_Msk                      /*!< Falling Pending Interrupt Flag on line 10 */
3068 #define EXTI_FPR1_FPIF11_Pos         (11U)
3069 #define EXTI_FPR1_FPIF11_Msk         (0x1UL << EXTI_FPR1_FPIF11_Pos)           /*!< 0x00000800 */
3070 #define EXTI_FPR1_FPIF11             EXTI_FPR1_FPIF11_Msk                      /*!< Falling Pending Interrupt Flag on line 11 */
3071 #define EXTI_FPR1_FPIF12_Pos         (12U)
3072 #define EXTI_FPR1_FPIF12_Msk         (0x1UL << EXTI_FPR1_FPIF12_Pos)           /*!< 0x00001000 */
3073 #define EXTI_FPR1_FPIF12             EXTI_FPR1_FPIF12_Msk                      /*!< Falling Pending Interrupt Flag on line 12 */
3074 #define EXTI_FPR1_FPIF13_Pos         (13U)
3075 #define EXTI_FPR1_FPIF13_Msk         (0x1UL << EXTI_FPR1_FPIF13_Pos)           /*!< 0x00020000 */
3076 #define EXTI_FPR1_FPIF13             EXTI_FPR1_FPIF13_Msk                      /*!< Falling Pending Interrupt Flag on line 13 */
3077 #define EXTI_FPR1_FPIF14_Pos         (14U)
3078 #define EXTI_FPR1_FPIF14_Msk         (0x1UL << EXTI_FPR1_FPIF14_Pos)           /*!< 0x00040000 */
3079 #define EXTI_FPR1_FPIF14             EXTI_FPR1_FPIF14_Msk                      /*!< Falling Pending Interrupt Flag on line 14 */
3080 #define EXTI_FPR1_FPIF15_Pos         (15U)
3081 #define EXTI_FPR1_FPIF15_Msk         (0x1UL << EXTI_FPR1_FPIF15_Pos)           /*!< 0x00080000 */
3082 #define EXTI_FPR1_FPIF15             EXTI_FPR1_FPIF15_Msk                      /*!< Falling Pending Interrupt Flag on line 15 */
3083 #define EXTI_FPR1_FPIF16_Pos         (16U)
3084 #define EXTI_FPR1_FPIF16_Msk         (0x1UL << EXTI_FPR1_FPIF16_Pos)           /*!< 0x00010000 */
3085 #define EXTI_FPR1_FPIF16             EXTI_FPR1_FPIF16_Msk                      /*!< Falling Pending Interrupt Flag on line 16 */
3086 #define EXTI_FPR1_FPIF17_Pos         (17U)
3087 #define EXTI_FPR1_FPIF17_Msk         (0x1UL << EXTI_FPR1_FPIF17_Pos)           /*!< 0x00020000 */
3088 #define EXTI_FPR1_FPIF17             EXTI_FPR1_FPIF17_Msk                      /*!< Falling Pending Interrupt Flag on line 17 */
3089 #define EXTI_FPR1_FPIF18_Pos         (18U)
3090 #define EXTI_FPR1_FPIF18_Msk         (0x1UL << EXTI_FPR1_FPIF18_Pos)           /*!< 0x00040000 */
3091 #define EXTI_FPR1_FPIF18             EXTI_FPR1_FPIF18_Msk                      /*!< Falling Pending Interrupt Flag on line 18 */
3092 #define EXTI_FPR1_FPIF19_Pos         (19U)
3093 #define EXTI_FPR1_FPIF19_Msk         (0x1UL << EXTI_FPR1_FPIF19_Pos)           /*!< 0x00080000 */
3094 #define EXTI_FPR1_FPIF19             EXTI_FPR1_FPIF19_Msk                      /*!< Falling Pending Interrupt Flag on line 19 */
3095 #define EXTI_FPR1_FPIF20_Pos         (20U)
3096 #define EXTI_FPR1_FPIF20_Msk         (0x1UL << EXTI_FPR1_FPIF20_Pos)           /*!< 0x00100000 */
3097 #define EXTI_FPR1_FPIF20             EXTI_FPR1_FPIF20_Msk                      /*!< Falling Pending Interrupt Flag on line 20 */
3098 #define EXTI_FPR1_FPIF21_Pos         (21U)
3099 #define EXTI_FPR1_FPIF21_Msk         (0x1UL << EXTI_FPR1_FPIF21_Pos)           /*!< 0x00200000 */
3100 #define EXTI_FPR1_FPIF21             EXTI_FPR1_FPIF21_Msk                      /*!< Falling Pending Interrupt Flag on line 21 */
3101 
3102 /*****************  Bit definition for EXTI_EXTICR1 register  **************/
3103 #define EXTI_EXTICR1_EXTI0_Pos       (0U)
3104 #define EXTI_EXTICR1_EXTI0_Msk       (0xFFUL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x000000FF */
3105 #define EXTI_EXTICR1_EXTI0           EXTI_EXTICR1_EXTI0_Msk                    /*!< EXTI 0 configuration */
3106 #define EXTI_EXTICR1_EXTI0_0         (0x1UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000001 */
3107 #define EXTI_EXTICR1_EXTI0_1         (0x2UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000002 */
3108 #define EXTI_EXTICR1_EXTI0_2         (0x4UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000004 */
3109 #define EXTI_EXTICR1_EXTI0_3         (0x8UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000008 */
3110 #define EXTI_EXTICR1_EXTI0_4         (0x10UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000010 */
3111 #define EXTI_EXTICR1_EXTI0_5         (0x20UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000020 */
3112 #define EXTI_EXTICR1_EXTI0_6         (0x40UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000040 */
3113 #define EXTI_EXTICR1_EXTI0_7         (0x80UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000080 */
3114 #define EXTI_EXTICR1_EXTI1_Pos       (8U)
3115 #define EXTI_EXTICR1_EXTI1_Msk       (0xFFUL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x0000FF00 */
3116 #define EXTI_EXTICR1_EXTI1           EXTI_EXTICR1_EXTI1_Msk                    /*!< EXTI 1 configuration */
3117 #define EXTI_EXTICR1_EXTI1_0         (0x1UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000100 */
3118 #define EXTI_EXTICR1_EXTI1_1         (0x2UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000200 */
3119 #define EXTI_EXTICR1_EXTI1_2         (0x4UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000400 */
3120 #define EXTI_EXTICR1_EXTI1_3         (0x8UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000800 */
3121 #define EXTI_EXTICR1_EXTI1_4         (0x10UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00001000 */
3122 #define EXTI_EXTICR1_EXTI1_5         (0x20UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00002000 */
3123 #define EXTI_EXTICR1_EXTI1_6         (0x40UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00004000 */
3124 #define EXTI_EXTICR1_EXTI1_7         (0x80UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00008000 */
3125 #define EXTI_EXTICR1_EXTI2_Pos       (16U)
3126 #define EXTI_EXTICR1_EXTI2_Msk       (0xFFUL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00FF0000 */
3127 #define EXTI_EXTICR1_EXTI2           EXTI_EXTICR1_EXTI2_Msk                    /*!< EXTI 2 configuration */
3128 #define EXTI_EXTICR1_EXTI2_0         (0x1UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00010000 */
3129 #define EXTI_EXTICR1_EXTI2_1         (0x2UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00020000 */
3130 #define EXTI_EXTICR1_EXTI2_2         (0x4UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00040000 */
3131 #define EXTI_EXTICR1_EXTI2_3         (0x8UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00080000 */
3132 #define EXTI_EXTICR1_EXTI2_4         (0x10UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00100000 */
3133 #define EXTI_EXTICR1_EXTI2_5         (0x20UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00200000 */
3134 #define EXTI_EXTICR1_EXTI2_6         (0x40UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00400000 */
3135 #define EXTI_EXTICR1_EXTI2_7         (0x80UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00800000 */
3136 #define EXTI_EXTICR1_EXTI3_Pos       (24U)
3137 #define EXTI_EXTICR1_EXTI3_Msk       (0xFFUL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0xFF000000 */
3138 #define EXTI_EXTICR1_EXTI3           EXTI_EXTICR1_EXTI3_Msk                    /*!< EXTI 3 configuration */
3139 #define EXTI_EXTICR1_EXTI3_0         (0x1UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x01000000 */
3140 #define EXTI_EXTICR1_EXTI3_1         (0x2UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x02000000 */
3141 #define EXTI_EXTICR1_EXTI3_2         (0x4UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x04000000 */
3142 #define EXTI_EXTICR1_EXTI3_3         (0x8UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x08000000 */
3143 #define EXTI_EXTICR1_EXTI3_4         (0x10UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x10000000 */
3144 #define EXTI_EXTICR1_EXTI3_5         (0x20UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x20000000 */
3145 #define EXTI_EXTICR1_EXTI3_6         (0x40UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x40000000 */
3146 #define EXTI_EXTICR1_EXTI3_7         (0x80UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x80000000 */
3147 
3148 /*****************  Bit definition for EXTI_EXTICR2 register  **************/
3149 #define EXTI_EXTICR2_EXTI4_Pos       (0U)
3150 #define EXTI_EXTICR2_EXTI4_Msk       (0xFFUL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x000000FF */
3151 #define EXTI_EXTICR2_EXTI4           EXTI_EXTICR2_EXTI4_Msk                    /*!< EXTI 4 configuration */
3152 #define EXTI_EXTICR2_EXTI4_0         (0x1UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000001 */
3153 #define EXTI_EXTICR2_EXTI4_1         (0x2UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000002 */
3154 #define EXTI_EXTICR2_EXTI4_2         (0x4UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000004 */
3155 #define EXTI_EXTICR2_EXTI4_3         (0x8UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000008 */
3156 #define EXTI_EXTICR2_EXTI4_4         (0x10UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000010 */
3157 #define EXTI_EXTICR2_EXTI4_5         (0x20UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000020 */
3158 #define EXTI_EXTICR2_EXTI4_6         (0x40UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000040 */
3159 #define EXTI_EXTICR2_EXTI4_7         (0x80UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000080 */
3160 #define EXTI_EXTICR2_EXTI5_Pos       (8U)
3161 #define EXTI_EXTICR2_EXTI5_Msk       (0xFFUL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x0000FF00 */
3162 #define EXTI_EXTICR2_EXTI5           EXTI_EXTICR2_EXTI5_Msk                    /*!< EXTI 5 configuration */
3163 #define EXTI_EXTICR2_EXTI5_0         (0x1UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000100 */
3164 #define EXTI_EXTICR2_EXTI5_1         (0x2UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000200 */
3165 #define EXTI_EXTICR2_EXTI5_2         (0x4UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000400 */
3166 #define EXTI_EXTICR2_EXTI5_3         (0x8UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000800 */
3167 #define EXTI_EXTICR2_EXTI5_4         (0x10UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00001000 */
3168 #define EXTI_EXTICR2_EXTI5_5         (0x20UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00002000 */
3169 #define EXTI_EXTICR2_EXTI5_6         (0x40UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00004000 */
3170 #define EXTI_EXTICR2_EXTI5_7         (0x80UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00008000 */
3171 #define EXTI_EXTICR2_EXTI6_Pos       (16U)
3172 #define EXTI_EXTICR2_EXTI6_Msk       (0xFFUL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00FF0000 */
3173 #define EXTI_EXTICR2_EXTI6           EXTI_EXTICR2_EXTI6_Msk                    /*!< EXTI 6 configuration */
3174 #define EXTI_EXTICR2_EXTI6_0         (0x1UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00010000 */
3175 #define EXTI_EXTICR2_EXTI6_1         (0x2UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00020000 */
3176 #define EXTI_EXTICR2_EXTI6_2         (0x4UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00040000 */
3177 #define EXTI_EXTICR2_EXTI6_3         (0x8UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00080000 */
3178 #define EXTI_EXTICR2_EXTI6_4         (0x10UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00100000 */
3179 #define EXTI_EXTICR2_EXTI6_5         (0x20UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00200000 */
3180 #define EXTI_EXTICR2_EXTI6_6         (0x40UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00400000 */
3181 #define EXTI_EXTICR2_EXTI6_7         (0x80UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00800000 */
3182 #define EXTI_EXTICR2_EXTI7_Pos       (24U)
3183 #define EXTI_EXTICR2_EXTI7_Msk       (0xFFUL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0xFF000000 */
3184 #define EXTI_EXTICR2_EXTI7           EXTI_EXTICR2_EXTI7_Msk                    /*!< EXTI 7 configuration */
3185 #define EXTI_EXTICR2_EXTI7_0         (0x1UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x01000000 */
3186 #define EXTI_EXTICR2_EXTI7_1         (0x2UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x02000000 */
3187 #define EXTI_EXTICR2_EXTI7_2         (0x4UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x04000000 */
3188 #define EXTI_EXTICR2_EXTI7_3         (0x8UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x08000000 */
3189 #define EXTI_EXTICR2_EXTI7_4         (0x10UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x10000000 */
3190 #define EXTI_EXTICR2_EXTI7_5         (0x20UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x20000000 */
3191 #define EXTI_EXTICR2_EXTI7_6         (0x40UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x40000000 */
3192 #define EXTI_EXTICR2_EXTI7_7         (0x80UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x80000000 */
3193 
3194 /*****************  Bit definition for EXTI_EXTICR3 register  **************/
3195 #define EXTI_EXTICR3_EXTI8_Pos       (0U)
3196 #define EXTI_EXTICR3_EXTI8_Msk       (0xFFUL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x000000FF */
3197 #define EXTI_EXTICR3_EXTI8           EXTI_EXTICR3_EXTI8_Msk                    /*!< EXTI 8 configuration */
3198 #define EXTI_EXTICR3_EXTI8_0         (0x1UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000001 */
3199 #define EXTI_EXTICR3_EXTI8_1         (0x2UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000002 */
3200 #define EXTI_EXTICR3_EXTI8_2         (0x4UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000004 */
3201 #define EXTI_EXTICR3_EXTI8_3         (0x8UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000008 */
3202 #define EXTI_EXTICR3_EXTI8_4         (0x10UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000010 */
3203 #define EXTI_EXTICR3_EXTI8_5         (0x20UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000020 */
3204 #define EXTI_EXTICR3_EXTI8_6         (0x40UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000040 */
3205 #define EXTI_EXTICR3_EXTI8_7         (0x80UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000080 */
3206 #define EXTI_EXTICR3_EXTI9_Pos       (8U)
3207 #define EXTI_EXTICR3_EXTI9_Msk       (0xFFUL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x0000FF00 */
3208 #define EXTI_EXTICR3_EXTI9           EXTI_EXTICR3_EXTI9_Msk                    /*!< EXTI 9 configuration */
3209 #define EXTI_EXTICR3_EXTI9_0         (0x1UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000100 */
3210 #define EXTI_EXTICR3_EXTI9_1         (0x2UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000200 */
3211 #define EXTI_EXTICR3_EXTI9_2         (0x4UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000400 */
3212 #define EXTI_EXTICR3_EXTI9_3         (0x8UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000800 */
3213 #define EXTI_EXTICR3_EXTI9_4         (0x10UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00001000 */
3214 #define EXTI_EXTICR3_EXTI9_5         (0x20UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00002000 */
3215 #define EXTI_EXTICR3_EXTI9_6         (0x40UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00004000 */
3216 #define EXTI_EXTICR3_EXTI9_7         (0x80UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00008000 */
3217 #define EXTI_EXTICR3_EXTI10_Pos      (16U)
3218 #define EXTI_EXTICR3_EXTI10_Msk      (0xFFUL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00FF0000 */
3219 #define EXTI_EXTICR3_EXTI10          EXTI_EXTICR3_EXTI10_Msk                   /*!< EXTI 10 configuration */
3220 #define EXTI_EXTICR3_EXTI10_0        (0x1UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00010000 */
3221 #define EXTI_EXTICR3_EXTI10_1        (0x2UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00020000 */
3222 #define EXTI_EXTICR3_EXTI10_2        (0x4UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00040000 */
3223 #define EXTI_EXTICR3_EXTI10_3        (0x8UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00080000 */
3224 #define EXTI_EXTICR3_EXTI10_4        (0x10UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00100000 */
3225 #define EXTI_EXTICR3_EXTI10_5        (0x20UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00200000 */
3226 #define EXTI_EXTICR3_EXTI10_6        (0x40UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00400000 */
3227 #define EXTI_EXTICR3_EXTI10_7        (0x80UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00800000 */
3228 #define EXTI_EXTICR3_EXTI11_Pos      (24U)
3229 #define EXTI_EXTICR3_EXTI11_Msk      (0xFFUL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0xFF000000 */
3230 #define EXTI_EXTICR3_EXTI11          EXTI_EXTICR3_EXTI11_Msk                   /*!< EXTI 11 configuration */
3231 #define EXTI_EXTICR3_EXTI11_0        (0x1UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x01000000 */
3232 #define EXTI_EXTICR3_EXTI11_1        (0x2UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x02000000 */
3233 #define EXTI_EXTICR3_EXTI11_2        (0x4UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x04000000 */
3234 #define EXTI_EXTICR3_EXTI11_3        (0x8UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x08000000 */
3235 #define EXTI_EXTICR3_EXTI11_4        (0x10UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x10000000 */
3236 #define EXTI_EXTICR3_EXTI11_5        (0x20UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x20000000 */
3237 #define EXTI_EXTICR3_EXTI11_6        (0x40UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x40000000 */
3238 #define EXTI_EXTICR3_EXTI11_7        (0x80UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x80000000 */
3239 
3240 /*****************  Bit definition for EXTI_EXTICR4 register  **************/
3241 #define EXTI_EXTICR4_EXTI12_Pos      (0U)
3242 #define EXTI_EXTICR4_EXTI12_Msk      (0xFFUL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x000000FF */
3243 #define EXTI_EXTICR4_EXTI12          EXTI_EXTICR4_EXTI12_Msk                   /*!< EXTI 12 configuration */
3244 #define EXTI_EXTICR4_EXTI12_0        (0x1UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000001 */
3245 #define EXTI_EXTICR4_EXTI12_1        (0x2UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000002 */
3246 #define EXTI_EXTICR4_EXTI12_2        (0x4UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000004 */
3247 #define EXTI_EXTICR4_EXTI12_3        (0x8UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000008 */
3248 #define EXTI_EXTICR4_EXTI12_4        (0x10UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000010 */
3249 #define EXTI_EXTICR4_EXTI12_5        (0x20UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000020 */
3250 #define EXTI_EXTICR4_EXTI12_6        (0x40UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000040 */
3251 #define EXTI_EXTICR4_EXTI12_7        (0x80UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000080 */
3252 #define EXTI_EXTICR4_EXTI13_Pos      (8U)
3253 #define EXTI_EXTICR4_EXTI13_Msk      (0xFFUL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x0000FF00 */
3254 #define EXTI_EXTICR4_EXTI13          EXTI_EXTICR4_EXTI13_Msk                   /*!< EXTI 13 configuration */
3255 #define EXTI_EXTICR4_EXTI13_0        (0x1UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000100 */
3256 #define EXTI_EXTICR4_EXTI13_1        (0x2UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000200 */
3257 #define EXTI_EXTICR4_EXTI13_2        (0x4UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000400 */
3258 #define EXTI_EXTICR4_EXTI13_3        (0x8UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000800 */
3259 #define EXTI_EXTICR4_EXTI13_4        (0x10UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00001000 */
3260 #define EXTI_EXTICR4_EXTI13_5        (0x20UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00002000 */
3261 #define EXTI_EXTICR4_EXTI13_6        (0x40UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00004000 */
3262 #define EXTI_EXTICR4_EXTI13_7        (0x80UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00008000 */
3263 #define EXTI_EXTICR4_EXTI14_Pos      (16U)
3264 #define EXTI_EXTICR4_EXTI14_Msk      (0xFFUL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00FF0000 */
3265 #define EXTI_EXTICR4_EXTI14          EXTI_EXTICR4_EXTI14_Msk                   /*!< EXTI 14 configuration */
3266 #define EXTI_EXTICR4_EXTI14_0        (0x1UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00010000 */
3267 #define EXTI_EXTICR4_EXTI14_1        (0x2UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00020000 */
3268 #define EXTI_EXTICR4_EXTI14_2        (0x4UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00040000 */
3269 #define EXTI_EXTICR4_EXTI14_3        (0x8UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00080000 */
3270 #define EXTI_EXTICR4_EXTI14_4        (0x10UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00100000 */
3271 #define EXTI_EXTICR4_EXTI14_5        (0x20UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00200000 */
3272 #define EXTI_EXTICR4_EXTI14_6        (0x40UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00400000 */
3273 #define EXTI_EXTICR4_EXTI14_7        (0x80UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00800000 */
3274 #define EXTI_EXTICR4_EXTI15_Pos      (24U)
3275 #define EXTI_EXTICR4_EXTI15_Msk      (0xFFUL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0xFF000000 */
3276 #define EXTI_EXTICR4_EXTI15          EXTI_EXTICR4_EXTI15_Msk                   /*!< EXTI 15 configuration */
3277 #define EXTI_EXTICR4_EXTI15_0        (0x1UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x01000000 */
3278 #define EXTI_EXTICR4_EXTI15_1        (0x2UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x02000000 */
3279 #define EXTI_EXTICR4_EXTI15_2        (0x4UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x04000000 */
3280 #define EXTI_EXTICR4_EXTI15_3        (0x8UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x08000000 */
3281 #define EXTI_EXTICR4_EXTI15_4        (0x10UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x10000000 */
3282 #define EXTI_EXTICR4_EXTI15_5        (0x20UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x20000000 */
3283 #define EXTI_EXTICR4_EXTI15_6        (0x40UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x40000000 */
3284 #define EXTI_EXTICR4_EXTI15_7        (0x80UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x80000000 */
3285 
3286 /*******************  Bit definition for EXTI_IMR1 register  *******************/
3287 #define EXTI_IMR1_IM_Pos           (0U)
3288 #define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */
3289 #define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */
3290 #define EXTI_IMR1_IM0_Pos          (0U)
3291 #define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */
3292 #define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */
3293 #define EXTI_IMR1_IM1_Pos          (1U)
3294 #define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */
3295 #define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */
3296 #define EXTI_IMR1_IM2_Pos          (2U)
3297 #define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */
3298 #define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */
3299 #define EXTI_IMR1_IM3_Pos          (3U)
3300 #define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */
3301 #define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */
3302 #define EXTI_IMR1_IM4_Pos          (4U)
3303 #define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */
3304 #define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */
3305 #define EXTI_IMR1_IM5_Pos          (5U)
3306 #define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */
3307 #define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */
3308 #define EXTI_IMR1_IM6_Pos          (6U)
3309 #define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */
3310 #define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */
3311 #define EXTI_IMR1_IM7_Pos          (7U)
3312 #define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */
3313 #define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */
3314 #define EXTI_IMR1_IM8_Pos          (8U)
3315 #define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */
3316 #define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */
3317 #define EXTI_IMR1_IM9_Pos          (9U)
3318 #define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */
3319 #define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */
3320 #define EXTI_IMR1_IM10_Pos         (10U)
3321 #define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */
3322 #define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */
3323 #define EXTI_IMR1_IM11_Pos         (11U)
3324 #define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */
3325 #define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */
3326 #define EXTI_IMR1_IM12_Pos         (12U)
3327 #define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */
3328 #define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */
3329 #define EXTI_IMR1_IM13_Pos         (13U)
3330 #define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */
3331 #define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */
3332 #define EXTI_IMR1_IM14_Pos         (14U)
3333 #define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */
3334 #define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */
3335 #define EXTI_IMR1_IM15_Pos         (15U)
3336 #define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */
3337 #define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */
3338 #define EXTI_IMR1_IM16_Pos         (16U)
3339 #define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */
3340 #define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */
3341 #define EXTI_IMR1_IM17_Pos         (17U)
3342 #define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */
3343 #define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */
3344 #define EXTI_IMR1_IM18_Pos         (18U)
3345 #define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */
3346 #define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */
3347 #define EXTI_IMR1_IM19_Pos         (19U)
3348 #define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */
3349 #define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */
3350 #define EXTI_IMR1_IM20_Pos         (20U)
3351 #define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */
3352 #define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */
3353 #define EXTI_IMR1_IM21_Pos         (21U)
3354 #define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */
3355 #define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */
3356 #define EXTI_IMR1_IM22_Pos         (22U)
3357 #define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */
3358 #define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */
3359 #define EXTI_IMR1_IM23_Pos         (23U)
3360 #define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */
3361 #define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */
3362 #define EXTI_IMR1_IM24_Pos         (24U)
3363 #define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */
3364 #define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */
3365 #define EXTI_IMR1_IM25_Pos         (25U)
3366 #define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */
3367 #define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */
3368 #define EXTI_IMR1_IM26_Pos         (26U)
3369 #define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */
3370 #define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */
3371 #define EXTI_IMR1_IM27_Pos         (27U)
3372 #define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */
3373 #define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */
3374 #define EXTI_IMR1_IM28_Pos         (28U)
3375 #define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */
3376 #define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */
3377 #define EXTI_IMR1_IM29_Pos         (29U)
3378 #define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */
3379 #define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */
3380 #define EXTI_IMR1_IM30_Pos         (30U)
3381 #define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */
3382 #define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */
3383 #define EXTI_IMR1_IM31_Pos         (31U)
3384 #define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */
3385 #define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */
3386 
3387 /*******************  Bit definition for EXTI_EMR1 register  *******************/
3388 #define EXTI_EMR1_EM_Pos           (0U)
3389 #define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */
3390 #define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */
3391 #define EXTI_EMR1_EM0_Pos          (0U)
3392 #define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */
3393 #define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */
3394 #define EXTI_EMR1_EM1_Pos          (1U)
3395 #define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */
3396 #define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */
3397 #define EXTI_EMR1_EM2_Pos          (2U)
3398 #define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */
3399 #define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */
3400 #define EXTI_EMR1_EM3_Pos          (3U)
3401 #define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */
3402 #define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */
3403 #define EXTI_EMR1_EM4_Pos          (4U)
3404 #define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */
3405 #define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */
3406 #define EXTI_EMR1_EM5_Pos          (5U)
3407 #define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */
3408 #define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */
3409 #define EXTI_EMR1_EM6_Pos          (6U)
3410 #define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */
3411 #define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */
3412 #define EXTI_EMR1_EM7_Pos          (7U)
3413 #define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */
3414 #define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */
3415 #define EXTI_EMR1_EM8_Pos          (8U)
3416 #define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */
3417 #define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */
3418 #define EXTI_EMR1_EM9_Pos          (9U)
3419 #define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */
3420 #define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */
3421 #define EXTI_EMR1_EM10_Pos         (10U)
3422 #define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */
3423 #define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */
3424 #define EXTI_EMR1_EM11_Pos         (11U)
3425 #define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */
3426 #define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */
3427 #define EXTI_EMR1_EM12_Pos         (12U)
3428 #define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */
3429 #define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */
3430 #define EXTI_EMR1_EM13_Pos         (13U)
3431 #define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */
3432 #define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */
3433 #define EXTI_EMR1_EM14_Pos         (14U)
3434 #define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */
3435 #define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */
3436 #define EXTI_EMR1_EM15_Pos         (15U)
3437 #define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */
3438 #define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */
3439 #define EXTI_EMR1_EM16_Pos         (16U)
3440 #define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */
3441 #define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */
3442 #define EXTI_EMR1_EM17_Pos         (17U)
3443 #define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */
3444 #define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */
3445 #define EXTI_EMR1_EM18_Pos         (18U)
3446 #define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */
3447 #define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */
3448 #define EXTI_EMR1_EM19_Pos         (19U)
3449 #define EXTI_EMR1_EM19_Msk         (0x1UL << EXTI_EMR1_EM19_Pos)               /*!< 0x00080000 */
3450 #define EXTI_EMR1_EM19             EXTI_EMR1_EM19_Msk                          /*!< Event Mask on line 19 */
3451 #define EXTI_EMR1_EM20_Pos         (20U)
3452 #define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */
3453 #define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */
3454 #define EXTI_EMR1_EM21_Pos         (21U)
3455 #define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */
3456 #define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */
3457 #define EXTI_EMR1_EM22_Pos         (22U)
3458 #define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */
3459 #define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */
3460 #define EXTI_EMR1_EM23_Pos         (23U)
3461 #define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */
3462 #define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */
3463 #define EXTI_EMR1_EM24_Pos         (24U)
3464 #define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */
3465 #define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */
3466 #define EXTI_EMR1_EM25_Pos         (25U)
3467 #define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */
3468 #define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */
3469 #define EXTI_EMR1_EM26_Pos         (26U)
3470 #define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */
3471 #define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */
3472 #define EXTI_EMR1_EM27_Pos         (27U)
3473 #define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */
3474 #define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */
3475 #define EXTI_EMR1_EM28_Pos         (28U)
3476 #define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */
3477 #define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */
3478 #define EXTI_EMR1_EM29_Pos         (29U)
3479 #define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */
3480 #define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */
3481 #define EXTI_EMR1_EM30_Pos         (30U)
3482 #define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */
3483 #define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */
3484 #define EXTI_EMR1_EM31_Pos         (31U)
3485 #define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */
3486 #define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */
3487 
3488 /*******************  Bit definition for EXTI_IMR2 register  *******************/
3489 #define EXTI_IMR2_IM_Pos           (0U)
3490 #define EXTI_IMR2_IM_Msk           (0x0000003FUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFF8FFF */
3491 #define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask            */
3492 #define EXTI_IMR2_IM32_Pos         (0U)
3493 #define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */
3494 #define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */
3495 #define EXTI_IMR2_IM33_Pos         (1U)
3496 #define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */
3497 #define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */
3498 #define EXTI_IMR2_IM34_Pos         (2U)
3499 #define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */
3500 #define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */
3501 #define EXTI_IMR2_IM35_Pos         (3U)
3502 #define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */
3503 #define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */
3504 #define EXTI_IMR2_IM36_Pos         (4U)
3505 #define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */
3506 #define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */
3507 #define EXTI_IMR2_IM37_Pos         (5U)
3508 #define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */
3509 #define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */
3510 
3511 /*******************  Bit definition for EXTI_EMR2 register  *******************/
3512 #define EXTI_EMR2_EM_Pos           (0U)
3513 #define EXTI_EMR2_EM_Msk           (0xFFFF8FFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFF8FFF */
3514 #define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask           */
3515 #define EXTI_EMR2_EM32_Pos         (0U)
3516 #define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */
3517 #define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/
3518 #define EXTI_EMR2_EM33_Pos         (1U)
3519 #define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */
3520 #define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/
3521 #define EXTI_EMR2_EM34_Pos         (2U)
3522 #define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */
3523 #define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/
3524 #define EXTI_EMR2_EM35_Pos         (3U)
3525 #define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */
3526 #define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/
3527 #define EXTI_EMR2_EM36_Pos         (4U)
3528 #define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */
3529 #define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/
3530 #define EXTI_EMR2_EM37_Pos         (5U)
3531 #define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */
3532 #define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/
3533 
3534 /******************************************************************************/
3535 /*                                                                            */
3536 /*                                    FLASH                                   */
3537 /*                                                                            */
3538 /******************************************************************************/
3539 
3540 /*******************  Bits definition for FLASH_ACR register  *****************/
3541 #define FLASH_ACR_LATENCY_Pos               (0U)
3542 #define FLASH_ACR_LATENCY_Msk               (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
3543 #define FLASH_ACR_LATENCY                   FLASH_ACR_LATENCY_Msk
3544 #define FLASH_ACR_LATENCY_0                 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
3545 #define FLASH_ACR_LATENCY_1                 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
3546 #define FLASH_ACR_LATENCY_2                 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
3547 #define FLASH_ACR_LATENCY_0WS               (0x00000000U)
3548 #define FLASH_ACR_LATENCY_1WS               (0x00000001U)
3549 #define FLASH_ACR_LATENCY_2WS               (0x00000002U)
3550 #define FLASH_ACR_LATENCY_3WS               (0x00000003U)
3551 #define FLASH_ACR_LATENCY_4WS               (0x00000004U)
3552 #define FLASH_ACR_LATENCY_5WS               (0x00000005U)
3553 #define FLASH_ACR_LATENCY_6WS               (0x00000006U)
3554 #define FLASH_ACR_LATENCY_7WS               (0x00000007U)
3555 #define FLASH_ACR_PRFTEN_Pos                (8U)
3556 #define FLASH_ACR_PRFTEN_Msk                (0x1UL << FLASH_ACR_PRFTEN_Pos)     /*!< 0x00000100 */
3557 #define FLASH_ACR_PRFTEN                    FLASH_ACR_PRFTEN_Msk
3558 #define FLASH_ACR_ICEN_Pos                  (9U)
3559 #define FLASH_ACR_ICEN_Msk                  (0x1UL << FLASH_ACR_ICEN_Pos)       /*!< 0x00000200 */
3560 #define FLASH_ACR_ICEN                      FLASH_ACR_ICEN_Msk
3561 #define FLASH_ACR_ICRST_Pos                 (11U)
3562 #define FLASH_ACR_ICRST_Msk                 (0x1UL << FLASH_ACR_ICRST_Pos)      /*!< 0x00000800 */
3563 #define FLASH_ACR_ICRST                     FLASH_ACR_ICRST_Msk
3564 #define FLASH_ACR_EMPTY_Pos                 (16U)
3565 #define FLASH_ACR_EMPTY_Msk                 (0x1UL << FLASH_ACR_EMPTY_Pos)      /*!< 0x00010000 */
3566 #define FLASH_ACR_EMPTY                     FLASH_ACR_EMPTY_Msk
3567 #define FLASH_ACR_DBG_SWEN_Pos              (18U)
3568 #define FLASH_ACR_DBG_SWEN_Msk              (0x1UL << FLASH_ACR_DBG_SWEN_Pos)   /*!< 0x00040000 */
3569 #define FLASH_ACR_DBG_SWEN                  FLASH_ACR_DBG_SWEN_Msk
3570 
3571 /*******************  Bits definition for FLASH_SR register  ******************/
3572 #define FLASH_SR_EOP_Pos                    (0U)
3573 #define FLASH_SR_EOP_Msk                    (0x1UL << FLASH_SR_EOP_Pos)             /*!< 0x00000001 */
3574 #define FLASH_SR_EOP                        FLASH_SR_EOP_Msk
3575 #define FLASH_SR_OPERR_Pos                  (1U)
3576 #define FLASH_SR_OPERR_Msk                  (0x1UL << FLASH_SR_OPERR_Pos)           /*!< 0x00000002 */
3577 #define FLASH_SR_OPERR                      FLASH_SR_OPERR_Msk
3578 #define FLASH_SR_PROGERR_Pos                (3U)
3579 #define FLASH_SR_PROGERR_Msk                (0x1UL << FLASH_SR_PROGERR_Pos)         /*!< 0x00000008 */
3580 #define FLASH_SR_PROGERR                    FLASH_SR_PROGERR_Msk
3581 #define FLASH_SR_WRPERR_Pos                 (4U)
3582 #define FLASH_SR_WRPERR_Msk                 (0x1UL << FLASH_SR_WRPERR_Pos)          /*!< 0x00000010 */
3583 #define FLASH_SR_WRPERR                     FLASH_SR_WRPERR_Msk
3584 #define FLASH_SR_PGAERR_Pos                 (5U)
3585 #define FLASH_SR_PGAERR_Msk                 (0x1UL << FLASH_SR_PGAERR_Pos)          /*!< 0x00000020 */
3586 #define FLASH_SR_PGAERR                     FLASH_SR_PGAERR_Msk
3587 #define FLASH_SR_SIZERR_Pos                 (6U)
3588 #define FLASH_SR_SIZERR_Msk                 (0x1UL << FLASH_SR_SIZERR_Pos)          /*!< 0x00000040 */
3589 #define FLASH_SR_SIZERR                     FLASH_SR_SIZERR_Msk
3590 #define FLASH_SR_PGSERR_Pos                 (7U)
3591 #define FLASH_SR_PGSERR_Msk                 (0x1UL << FLASH_SR_PGSERR_Pos)          /*!< 0x00000080 */
3592 #define FLASH_SR_PGSERR                     FLASH_SR_PGSERR_Msk
3593 #define FLASH_SR_MISERR_Pos                 (8U)
3594 #define FLASH_SR_MISERR_Msk                 (0x1UL << FLASH_SR_MISERR_Pos)          /*!< 0x00000100 */
3595 #define FLASH_SR_MISERR                     FLASH_SR_MISERR_Msk
3596 #define FLASH_SR_FASTERR_Pos                (9U)
3597 #define FLASH_SR_FASTERR_Msk                (0x1UL << FLASH_SR_FASTERR_Pos)         /*!< 0x00000200 */
3598 #define FLASH_SR_FASTERR                    FLASH_SR_FASTERR_Msk
3599 #define FLASH_SR_HDPOPTWERR_Pos             (11U)
3600 #define FLASH_SR_HDPOPTWERRR_Msk            (0x1UL << FLASH_SR_HDPOPTWERR_Pos)      /*!< 0x00000800 */
3601 #define FLASH_SR_HDPOPTWERR                 FLASH_SR_HDPOPTWERR_Msk
3602 #define FLASH_SR_OEMOPTWERR_Pos             (12U)
3603 #define FLASH_SR_OEMOPTWERR_Msk             (0x1UL << FLASH_SR_OEMOPTWERR_Pos)      /*!< 0x00001000 */
3604 #define FLASH_SR_OEMOPTWERR                 FLASH_SR_OEMOPTWERR_Msk
3605 #define FLASH_SR_OPTVERR_Pos                (15U)
3606 #define FLASH_SR_OPTVERR_Msk                (0x1UL << FLASH_SR_OPTVERR_Pos)         /*!< 0x00008000 */
3607 #define FLASH_SR_OPTVERR                    FLASH_SR_OPTVERR_Msk
3608 #define FLASH_SR_BSY1_Pos                   (16U)
3609 #define FLASH_SR_BSY1_Msk                   (0x1UL << FLASH_SR_BSY1_Pos)            /*!< 0x00010000 */
3610 #define FLASH_SR_BSY1                       FLASH_SR_BSY1_Msk
3611 #define FLASH_SR_CFGBSY_Pos                 (18U)
3612 #define FLASH_SR_CFGBSY_Msk                 (0x1UL << FLASH_SR_CFGBSY_Pos)          /*!< 0x00040000 */
3613 #define FLASH_SR_CFGBSY                     FLASH_SR_CFGBSY_Msk
3614 #define FLASH_SR_OEM1LOCK_POS               (20U)
3615 #define FLASH_SR_OEM1LOCK_Msk               (0x1UL << FLASH_SR_OEM1LOCK_POS)        /*!< 0x00100000 */
3616 #define FLASH_SR_OEM1LOCK                   FLASH_SR_OEM1LOCK_Msk
3617 #define FLASH_SR_OEM2LOCK_POS               (21U)
3618 #define FLASH_SR_OEM2LOCK_Msk               (0x1UL << FLASH_SR_OEM2LOCK_POS)        /*!< 0x00200000 */
3619 #define FLASH_SR_OEM2LOCK                   FLASH_SR_OEM2LOCK_Msk
3620 
3621 /*******************  Bits definition for FLASH_CR register  ******************/
3622 #define FLASH_CR_PG_Pos                     (0U)
3623 #define FLASH_CR_PG_Msk                     (0x1UL << FLASH_CR_PG_Pos)              /*!< 0x00000001 */
3624 #define FLASH_CR_PG                         FLASH_CR_PG_Msk
3625 #define FLASH_CR_PER_Pos                    (1U)
3626 #define FLASH_CR_PER_Msk                    (0x1UL << FLASH_CR_PER_Pos)             /*!< 0x00000002 */
3627 #define FLASH_CR_PER                        FLASH_CR_PER_Msk
3628 #define FLASH_CR_MER1_Pos                   (2U)
3629 #define FLASH_CR_MER1_Msk                   (0x1UL << FLASH_CR_MER1_Pos)            /*!< 0x00000004 */
3630 #define FLASH_CR_MER1                       FLASH_CR_MER1_Msk
3631 #define FLASH_CR_PNB_Pos                    (3U)
3632 #define FLASH_CR_PNB_Msk                    (0x7FUL << FLASH_CR_PNB_Pos)            /*!< 0x000003F8 */
3633 #define FLASH_CR_PNB                        FLASH_CR_PNB_Msk
3634 #define FLASH_CR_STRT_Pos                   (16U)
3635 #define FLASH_CR_STRT_Msk                   (0x1UL << FLASH_CR_STRT_Pos)            /*!< 0x00010000 */
3636 #define FLASH_CR_STRT                       FLASH_CR_STRT_Msk
3637 #define FLASH_CR_OPTSTRT_Pos                (17U)
3638 #define FLASH_CR_OPTSTRT_Msk                (0x1UL << FLASH_CR_OPTSTRT_Pos)         /*!< 0x00020000 */
3639 #define FLASH_CR_OPTSTRT                    FLASH_CR_OPTSTRT_Msk
3640 #define FLASH_CR_FSTPG_Pos                  (18U)
3641 #define FLASH_CR_FSTPG_Msk                  (0x1UL << FLASH_CR_FSTPG_Pos)           /*!< 0x00040000 */
3642 #define FLASH_CR_FSTPG                      FLASH_CR_FSTPG_Msk
3643 #define FLASH_CR_EOPIE_Pos                  (24U)
3644 #define FLASH_CR_EOPIE_Msk                  (0x1UL << FLASH_CR_EOPIE_Pos)           /*!< 0x01000000 */
3645 #define FLASH_CR_EOPIE                      FLASH_CR_EOPIE_Msk
3646 #define FLASH_CR_ERRIE_Pos                  (25U)
3647 #define FLASH_CR_ERRIE_Msk                  (0x1UL << FLASH_CR_ERRIE_Pos)           /*!< 0x02000000 */
3648 #define FLASH_CR_ERRIE                      FLASH_CR_ERRIE_Msk
3649 
3650 #define FLASH_CR_OBL_LAUNCH_Pos             (27U)
3651 #define FLASH_CR_OBL_LAUNCH_Msk             (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)      /*!< 0x08000000 */
3652 #define FLASH_CR_OBL_LAUNCH                 FLASH_CR_OBL_LAUNCH_Msk
3653 #define FLASH_CR_OPTLOCK_Pos                (30U)
3654 #define FLASH_CR_OPTLOCK_Msk                (0x1UL << FLASH_CR_OPTLOCK_Pos)         /*!< 0x40000000 */
3655 #define FLASH_CR_OPTLOCK                    FLASH_CR_OPTLOCK_Msk
3656 #define FLASH_CR_LOCK_Pos                   (31U)
3657 #define FLASH_CR_LOCK_Msk                   (0x1UL << FLASH_CR_LOCK_Pos)            /*!< 0x80000000 */
3658 #define FLASH_CR_LOCK                       FLASH_CR_LOCK_Msk
3659 
3660 /*******************  Bits definition for FLASH_ECCR register  ****************/
3661 #define FLASH_ECCR_ADDR_ECC_Pos             (0U)
3662 #define FLASH_ECCR_ADDR_ECC_Msk             (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos)   /*!< 0x00003FFF */
3663 #define FLASH_ECCR_ADDR_ECC                 FLASH_ECCR_ADDR_ECC_Msk
3664 #define FLASH_ECCR_SYSF_ECC_Pos             (20U)
3665 #define FLASH_ECCR_SYSF_ECC_Msk             (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)      /*!< 0x00100000 */
3666 #define FLASH_ECCR_SYSF_ECC                 FLASH_ECCR_SYSF_ECC_Msk
3667 #define FLASH_ECCR_ECCCIE_Pos               (24U)
3668 #define FLASH_ECCR_ECCCIE_Msk               (0x1UL << FLASH_ECCR_ECCCIE_Pos)        /*!< 0x01000000 */
3669 #define FLASH_ECCR_ECCCIE                   FLASH_ECCR_ECCCIE_Msk
3670 #define FLASH_ECCR_ECCC_Pos                 (30U)
3671 #define FLASH_ECCR_ECCC_Msk                 (0x1UL << FLASH_ECCR_ECCC_Pos)          /*!< 0x40000000 */
3672 #define FLASH_ECCR_ECCC                     FLASH_ECCR_ECCC_Msk
3673 #define FLASH_ECCR_ECCD_Pos                 (31U)
3674 #define FLASH_ECCR_ECCD_Msk                 (0x1UL << FLASH_ECCR_ECCD_Pos)          /*!< 0x80000000 */
3675 #define FLASH_ECCR_ECCD                     FLASH_ECCR_ECCD_Msk
3676 
3677 /*******************  Bits definition for FLASH_OPTR register  ****************/
3678 #define FLASH_OPTR_RDP_Pos                  (0U)
3679 #define FLASH_OPTR_RDP_Msk                  (0xFFUL << FLASH_OPTR_RDP_Pos)            /*!< 0x000000FF */
3680 #define FLASH_OPTR_RDP                      FLASH_OPTR_RDP_Msk
3681 #define FLASH_OPTR_BOR_EN_Pos               (8U)
3682 #define FLASH_OPTR_BOR_EN_Msk               (0x1UL << FLASH_OPTR_BOR_EN_Pos)           /*!< 0x00000100 */
3683 #define FLASH_OPTR_BOR_EN                   FLASH_OPTR_BOR_EN_Msk
3684 #define FLASH_OPTR_BORR_LEV_Pos             (9U)
3685 #define FLASH_OPTR_BORR_LEV_Msk             (0x3UL << FLASH_OPTR_BORR_LEV_Pos)         /*!< 0x00000600 */
3686 #define FLASH_OPTR_BORR_LEV                 FLASH_OPTR_BORR_LEV_Msk
3687 #define FLASH_OPTR_BORR_LEV_0               (0x1UL << FLASH_OPTR_BORR_LEV_Pos)         /*!< 0x00000200 */
3688 #define FLASH_OPTR_BORR_LEV_1               (0x2UL << FLASH_OPTR_BORR_LEV_Pos)         /*!< 0x00000400 */
3689 #define FLASH_OPTR_BORF_LEV_Pos             (11U)
3690 #define FLASH_OPTR_BORF_LEV_Msk             (0x3UL << FLASH_OPTR_BORF_LEV_Pos)         /*!< 0x00001800 */
3691 #define FLASH_OPTR_BORF_LEV                 FLASH_OPTR_BORF_LEV_Msk
3692 #define FLASH_OPTR_BORF_LEV_0               (0x1UL << FLASH_OPTR_BORF_LEV_Pos)         /*!< 0x00000800 */
3693 #define FLASH_OPTR_BORF_LEV_1               (0x2UL << FLASH_OPTR_BORF_LEV_Pos)         /*!< 0x00001000 */
3694 #define FLASH_OPTR_nRST_STOP_Pos            (13U)
3695 #define FLASH_OPTR_nRST_STOP_Msk            (0x1UL << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00002000 */
3696 #define FLASH_OPTR_nRST_STOP                FLASH_OPTR_nRST_STOP_Msk
3697 #define FLASH_OPTR_nRST_STDBY_Pos           (14U)
3698 #define FLASH_OPTR_nRST_STDBY_Msk           (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00004000 */
3699 #define FLASH_OPTR_nRST_STDBY               FLASH_OPTR_nRST_STDBY_Msk
3700 #define FLASH_OPTR_nRST_SHDW_Pos            (15U)
3701 #define FLASH_OPTR_nRST_SHDW_Msk            (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)        /*!< 0x00008000 */
3702 #define FLASH_OPTR_nRST_SHDW                FLASH_OPTR_nRST_SHDW_Msk
3703 #define FLASH_OPTR_IWDG_SW_Pos              (16U)
3704 #define FLASH_OPTR_IWDG_SW_Msk              (0x1UL << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00010000 */
3705 #define FLASH_OPTR_IWDG_SW                  FLASH_OPTR_IWDG_SW_Msk
3706 #define FLASH_OPTR_IWDG_STOP_Pos            (17U)
3707 #define FLASH_OPTR_IWDG_STOP_Msk            (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)        /*!< 0x00020000 */
3708 #define FLASH_OPTR_IWDG_STOP                FLASH_OPTR_IWDG_STOP_Msk
3709 #define FLASH_OPTR_IWDG_STDBY_Pos           (18U)
3710 #define FLASH_OPTR_IWDG_STDBY_Msk           (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos)       /*!< 0x00040000 */
3711 #define FLASH_OPTR_IWDG_STDBY               FLASH_OPTR_IWDG_STDBY_Msk
3712 #define FLASH_OPTR_WWDG_SW_Pos              (19U)
3713 #define FLASH_OPTR_WWDG_SW_Msk              (0x1UL << FLASH_OPTR_WWDG_SW_Pos)          /*!< 0x00080000 */
3714 #define FLASH_OPTR_WWDG_SW                  FLASH_OPTR_WWDG_SW_Msk
3715 #define FLASH_OPTR_BDRST_Pos                (21U)
3716 #define FLASH_OPTR_BDRST_Msk                (0x1UL << FLASH_OPTR_BDRST_Pos)            /*!< 0x00200000 */
3717 #define FLASH_OPTR_BDRST                    FLASH_OPTR_BDRST_Msk
3718 #define FLASH_OPTR_RAM_PARITY_CHECK_Pos     (22U)
3719 #define FLASH_OPTR_RAM_PARITY_CHECK_Msk     (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */
3720 #define FLASH_OPTR_RAM_PARITY_CHECK         FLASH_OPTR_RAM_PARITY_CHECK_Msk
3721 #define FLASH_OPTR_BKPSRAM_HW_ERASE_Pos     (23U)
3722 #define FLASH_OPTR_BKPSRAM_HW_ERASE_Msk     (0x1UL << FLASH_OPTR_BKPSRAM_HW_ERASE_Pos) /*!< 0x00800000 */
3723 #define FLASH_OPTR_BKPSRAM_HW_ERASE         FLASH_OPTR_BKPSRAM_HW_ERASE_Msk
3724 #define FLASH_OPTR_nBOOT_SEL_Pos            (24U)
3725 #define FLASH_OPTR_nBOOT_SEL_Msk            (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos)        /*!< 0x01000000 */
3726 #define FLASH_OPTR_nBOOT_SEL                FLASH_OPTR_nBOOT_SEL_Msk
3727 #define FLASH_OPTR_nBOOT1_Pos               (25U)
3728 #define FLASH_OPTR_nBOOT1_Msk               (0x1UL << FLASH_OPTR_nBOOT1_Pos)           /*!< 0x02000000 */
3729 #define FLASH_OPTR_nBOOT1                   FLASH_OPTR_nBOOT1_Msk
3730 #define FLASH_OPTR_nBOOT0_Pos               (26U)
3731 #define FLASH_OPTR_nBOOT0_Msk               (0x1UL << FLASH_OPTR_nBOOT0_Pos)           /*!< 0x04000000 */
3732 #define FLASH_OPTR_nBOOT0                   FLASH_OPTR_nBOOT0_Msk
3733 #define FLASH_OPTR_NRST_MODE_Pos            (27U)
3734 #define FLASH_OPTR_NRST_MODE_Msk            (0x3UL << FLASH_OPTR_NRST_MODE_Pos)        /*!< 0x18000000 */
3735 #define FLASH_OPTR_NRST_MODE                FLASH_OPTR_NRST_MODE_Msk
3736 #define FLASH_OPTR_NRST_MODE_0              (0x1UL << FLASH_OPTR_NRST_MODE_Pos)        /*!< 0x08000000 */
3737 #define FLASH_OPTR_NRST_MODE_1              (0x2UL << FLASH_OPTR_NRST_MODE_Pos)        /*!< 0x10000000 */
3738 #define FLASH_OPTR_IRHEN_Pos                (29U)
3739 #define FLASH_OPTR_IRHEN_Msk                (0x1UL << FLASH_OPTR_IRHEN_Pos)            /*!< 0x20000000 */
3740 #define FLASH_OPTR_IRHEN                    FLASH_OPTR_IRHEN_Msk
3741 
3742 
3743 /******************  Bits definition for FLASH_WRP1AR register  ***************/
3744 #define FLASH_WRP1AR_WRP1A_STRT_Pos         (0U)
3745 #define FLASH_WRP1AR_WRP1A_STRT_Msk         (0xFFFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000FFFF */
3746 #define FLASH_WRP1AR_WRP1A_STRT             FLASH_WRP1AR_WRP1A_STRT_Msk
3747 #define FLASH_WRP1AR_WRP1A_END_Pos          (16U)
3748 #define FLASH_WRP1AR_WRP1A_END_Msk          (0xFFFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0xFFFF0000 */
3749 #define FLASH_WRP1AR_WRP1A_END              FLASH_WRP1AR_WRP1A_END_Msk
3750 
3751 /******************  Bits definition for FLASH_WRP1BR register  ***************/
3752 #define FLASH_WRP1BR_WRP1B_STRT_Pos         (0U)
3753 #define FLASH_WRP1BR_WRP1B_STRT_Msk         (0xFFFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000FFFF */
3754 #define FLASH_WRP1BR_WRP1B_STRT             FLASH_WRP1BR_WRP1B_STRT_Msk
3755 #define FLASH_WRP1BR_WRP1B_END_Pos          (16U)
3756 #define FLASH_WRP1BR_WRP1B_END_Msk          (0xFFFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0xFFFF0000 */
3757 #define FLASH_WRP1BR_WRP1B_END              FLASH_WRP1BR_WRP1B_END_Msk
3758 
3759 
3760 /******************  Bits definition for FLASH_SECR register  *****************/
3761 #define FLASH_SECR_HDP1_PEND_Pos            (0U)
3762 #define FLASH_SECR_HDP1_PEND_Msk            (0x3FUL << FLASH_SECR_HDP1_PEND_Pos)    /*!< 0x0000003F */
3763 #define FLASH_SECR_HDP1_PEND                FLASH_SECR_HDP1_PEND_Msk
3764 #define FLASH_SECR_BOOT_LOCK_Pos            (16U)
3765 #define FLASH_SECR_BOOT_LOCK_Msk            (0x1UL << FLASH_SECR_BOOT_LOCK_Pos)       /*!< 0x00010000 */
3766 #define FLASH_SECR_BOOT_LOCK                FLASH_SECR_BOOT_LOCK_Msk
3767 #define FLASH_SECR_HDP1EN_Pos               (24U)
3768 #define FLASH_SECR_HDP1EN_Msk               (0xFFUL << FLASH_SECR_HDP1EN_Pos)       /*!< 0xFF000000 */
3769 #define FLASH_SECR_HDP1EN                   FLASH_SECR_HDP1EN_Msk
3770 
3771 /******************  Bits definition for FLASH_OEMKEYSR register  *****************/
3772 #define FLASH_OEMKEYSR_OEM1KEYCRC_Pos       (0U)
3773 #define FLASH_OEMKEYSR_OEM1KEYCRC_Msk       (0xFFUL << FLASH_OEMKEYSR_OEM1KEYCRC_Pos)     /*!< 0x000000FF */
3774 #define FLASH_OEMKEYSR_OEM1KEYCRC           FLASH_OEMKEYSR_OEM1KEYCRC_Msk
3775 #define FLASH_OEMKEYSR_OEM2KEYCRC_Pos       (16U)
3776 #define FLASH_OEMKEYSR_OEM2KEYCRC_Msk       (0xFFUL << FLASH_OEMKEYSR_OEM2KEYCRC_Pos)     /*!< 0x00FF0000 */
3777 #define FLASH_OEMKEYSR_OEM2KEYCRC           FLASH_OEMKEYSR_OEM2KEYCRC_Msk
3778 
3779 /******************  Bits definition for FLASH_HDPCR register  *****************/
3780 #define FLASH_HDPCR_HDP1_ACCDIS_Pos         (0U)
3781 #define FLASH_HDPCR_HDP1_ACCDIS_Msk         (0xFFUL << FLASH_HDPCR_HDP1_ACCDIS_Pos)     /*!< 0x000000FF */
3782 #define FLASH_HDPCR_HDP1_ACCDIS             FLASH_HDPCR_HDP1_ACCDIS_Msk
3783 #define FLASH_HDPCR_HDP1EXT_ACCDIS_Pos      (16U)
3784 #define FLASH_HDPCR_HDP1EXT_ACCDIS_Msk      (0xFFUL << FLASH_HDPCR_HDP1EXT_ACCDIS_Pos)     /*!< 0x000000FF */
3785 #define FLASH_HDPCR_HDP1EXT_ACCDIS          FLASH_HDPCR_HDP1EXT_ACCDIS_Msk
3786 
3787 /******************  Bits definition for FLASH_HDPEXTR register  *****************/
3788 #define FLASH_HDPEXTR_HDP1_EXT_Pos          (0U)
3789 #define FLASH_HDPEXTR_HDP1_EXT_Msk          (0x3FUL << FLASH_HDPEXTR_HDP1_EXT_Pos)     /*!< 0x0000003F */
3790 #define FLASH_HDPEXTR_HDP1_EXT              FLASH_HDPEXTR_HDP1_EXT_Msk
3791 
3792 /******************************************************************************/
3793 /*                                                                            */
3794 /*                            General Purpose I/O                             */
3795 /*                                                                            */
3796 /******************************************************************************/
3797 /******************  Bits definition for GPIO_MODER register  *****************/
3798 #define GPIO_MODER_MODE0_Pos           (0U)
3799 #define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
3800 #define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
3801 #define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */
3802 #define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */
3803 
3804 #define GPIO_MODER_MODE1_Pos           (2U)
3805 #define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
3806 #define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
3807 #define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */
3808 #define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */
3809 
3810 #define GPIO_MODER_MODE2_Pos           (4U)
3811 #define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
3812 #define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
3813 #define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */
3814 #define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */
3815 
3816 #define GPIO_MODER_MODE3_Pos           (6U)
3817 #define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
3818 #define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
3819 #define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */
3820 #define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */
3821 
3822 #define GPIO_MODER_MODE4_Pos           (8U)
3823 #define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
3824 #define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
3825 #define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */
3826 #define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */
3827 
3828 #define GPIO_MODER_MODE5_Pos           (10U)
3829 #define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
3830 #define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
3831 #define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */
3832 #define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */
3833 
3834 #define GPIO_MODER_MODE6_Pos           (12U)
3835 #define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
3836 #define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
3837 #define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */
3838 #define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */
3839 
3840 #define GPIO_MODER_MODE7_Pos           (14U)
3841 #define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
3842 #define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
3843 #define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */
3844 #define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */
3845 
3846 #define GPIO_MODER_MODE8_Pos           (16U)
3847 #define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
3848 #define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
3849 #define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */
3850 #define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */
3851 
3852 #define GPIO_MODER_MODE9_Pos           (18U)
3853 #define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
3854 #define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
3855 #define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */
3856 #define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */
3857 
3858 #define GPIO_MODER_MODE10_Pos          (20U)
3859 #define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
3860 #define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
3861 #define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */
3862 #define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */
3863 
3864 #define GPIO_MODER_MODE11_Pos          (22U)
3865 #define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
3866 #define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
3867 #define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */
3868 #define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */
3869 
3870 #define GPIO_MODER_MODE12_Pos          (24U)
3871 #define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
3872 #define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
3873 #define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */
3874 #define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */
3875 
3876 #define GPIO_MODER_MODE13_Pos          (26U)
3877 #define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
3878 #define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
3879 #define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */
3880 #define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */
3881 
3882 #define GPIO_MODER_MODE14_Pos          (28U)
3883 #define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
3884 #define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
3885 #define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */
3886 #define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */
3887 
3888 #define GPIO_MODER_MODE15_Pos          (30U)
3889 #define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
3890 #define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
3891 #define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */
3892 #define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */
3893 
3894 /******************  Bits definition for GPIO_OTYPER register  ****************/
3895 #define GPIO_OTYPER_OT0_Pos            (0U)
3896 #define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
3897 #define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
3898 #define GPIO_OTYPER_OT1_Pos            (1U)
3899 #define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
3900 #define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
3901 #define GPIO_OTYPER_OT2_Pos            (2U)
3902 #define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
3903 #define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
3904 #define GPIO_OTYPER_OT3_Pos            (3U)
3905 #define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
3906 #define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
3907 #define GPIO_OTYPER_OT4_Pos            (4U)
3908 #define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
3909 #define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
3910 #define GPIO_OTYPER_OT5_Pos            (5U)
3911 #define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
3912 #define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
3913 #define GPIO_OTYPER_OT6_Pos            (6U)
3914 #define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
3915 #define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
3916 #define GPIO_OTYPER_OT7_Pos            (7U)
3917 #define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
3918 #define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
3919 #define GPIO_OTYPER_OT8_Pos            (8U)
3920 #define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
3921 #define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
3922 #define GPIO_OTYPER_OT9_Pos            (9U)
3923 #define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
3924 #define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
3925 #define GPIO_OTYPER_OT10_Pos           (10U)
3926 #define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
3927 #define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
3928 #define GPIO_OTYPER_OT11_Pos           (11U)
3929 #define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
3930 #define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
3931 #define GPIO_OTYPER_OT12_Pos           (12U)
3932 #define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
3933 #define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
3934 #define GPIO_OTYPER_OT13_Pos           (13U)
3935 #define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
3936 #define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
3937 #define GPIO_OTYPER_OT14_Pos           (14U)
3938 #define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
3939 #define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
3940 #define GPIO_OTYPER_OT15_Pos           (15U)
3941 #define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
3942 #define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
3943 
3944 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
3945 #define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
3946 #define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
3947 #define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
3948 #define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */
3949 #define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */
3950 
3951 #define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
3952 #define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
3953 #define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
3954 #define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */
3955 #define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */
3956 
3957 #define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
3958 #define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
3959 #define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
3960 #define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */
3961 #define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */
3962 
3963 #define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
3964 #define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
3965 #define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
3966 #define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */
3967 #define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */
3968 
3969 #define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
3970 #define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
3971 #define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
3972 #define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */
3973 #define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */
3974 
3975 #define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
3976 #define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
3977 #define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
3978 #define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */
3979 #define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */
3980 
3981 #define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
3982 #define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
3983 #define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
3984 #define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */
3985 #define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */
3986 
3987 #define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
3988 #define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
3989 #define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
3990 #define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */
3991 #define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */
3992 
3993 #define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
3994 #define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
3995 #define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
3996 #define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */
3997 #define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */
3998 
3999 #define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
4000 #define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
4001 #define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
4002 #define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */
4003 #define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */
4004 
4005 #define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
4006 #define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
4007 #define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
4008 #define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */
4009 #define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */
4010 
4011 #define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
4012 #define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
4013 #define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
4014 #define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */
4015 #define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */
4016 
4017 #define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
4018 #define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
4019 #define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
4020 #define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */
4021 #define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */
4022 
4023 #define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
4024 #define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
4025 #define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
4026 #define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */
4027 #define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */
4028 
4029 #define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
4030 #define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
4031 #define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
4032 #define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */
4033 #define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */
4034 
4035 #define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
4036 #define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
4037 #define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
4038 #define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */
4039 #define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */
4040 
4041 /******************  Bits definition for GPIO_PUPDR register  *****************/
4042 #define GPIO_PUPDR_PUPD0_Pos           (0U)
4043 #define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
4044 #define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
4045 #define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */
4046 #define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */
4047 
4048 #define GPIO_PUPDR_PUPD1_Pos           (2U)
4049 #define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
4050 #define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
4051 #define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */
4052 #define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */
4053 
4054 #define GPIO_PUPDR_PUPD2_Pos           (4U)
4055 #define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
4056 #define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
4057 #define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */
4058 #define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */
4059 
4060 #define GPIO_PUPDR_PUPD3_Pos           (6U)
4061 #define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
4062 #define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
4063 #define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */
4064 #define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */
4065 
4066 #define GPIO_PUPDR_PUPD4_Pos           (8U)
4067 #define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
4068 #define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
4069 #define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */
4070 #define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */
4071 
4072 #define GPIO_PUPDR_PUPD5_Pos           (10U)
4073 #define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
4074 #define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
4075 #define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */
4076 #define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */
4077 
4078 #define GPIO_PUPDR_PUPD6_Pos           (12U)
4079 #define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
4080 #define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
4081 #define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */
4082 #define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */
4083 
4084 #define GPIO_PUPDR_PUPD7_Pos           (14U)
4085 #define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
4086 #define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
4087 #define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */
4088 #define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */
4089 
4090 #define GPIO_PUPDR_PUPD8_Pos           (16U)
4091 #define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
4092 #define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
4093 #define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */
4094 #define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */
4095 
4096 #define GPIO_PUPDR_PUPD9_Pos           (18U)
4097 #define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
4098 #define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
4099 #define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */
4100 #define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */
4101 
4102 #define GPIO_PUPDR_PUPD10_Pos          (20U)
4103 #define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
4104 #define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
4105 #define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */
4106 #define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */
4107 
4108 #define GPIO_PUPDR_PUPD11_Pos          (22U)
4109 #define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
4110 #define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
4111 #define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */
4112 #define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */
4113 
4114 #define GPIO_PUPDR_PUPD12_Pos          (24U)
4115 #define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
4116 #define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
4117 #define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */
4118 #define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */
4119 
4120 #define GPIO_PUPDR_PUPD13_Pos          (26U)
4121 #define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
4122 #define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
4123 #define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */
4124 #define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */
4125 
4126 #define GPIO_PUPDR_PUPD14_Pos          (28U)
4127 #define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
4128 #define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
4129 #define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */
4130 #define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */
4131 
4132 #define GPIO_PUPDR_PUPD15_Pos          (30U)
4133 #define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
4134 #define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
4135 #define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */
4136 #define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */
4137 
4138 /******************  Bits definition for GPIO_IDR register  *******************/
4139 #define GPIO_IDR_ID0_Pos               (0U)
4140 #define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
4141 #define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
4142 #define GPIO_IDR_ID1_Pos               (1U)
4143 #define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
4144 #define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
4145 #define GPIO_IDR_ID2_Pos               (2U)
4146 #define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
4147 #define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
4148 #define GPIO_IDR_ID3_Pos               (3U)
4149 #define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
4150 #define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
4151 #define GPIO_IDR_ID4_Pos               (4U)
4152 #define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
4153 #define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
4154 #define GPIO_IDR_ID5_Pos               (5U)
4155 #define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
4156 #define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
4157 #define GPIO_IDR_ID6_Pos               (6U)
4158 #define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
4159 #define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
4160 #define GPIO_IDR_ID7_Pos               (7U)
4161 #define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
4162 #define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
4163 #define GPIO_IDR_ID8_Pos               (8U)
4164 #define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
4165 #define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
4166 #define GPIO_IDR_ID9_Pos               (9U)
4167 #define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
4168 #define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
4169 #define GPIO_IDR_ID10_Pos              (10U)
4170 #define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
4171 #define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
4172 #define GPIO_IDR_ID11_Pos              (11U)
4173 #define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
4174 #define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
4175 #define GPIO_IDR_ID12_Pos              (12U)
4176 #define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
4177 #define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
4178 #define GPIO_IDR_ID13_Pos              (13U)
4179 #define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
4180 #define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
4181 #define GPIO_IDR_ID14_Pos              (14U)
4182 #define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
4183 #define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
4184 #define GPIO_IDR_ID15_Pos              (15U)
4185 #define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
4186 #define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
4187 
4188 /******************  Bits definition for GPIO_ODR register  *******************/
4189 #define GPIO_ODR_OD0_Pos               (0U)
4190 #define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
4191 #define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
4192 #define GPIO_ODR_OD1_Pos               (1U)
4193 #define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
4194 #define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
4195 #define GPIO_ODR_OD2_Pos               (2U)
4196 #define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
4197 #define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
4198 #define GPIO_ODR_OD3_Pos               (3U)
4199 #define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
4200 #define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
4201 #define GPIO_ODR_OD4_Pos               (4U)
4202 #define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
4203 #define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
4204 #define GPIO_ODR_OD5_Pos               (5U)
4205 #define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
4206 #define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
4207 #define GPIO_ODR_OD6_Pos               (6U)
4208 #define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
4209 #define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
4210 #define GPIO_ODR_OD7_Pos               (7U)
4211 #define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
4212 #define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
4213 #define GPIO_ODR_OD8_Pos               (8U)
4214 #define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
4215 #define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
4216 #define GPIO_ODR_OD9_Pos               (9U)
4217 #define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
4218 #define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
4219 #define GPIO_ODR_OD10_Pos              (10U)
4220 #define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
4221 #define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
4222 #define GPIO_ODR_OD11_Pos              (11U)
4223 #define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
4224 #define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
4225 #define GPIO_ODR_OD12_Pos              (12U)
4226 #define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
4227 #define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
4228 #define GPIO_ODR_OD13_Pos              (13U)
4229 #define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
4230 #define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
4231 #define GPIO_ODR_OD14_Pos              (14U)
4232 #define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
4233 #define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
4234 #define GPIO_ODR_OD15_Pos              (15U)
4235 #define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
4236 #define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
4237 
4238 /******************  Bits definition for GPIO_BSRR register  ******************/
4239 #define GPIO_BSRR_BS0_Pos              (0U)
4240 #define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
4241 #define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
4242 #define GPIO_BSRR_BS1_Pos              (1U)
4243 #define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
4244 #define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
4245 #define GPIO_BSRR_BS2_Pos              (2U)
4246 #define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
4247 #define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
4248 #define GPIO_BSRR_BS3_Pos              (3U)
4249 #define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
4250 #define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
4251 #define GPIO_BSRR_BS4_Pos              (4U)
4252 #define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
4253 #define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
4254 #define GPIO_BSRR_BS5_Pos              (5U)
4255 #define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
4256 #define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
4257 #define GPIO_BSRR_BS6_Pos              (6U)
4258 #define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
4259 #define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
4260 #define GPIO_BSRR_BS7_Pos              (7U)
4261 #define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
4262 #define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
4263 #define GPIO_BSRR_BS8_Pos              (8U)
4264 #define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
4265 #define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
4266 #define GPIO_BSRR_BS9_Pos              (9U)
4267 #define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
4268 #define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
4269 #define GPIO_BSRR_BS10_Pos             (10U)
4270 #define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
4271 #define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
4272 #define GPIO_BSRR_BS11_Pos             (11U)
4273 #define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
4274 #define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
4275 #define GPIO_BSRR_BS12_Pos             (12U)
4276 #define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
4277 #define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
4278 #define GPIO_BSRR_BS13_Pos             (13U)
4279 #define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
4280 #define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
4281 #define GPIO_BSRR_BS14_Pos             (14U)
4282 #define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
4283 #define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
4284 #define GPIO_BSRR_BS15_Pos             (15U)
4285 #define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
4286 #define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
4287 #define GPIO_BSRR_BR0_Pos              (16U)
4288 #define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
4289 #define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
4290 #define GPIO_BSRR_BR1_Pos              (17U)
4291 #define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
4292 #define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
4293 #define GPIO_BSRR_BR2_Pos              (18U)
4294 #define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
4295 #define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
4296 #define GPIO_BSRR_BR3_Pos              (19U)
4297 #define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
4298 #define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
4299 #define GPIO_BSRR_BR4_Pos              (20U)
4300 #define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
4301 #define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
4302 #define GPIO_BSRR_BR5_Pos              (21U)
4303 #define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
4304 #define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
4305 #define GPIO_BSRR_BR6_Pos              (22U)
4306 #define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
4307 #define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
4308 #define GPIO_BSRR_BR7_Pos              (23U)
4309 #define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
4310 #define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
4311 #define GPIO_BSRR_BR8_Pos              (24U)
4312 #define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
4313 #define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
4314 #define GPIO_BSRR_BR9_Pos              (25U)
4315 #define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
4316 #define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
4317 #define GPIO_BSRR_BR10_Pos             (26U)
4318 #define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
4319 #define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
4320 #define GPIO_BSRR_BR11_Pos             (27U)
4321 #define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
4322 #define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
4323 #define GPIO_BSRR_BR12_Pos             (28U)
4324 #define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
4325 #define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
4326 #define GPIO_BSRR_BR13_Pos             (29U)
4327 #define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
4328 #define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
4329 #define GPIO_BSRR_BR14_Pos             (30U)
4330 #define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
4331 #define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
4332 #define GPIO_BSRR_BR15_Pos             (31U)
4333 #define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
4334 #define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
4335 
4336 /****************** Bit definition for GPIO_LCKR register *********************/
4337 #define GPIO_LCKR_LCK0_Pos             (0U)
4338 #define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
4339 #define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
4340 #define GPIO_LCKR_LCK1_Pos             (1U)
4341 #define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
4342 #define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
4343 #define GPIO_LCKR_LCK2_Pos             (2U)
4344 #define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
4345 #define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
4346 #define GPIO_LCKR_LCK3_Pos             (3U)
4347 #define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
4348 #define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
4349 #define GPIO_LCKR_LCK4_Pos             (4U)
4350 #define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
4351 #define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
4352 #define GPIO_LCKR_LCK5_Pos             (5U)
4353 #define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
4354 #define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
4355 #define GPIO_LCKR_LCK6_Pos             (6U)
4356 #define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
4357 #define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
4358 #define GPIO_LCKR_LCK7_Pos             (7U)
4359 #define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
4360 #define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
4361 #define GPIO_LCKR_LCK8_Pos             (8U)
4362 #define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
4363 #define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
4364 #define GPIO_LCKR_LCK9_Pos             (9U)
4365 #define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
4366 #define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
4367 #define GPIO_LCKR_LCK10_Pos            (10U)
4368 #define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
4369 #define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
4370 #define GPIO_LCKR_LCK11_Pos            (11U)
4371 #define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
4372 #define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
4373 #define GPIO_LCKR_LCK12_Pos            (12U)
4374 #define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
4375 #define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
4376 #define GPIO_LCKR_LCK13_Pos            (13U)
4377 #define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
4378 #define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
4379 #define GPIO_LCKR_LCK14_Pos            (14U)
4380 #define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
4381 #define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
4382 #define GPIO_LCKR_LCK15_Pos            (15U)
4383 #define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
4384 #define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
4385 #define GPIO_LCKR_LCKK_Pos             (16U)
4386 #define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
4387 #define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
4388 
4389 /****************** Bit definition for GPIO_AFRL register  ********************/
4390 #define GPIO_AFRL_AFSEL0_Pos           (0U)
4391 #define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
4392 #define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
4393 #define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */
4394 #define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */
4395 #define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */
4396 #define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */
4397 #define GPIO_AFRL_AFSEL1_Pos           (4U)
4398 #define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
4399 #define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
4400 #define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */
4401 #define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */
4402 #define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */
4403 #define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */
4404 #define GPIO_AFRL_AFSEL2_Pos           (8U)
4405 #define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
4406 #define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
4407 #define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */
4408 #define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */
4409 #define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */
4410 #define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */
4411 #define GPIO_AFRL_AFSEL3_Pos           (12U)
4412 #define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
4413 #define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
4414 #define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */
4415 #define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */
4416 #define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */
4417 #define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */
4418 #define GPIO_AFRL_AFSEL4_Pos           (16U)
4419 #define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
4420 #define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
4421 #define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */
4422 #define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */
4423 #define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */
4424 #define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */
4425 #define GPIO_AFRL_AFSEL5_Pos           (20U)
4426 #define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
4427 #define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
4428 #define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */
4429 #define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */
4430 #define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */
4431 #define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */
4432 #define GPIO_AFRL_AFSEL6_Pos           (24U)
4433 #define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
4434 #define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
4435 #define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */
4436 #define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */
4437 #define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */
4438 #define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */
4439 #define GPIO_AFRL_AFSEL7_Pos           (28U)
4440 #define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
4441 #define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
4442 #define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */
4443 #define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */
4444 #define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */
4445 #define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */
4446 
4447 /* Legacy defines */
4448 #define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
4449 #define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
4450 #define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
4451 #define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
4452 #define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
4453 #define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
4454 #define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
4455 #define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
4456 
4457 /****************** Bit definition for GPIO_AFRH register  ********************/
4458 #define GPIO_AFRH_AFSEL8_Pos           (0U)
4459 #define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
4460 #define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
4461 #define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */
4462 #define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */
4463 #define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */
4464 #define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */
4465 #define GPIO_AFRH_AFSEL9_Pos           (4U)
4466 #define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
4467 #define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
4468 #define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */
4469 #define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */
4470 #define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */
4471 #define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */
4472 #define GPIO_AFRH_AFSEL10_Pos          (8U)
4473 #define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
4474 #define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
4475 #define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */
4476 #define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */
4477 #define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */
4478 #define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */
4479 #define GPIO_AFRH_AFSEL11_Pos          (12U)
4480 #define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
4481 #define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
4482 #define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */
4483 #define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */
4484 #define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */
4485 #define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */
4486 #define GPIO_AFRH_AFSEL12_Pos          (16U)
4487 #define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
4488 #define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
4489 #define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */
4490 #define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */
4491 #define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */
4492 #define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */
4493 #define GPIO_AFRH_AFSEL13_Pos          (20U)
4494 #define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
4495 #define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
4496 #define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */
4497 #define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */
4498 #define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */
4499 #define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */
4500 #define GPIO_AFRH_AFSEL14_Pos          (24U)
4501 #define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
4502 #define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
4503 #define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */
4504 #define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */
4505 #define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */
4506 #define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */
4507 #define GPIO_AFRH_AFSEL15_Pos          (28U)
4508 #define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
4509 #define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
4510 #define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */
4511 #define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */
4512 #define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */
4513 #define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */
4514 
4515 /* Legacy defines */
4516 #define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
4517 #define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
4518 #define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
4519 #define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
4520 #define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
4521 #define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
4522 #define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
4523 #define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
4524 
4525 /******************************************************************************/
4526 /*                                                                            */
4527 /*                      Inter-integrated Circuit Interface (I2C)              */
4528 /*                                                                            */
4529 /******************************************************************************/
4530 /*******************  Bit definition for I2C_CR1 register  *******************/
4531 #define I2C_CR1_PE_Pos                      (0U)
4532 #define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)               /*!< 0x00000001 */
4533 #define I2C_CR1_PE                          I2C_CR1_PE_Msk                          /*!< Peripheral enable */
4534 #define I2C_CR1_TXIE_Pos                    (1U)
4535 #define I2C_CR1_TXIE_Msk                    (0x1UL << I2C_CR1_TXIE_Pos)             /*!< 0x00000002 */
4536 #define I2C_CR1_TXIE                        I2C_CR1_TXIE_Msk                        /*!< TX interrupt enable */
4537 #define I2C_CR1_RXIE_Pos                    (2U)
4538 #define I2C_CR1_RXIE_Msk                    (0x1UL << I2C_CR1_RXIE_Pos)             /*!< 0x00000004 */
4539 #define I2C_CR1_RXIE                        I2C_CR1_RXIE_Msk                        /*!< RX interrupt enable */
4540 #define I2C_CR1_ADDRIE_Pos                  (3U)
4541 #define I2C_CR1_ADDRIE_Msk                  (0x1UL << I2C_CR1_ADDRIE_Pos)           /*!< 0x00000008 */
4542 #define I2C_CR1_ADDRIE                      I2C_CR1_ADDRIE_Msk                      /*!< Address match interrupt enable */
4543 #define I2C_CR1_NACKIE_Pos                  (4U)
4544 #define I2C_CR1_NACKIE_Msk                  (0x1UL << I2C_CR1_NACKIE_Pos)           /*!< 0x00000010 */
4545 #define I2C_CR1_NACKIE                      I2C_CR1_NACKIE_Msk                      /*!< NACK received interrupt enable */
4546 #define I2C_CR1_STOPIE_Pos                  (5U)
4547 #define I2C_CR1_STOPIE_Msk                  (0x1UL << I2C_CR1_STOPIE_Pos)           /*!< 0x00000020 */
4548 #define I2C_CR1_STOPIE                      I2C_CR1_STOPIE_Msk                      /*!< STOP detection interrupt enable */
4549 #define I2C_CR1_TCIE_Pos                    (6U)
4550 #define I2C_CR1_TCIE_Msk                    (0x1UL << I2C_CR1_TCIE_Pos)             /*!< 0x00000040 */
4551 #define I2C_CR1_TCIE                        I2C_CR1_TCIE_Msk                        /*!< Transfer complete interrupt enable */
4552 #define I2C_CR1_ERRIE_Pos                   (7U)
4553 #define I2C_CR1_ERRIE_Msk                   (0x1UL << I2C_CR1_ERRIE_Pos)            /*!< 0x00000080 */
4554 #define I2C_CR1_ERRIE                       I2C_CR1_ERRIE_Msk                       /*!< Errors interrupt enable */
4555 #define I2C_CR1_DNF_Pos                     (8U)
4556 #define I2C_CR1_DNF_Msk                     (0xFUL << I2C_CR1_DNF_Pos)              /*!< 0x00000F00 */
4557 #define I2C_CR1_DNF                         I2C_CR1_DNF_Msk                         /*!< Digital noise filter */
4558 #define I2C_CR1_ANFOFF_Pos                  (12U)
4559 #define I2C_CR1_ANFOFF_Msk                  (0x1UL << I2C_CR1_ANFOFF_Pos)           /*!< 0x00001000 */
4560 #define I2C_CR1_ANFOFF                      I2C_CR1_ANFOFF_Msk                      /*!< Analog noise filter OFF */
4561 #define I2C_CR1_TXDMAEN_Pos                 (14U)
4562 #define I2C_CR1_TXDMAEN_Msk                 (0x1UL << I2C_CR1_TXDMAEN_Pos)          /*!< 0x00004000 */
4563 #define I2C_CR1_TXDMAEN                     I2C_CR1_TXDMAEN_Msk                     /*!< DMA transmission requests enable */
4564 #define I2C_CR1_RXDMAEN_Pos                 (15U)
4565 #define I2C_CR1_RXDMAEN_Msk                 (0x1UL << I2C_CR1_RXDMAEN_Pos)          /*!< 0x00008000 */
4566 #define I2C_CR1_RXDMAEN                     I2C_CR1_RXDMAEN_Msk                     /*!< DMA reception requests enable */
4567 #define I2C_CR1_SBC_Pos                     (16U)
4568 #define I2C_CR1_SBC_Msk                     (0x1UL << I2C_CR1_SBC_Pos)              /*!< 0x00010000 */
4569 #define I2C_CR1_SBC                         I2C_CR1_SBC_Msk                         /*!< Slave byte control */
4570 #define I2C_CR1_NOSTRETCH_Pos               (17U)
4571 #define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)        /*!< 0x00020000 */
4572 #define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk                   /*!< Clock stretching disable */
4573 #define I2C_CR1_WUPEN_Pos                   (18U)
4574 #define I2C_CR1_WUPEN_Msk                   (0x1UL << I2C_CR1_WUPEN_Pos)            /*!< 0x00040000 */
4575 #define I2C_CR1_WUPEN                       I2C_CR1_WUPEN_Msk                       /*!< Wakeup from STOP enable */
4576 #define I2C_CR1_GCEN_Pos                    (19U)
4577 #define I2C_CR1_GCEN_Msk                    (0x1UL << I2C_CR1_GCEN_Pos)             /*!< 0x00080000 */
4578 #define I2C_CR1_GCEN                        I2C_CR1_GCEN_Msk                        /*!< General call enable */
4579 #define I2C_CR1_FMP_Pos                     (24U)
4580 #define I2C_CR1_FMP_Msk                     (0x1UL << I2C_CR1_FMP_Pos)            /*!< 0x01000000 */
4581 #define I2C_CR1_FMP                         I2C_CR1_FMP_Msk                       /*!< Fast-mode Plus 20 mA drive enable */
4582 #define I2C_CR1_ADDRACLR_Pos                (30U)
4583 #define I2C_CR1_ADDRACLR_Msk                (0x1UL << I2C_CR1_ADDRACLR_Pos)         /*!< 0x40000000 */
4584 #define I2C_CR1_ADDRACLR                    I2C_CR1_ADDRACLR_Msk                    /*!< ADDRACLR enable */
4585 #define I2C_CR1_STOPFACLR_Pos               (31U)
4586 #define I2C_CR1_STOPFACLR_Msk               (0x1UL << I2C_CR1_STOPFACLR_Pos)        /*!< 0x80000000 */
4587 #define I2C_CR1_STOPFACLR                   I2C_CR1_STOPFACLR_Msk                   /*!< STOPFACLR enable */
4588 
4589 /******************  Bit definition for I2C_CR2 register  ********************/
4590 #define I2C_CR2_SADD_Pos                    (0U)
4591 #define I2C_CR2_SADD_Msk                    (0x3FFUL << I2C_CR2_SADD_Pos)           /*!< 0x000003FF */
4592 #define I2C_CR2_SADD                        I2C_CR2_SADD_Msk                        /*!< Slave address (master mode) */
4593 #define I2C_CR2_RD_WRN_Pos                  (10U)
4594 #define I2C_CR2_RD_WRN_Msk                  (0x1UL << I2C_CR2_RD_WRN_Pos)           /*!< 0x00000400 */
4595 #define I2C_CR2_RD_WRN                      I2C_CR2_RD_WRN_Msk                      /*!< Transfer direction (master mode) */
4596 #define I2C_CR2_ADD10_Pos                   (11U)
4597 #define I2C_CR2_ADD10_Msk                   (0x1UL << I2C_CR2_ADD10_Pos)            /*!< 0x00000800 */
4598 #define I2C_CR2_ADD10                       I2C_CR2_ADD10_Msk                       /*!< 10-bit addressing mode (master mode) */
4599 #define I2C_CR2_HEAD10R_Pos                 (12U)
4600 #define I2C_CR2_HEAD10R_Msk                 (0x1UL << I2C_CR2_HEAD10R_Pos)          /*!< 0x00001000 */
4601 #define I2C_CR2_HEAD10R                     I2C_CR2_HEAD10R_Msk                     /*!< 10-bit address header only read direction (master mode) */
4602 #define I2C_CR2_START_Pos                   (13U)
4603 #define I2C_CR2_START_Msk                   (0x1UL << I2C_CR2_START_Pos)            /*!< 0x00002000 */
4604 #define I2C_CR2_START                       I2C_CR2_START_Msk                       /*!< START generation */
4605 #define I2C_CR2_STOP_Pos                    (14U)
4606 #define I2C_CR2_STOP_Msk                    (0x1UL << I2C_CR2_STOP_Pos)             /*!< 0x00004000 */
4607 #define I2C_CR2_STOP                        I2C_CR2_STOP_Msk                        /*!< STOP generation (master mode) */
4608 #define I2C_CR2_NACK_Pos                    (15U)
4609 #define I2C_CR2_NACK_Msk                    (0x1UL << I2C_CR2_NACK_Pos)             /*!< 0x00008000 */
4610 #define I2C_CR2_NACK                        I2C_CR2_NACK_Msk                        /*!< NACK generation (slave mode) */
4611 #define I2C_CR2_NBYTES_Pos                  (16U)
4612 #define I2C_CR2_NBYTES_Msk                  (0xFFUL << I2C_CR2_NBYTES_Pos)          /*!< 0x00FF0000 */
4613 #define I2C_CR2_NBYTES                      I2C_CR2_NBYTES_Msk                      /*!< Number of bytes */
4614 #define I2C_CR2_RELOAD_Pos                  (24U)
4615 #define I2C_CR2_RELOAD_Msk                  (0x1UL << I2C_CR2_RELOAD_Pos)           /*!< 0x01000000 */
4616 #define I2C_CR2_RELOAD                      I2C_CR2_RELOAD_Msk                      /*!< NBYTES reload mode */
4617 #define I2C_CR2_AUTOEND_Pos                 (25U)
4618 #define I2C_CR2_AUTOEND_Msk                 (0x1UL << I2C_CR2_AUTOEND_Pos)          /*!< 0x02000000 */
4619 #define I2C_CR2_AUTOEND                     I2C_CR2_AUTOEND_Msk                     /*!< Automatic end mode (master mode) */
4620 
4621 /*******************  Bit definition for I2C_OAR1 register  ******************/
4622 #define I2C_OAR1_OA1_Pos                    (0U)
4623 #define I2C_OAR1_OA1_Msk                    (0x3FFUL << I2C_OAR1_OA1_Pos)           /*!< 0x000003FF */
4624 #define I2C_OAR1_OA1                        I2C_OAR1_OA1_Msk                        /*!< Interface own address 1 */
4625 #define I2C_OAR1_OA1MODE_Pos                (10U)
4626 #define I2C_OAR1_OA1MODE_Msk                (0x1UL << I2C_OAR1_OA1MODE_Pos)         /*!< 0x00000400 */
4627 #define I2C_OAR1_OA1MODE                    I2C_OAR1_OA1MODE_Msk                    /*!< Own address 1 10-bit mode */
4628 #define I2C_OAR1_OA1EN_Pos                  (15U)
4629 #define I2C_OAR1_OA1EN_Msk                  (0x1UL << I2C_OAR1_OA1EN_Pos)           /*!< 0x00008000 */
4630 #define I2C_OAR1_OA1EN                      I2C_OAR1_OA1EN_Msk                      /*!< Own address 1 enable */
4631 
4632 /*******************  Bit definition for I2C_OAR2 register  ******************/
4633 #define I2C_OAR2_OA2_Pos                    (1U)
4634 #define I2C_OAR2_OA2_Msk                    (0x7FUL << I2C_OAR2_OA2_Pos)            /*!< 0x000000FE */
4635 #define I2C_OAR2_OA2                        I2C_OAR2_OA2_Msk                        /*!< Interface own address 2 */
4636 #define I2C_OAR2_OA2MSK_Pos                 (8U)
4637 #define I2C_OAR2_OA2MSK_Msk                 (0x7UL << I2C_OAR2_OA2MSK_Pos)          /*!< 0x00000700 */
4638 #define I2C_OAR2_OA2MSK                     I2C_OAR2_OA2MSK_Msk                     /*!< Own address 2 masks */
4639 #define I2C_OAR2_OA2NOMASK                  (0x00000000UL)                          /*!< No mask                                        */
4640 #define I2C_OAR2_OA2MASK01_Pos              (8U)
4641 #define I2C_OAR2_OA2MASK01_Msk              (0x1UL << I2C_OAR2_OA2MASK01_Pos)       /*!< 0x00000100 */
4642 #define I2C_OAR2_OA2MASK01                  I2C_OAR2_OA2MASK01_Msk                  /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
4643 #define I2C_OAR2_OA2MASK02_Pos              (9U)
4644 #define I2C_OAR2_OA2MASK02_Msk              (0x1UL << I2C_OAR2_OA2MASK02_Pos)       /*!< 0x00000200 */
4645 #define I2C_OAR2_OA2MASK02                  I2C_OAR2_OA2MASK02_Msk                  /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
4646 #define I2C_OAR2_OA2MASK03_Pos              (8U)
4647 #define I2C_OAR2_OA2MASK03_Msk              (0x3UL << I2C_OAR2_OA2MASK03_Pos)       /*!< 0x00000300 */
4648 #define I2C_OAR2_OA2MASK03                  I2C_OAR2_OA2MASK03_Msk                  /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
4649 #define I2C_OAR2_OA2MASK04_Pos              (10U)
4650 #define I2C_OAR2_OA2MASK04_Msk              (0x1UL << I2C_OAR2_OA2MASK04_Pos)       /*!< 0x00000400 */
4651 #define I2C_OAR2_OA2MASK04                  I2C_OAR2_OA2MASK04_Msk                  /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
4652 #define I2C_OAR2_OA2MASK05_Pos              (8U)
4653 #define I2C_OAR2_OA2MASK05_Msk              (0x5UL << I2C_OAR2_OA2MASK05_Pos)       /*!< 0x00000500 */
4654 #define I2C_OAR2_OA2MASK05                  I2C_OAR2_OA2MASK05_Msk                  /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
4655 #define I2C_OAR2_OA2MASK06_Pos              (9U)
4656 #define I2C_OAR2_OA2MASK06_Msk              (0x3UL << I2C_OAR2_OA2MASK06_Pos)       /*!< 0x00000600 */
4657 #define I2C_OAR2_OA2MASK06                  I2C_OAR2_OA2MASK06_Msk                  /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
4658 #define I2C_OAR2_OA2MASK07_Pos              (8U)
4659 #define I2C_OAR2_OA2MASK07_Msk              (0x7UL << I2C_OAR2_OA2MASK07_Pos)       /*!< 0x00000700 */
4660 #define I2C_OAR2_OA2MASK07                  I2C_OAR2_OA2MASK07_Msk                  /*!< OA2[7:1] is masked, No comparison is done      */
4661 #define I2C_OAR2_OA2EN_Pos                  (15U)
4662 #define I2C_OAR2_OA2EN_Msk                  (0x1UL << I2C_OAR2_OA2EN_Pos)           /*!< 0x00008000 */
4663 #define I2C_OAR2_OA2EN                      I2C_OAR2_OA2EN_Msk                      /*!< Own address 2 enable */
4664 
4665 /*******************  Bit definition for I2C_TIMINGR register *******************/
4666 #define I2C_TIMINGR_SCLL_Pos                (0U)
4667 #define I2C_TIMINGR_SCLL_Msk                (0xFFUL << I2C_TIMINGR_SCLL_Pos)        /*!< 0x000000FF */
4668 #define I2C_TIMINGR_SCLL                    I2C_TIMINGR_SCLL_Msk                    /*!< SCL low period (master mode) */
4669 #define I2C_TIMINGR_SCLH_Pos                (8U)
4670 #define I2C_TIMINGR_SCLH_Msk                (0xFFUL << I2C_TIMINGR_SCLH_Pos)        /*!< 0x0000FF00 */
4671 #define I2C_TIMINGR_SCLH                    I2C_TIMINGR_SCLH_Msk                    /*!< SCL high period (master mode) */
4672 #define I2C_TIMINGR_SDADEL_Pos              (16U)
4673 #define I2C_TIMINGR_SDADEL_Msk              (0xFUL << I2C_TIMINGR_SDADEL_Pos)       /*!< 0x000F0000 */
4674 #define I2C_TIMINGR_SDADEL                  I2C_TIMINGR_SDADEL_Msk                  /*!< Data hold time */
4675 #define I2C_TIMINGR_SCLDEL_Pos              (20U)
4676 #define I2C_TIMINGR_SCLDEL_Msk              (0xFUL << I2C_TIMINGR_SCLDEL_Pos)       /*!< 0x00F00000 */
4677 #define I2C_TIMINGR_SCLDEL                  I2C_TIMINGR_SCLDEL_Msk                  /*!< Data setup time */
4678 #define I2C_TIMINGR_PRESC_Pos               (28U)
4679 #define I2C_TIMINGR_PRESC_Msk               (0xFUL << I2C_TIMINGR_PRESC_Pos)        /*!< 0xF0000000 */
4680 #define I2C_TIMINGR_PRESC                   I2C_TIMINGR_PRESC_Msk                   /*!< Timings prescaler */
4681 
4682 /******************  Bit definition for I2C_ISR register  *********************/
4683 #define I2C_ISR_TXE_Pos                     (0U)
4684 #define I2C_ISR_TXE_Msk                     (0x1UL << I2C_ISR_TXE_Pos)              /*!< 0x00000001 */
4685 #define I2C_ISR_TXE                         I2C_ISR_TXE_Msk                         /*!< Transmit data register empty */
4686 #define I2C_ISR_TXIS_Pos                    (1U)
4687 #define I2C_ISR_TXIS_Msk                    (0x1UL << I2C_ISR_TXIS_Pos)             /*!< 0x00000002 */
4688 #define I2C_ISR_TXIS                        I2C_ISR_TXIS_Msk                        /*!< Transmit interrupt status */
4689 #define I2C_ISR_RXNE_Pos                    (2U)
4690 #define I2C_ISR_RXNE_Msk                    (0x1UL << I2C_ISR_RXNE_Pos)             /*!< 0x00000004 */
4691 #define I2C_ISR_RXNE                        I2C_ISR_RXNE_Msk                        /*!< Receive data register not empty */
4692 #define I2C_ISR_ADDR_Pos                    (3U)
4693 #define I2C_ISR_ADDR_Msk                    (0x1UL << I2C_ISR_ADDR_Pos)             /*!< 0x00000008 */
4694 #define I2C_ISR_ADDR                        I2C_ISR_ADDR_Msk                        /*!< Address matched (slave mode)*/
4695 #define I2C_ISR_NACKF_Pos                   (4U)
4696 #define I2C_ISR_NACKF_Msk                   (0x1UL << I2C_ISR_NACKF_Pos)            /*!< 0x00000010 */
4697 #define I2C_ISR_NACKF                       I2C_ISR_NACKF_Msk                       /*!< NACK received flag */
4698 #define I2C_ISR_STOPF_Pos                   (5U)
4699 #define I2C_ISR_STOPF_Msk                   (0x1UL << I2C_ISR_STOPF_Pos)            /*!< 0x00000020 */
4700 #define I2C_ISR_STOPF                       I2C_ISR_STOPF_Msk                       /*!< STOP detection flag */
4701 #define I2C_ISR_TC_Pos                      (6U)
4702 #define I2C_ISR_TC_Msk                      (0x1UL << I2C_ISR_TC_Pos)               /*!< 0x00000040 */
4703 #define I2C_ISR_TC                          I2C_ISR_TC_Msk                          /*!< Transfer complete (master mode) */
4704 #define I2C_ISR_TCR_Pos                     (7U)
4705 #define I2C_ISR_TCR_Msk                     (0x1UL << I2C_ISR_TCR_Pos)              /*!< 0x00000080 */
4706 #define I2C_ISR_TCR                         I2C_ISR_TCR_Msk                         /*!< Transfer complete reload */
4707 #define I2C_ISR_BERR_Pos                    (8U)
4708 #define I2C_ISR_BERR_Msk                    (0x1UL << I2C_ISR_BERR_Pos)             /*!< 0x00000100 */
4709 #define I2C_ISR_BERR                        I2C_ISR_BERR_Msk                        /*!< Bus error */
4710 #define I2C_ISR_ARLO_Pos                    (9U)
4711 #define I2C_ISR_ARLO_Msk                    (0x1UL << I2C_ISR_ARLO_Pos)             /*!< 0x00000200 */
4712 #define I2C_ISR_ARLO                        I2C_ISR_ARLO_Msk                        /*!< Arbitration lost */
4713 #define I2C_ISR_OVR_Pos                     (10U)
4714 #define I2C_ISR_OVR_Msk                     (0x1UL << I2C_ISR_OVR_Pos)              /*!< 0x00000400 */
4715 #define I2C_ISR_OVR                         I2C_ISR_OVR_Msk                         /*!< Overrun/Underrun */
4716 #define I2C_ISR_BUSY_Pos                    (15U)
4717 #define I2C_ISR_BUSY_Msk                    (0x1UL << I2C_ISR_BUSY_Pos)             /*!< 0x00008000 */
4718 #define I2C_ISR_BUSY                        I2C_ISR_BUSY_Msk                        /*!< Bus busy */
4719 #define I2C_ISR_DIR_Pos                     (16U)
4720 #define I2C_ISR_DIR_Msk                     (0x1UL << I2C_ISR_DIR_Pos)              /*!< 0x00010000 */
4721 #define I2C_ISR_DIR                         I2C_ISR_DIR_Msk                         /*!< Transfer direction (slave mode) */
4722 #define I2C_ISR_ADDCODE_Pos                 (17U)
4723 #define I2C_ISR_ADDCODE_Msk                 (0x7FUL << I2C_ISR_ADDCODE_Pos)         /*!< 0x00FE0000 */
4724 #define I2C_ISR_ADDCODE                     I2C_ISR_ADDCODE_Msk                     /*!< Address match code (slave mode) */
4725 
4726 /******************  Bit definition for I2C_ICR register  *********************/
4727 #define I2C_ICR_ADDRCF_Pos                  (3U)
4728 #define I2C_ICR_ADDRCF_Msk                  (0x1UL << I2C_ICR_ADDRCF_Pos)           /*!< 0x00000008 */
4729 #define I2C_ICR_ADDRCF                      I2C_ICR_ADDRCF_Msk                      /*!< Address matched clear flag */
4730 #define I2C_ICR_NACKCF_Pos                  (4U)
4731 #define I2C_ICR_NACKCF_Msk                  (0x1UL << I2C_ICR_NACKCF_Pos)           /*!< 0x00000010 */
4732 #define I2C_ICR_NACKCF                      I2C_ICR_NACKCF_Msk                      /*!< NACK clear flag */
4733 #define I2C_ICR_STOPCF_Pos                  (5U)
4734 #define I2C_ICR_STOPCF_Msk                  (0x1UL << I2C_ICR_STOPCF_Pos)           /*!< 0x00000020 */
4735 #define I2C_ICR_STOPCF                      I2C_ICR_STOPCF_Msk                      /*!< STOP detection clear flag */
4736 #define I2C_ICR_BERRCF_Pos                  (8U)
4737 #define I2C_ICR_BERRCF_Msk                  (0x1UL << I2C_ICR_BERRCF_Pos)           /*!< 0x00000100 */
4738 #define I2C_ICR_BERRCF                      I2C_ICR_BERRCF_Msk                      /*!< Bus error clear flag */
4739 #define I2C_ICR_ARLOCF_Pos                  (9U)
4740 #define I2C_ICR_ARLOCF_Msk                  (0x1UL << I2C_ICR_ARLOCF_Pos)           /*!< 0x00000200 */
4741 #define I2C_ICR_ARLOCF                      I2C_ICR_ARLOCF_Msk                      /*!< Arbitration lost clear flag */
4742 #define I2C_ICR_OVRCF_Pos                   (10U)
4743 #define I2C_ICR_OVRCF_Msk                   (0x1UL << I2C_ICR_OVRCF_Pos)            /*!< 0x00000400 */
4744 #define I2C_ICR_OVRCF                       I2C_ICR_OVRCF_Msk                       /*!< Overrun/Underrun clear flag */
4745 
4746 /******************  Bit definition for I2C_RXDR register  *********************/
4747 #define I2C_RXDR_RXDATA_Pos                 (0U)
4748 #define I2C_RXDR_RXDATA_Msk                 (0xFFUL << I2C_RXDR_RXDATA_Pos)         /*!< 0x000000FF */
4749 #define I2C_RXDR_RXDATA                     I2C_RXDR_RXDATA_Msk                     /*!< 8-bit receive data */
4750 
4751 /******************  Bit definition for I2C_TXDR register  *********************/
4752 #define I2C_TXDR_TXDATA_Pos                 (0U)
4753 #define I2C_TXDR_TXDATA_Msk                 (0xFFUL << I2C_TXDR_TXDATA_Pos)         /*!< 0x000000FF */
4754 #define I2C_TXDR_TXDATA                     I2C_TXDR_TXDATA_Msk                     /*!< 8-bit transmit data */
4755 
4756 /******************************************************************************/
4757 /*                                                                            */
4758 /*                           Independent WATCHDOG                             */
4759 /*                                                                            */
4760 /******************************************************************************/
4761 /*******************  Bit definition for IWDG_KR register  ********************/
4762 #define IWDG_KR_KEY_Pos      (0U)
4763 #define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
4764 #define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
4765 
4766 /*******************  Bit definition for IWDG_PR register  ********************/
4767 #define IWDG_PR_PR_Pos       (0U)
4768 #define IWDG_PR_PR_Msk       (0xFUL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
4769 #define IWDG_PR_PR           IWDG_PR_PR_Msk                                     /*!< PR[3:0] (Prescaler divider)         */
4770 #define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
4771 #define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
4772 #define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
4773 #define IWDG_PR_PR_3         (0x8UL << IWDG_PR_PR_Pos)                          /*!< 0x00000008 */
4774 
4775 /*******************  Bit definition for IWDG_RLR register  *******************/
4776 #define IWDG_RLR_RL_Pos      (0U)
4777 #define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
4778 #define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
4779 
4780 /*******************  Bit definition for IWDG_SR register  ********************/
4781 #define IWDG_SR_PVU_Pos      (0U)
4782 #define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
4783 #define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
4784 #define IWDG_SR_RVU_Pos      (1U)
4785 #define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
4786 #define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
4787 #define IWDG_SR_WVU_Pos      (2U)
4788 #define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
4789 #define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
4790 #define IWDG_SR_EWU_Pos      (3U)
4791 #define IWDG_SR_EWU_Msk      (0x1UL << IWDG_SR_EWU_Pos)                        /*!< 0x00000008 */
4792 #define IWDG_SR_EWU          IWDG_SR_EWU_Msk                                   /*!< Watchdog interrupt comparator value update */
4793 #define IWDG_SR_ONF_Pos      (8U)
4794 #define IWDG_SR_ONF_Msk      (0x1UL << IWDG_SR_ONF_Pos)                        /*!< 0x00000100 */
4795 #define IWDG_SR_ONF          IWDG_SR_ONF_Msk                                   /*!< Watchdog Enable status bit */
4796 #define IWDG_SR_EWIF_Pos     (14U)
4797 #define IWDG_SR_EWIF_Msk     (0x1UL << IWDG_SR_EWIF_Pos)                       /*!< 0x00004000 */
4798 #define IWDG_SR_EWIF         IWDG_SR_EWIF_Msk                                  /*!< Watchdog early interrupt flag */
4799 
4800 /*******************  Bit definition for IWDG_WINR register  ********************/
4801 #define IWDG_WINR_WIN_Pos    (0U)
4802 #define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
4803 #define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
4804 
4805 /******************  Bit definition for IWDG_EWCR register  *******************/
4806 #define IWDG_EWCR_EWIT_Pos                  (0U)
4807 #define IWDG_EWCR_EWIT_Msk                  (0xFFFUL << IWDG_EWCR_EWIT_Pos)         /*!< 0x00000FFF */
4808 #define IWDG_EWCR_EWIT                      IWDG_EWCR_EWIT_Msk                      /*!< Watchdog early wakeup comparator value */
4809 #define IWDG_EWCR_EWIC_Pos                  (14U)
4810 #define IWDG_EWCR_EWIC_Msk                  (0x1UL << IWDG_EWCR_EWIC_Pos)           /*!< 0x00004000 */
4811 #define IWDG_EWCR_EWIC                      IWDG_EWCR_EWIC_Msk                      /*!< Watchdog early wakeup comparator value */
4812 #define IWDG_EWCR_EWIE_Pos                  (15U)
4813 #define IWDG_EWCR_EWIE_Msk                  (0x1UL << IWDG_EWCR_EWIE_Pos)           /*!< 0x00008000 */
4814 #define IWDG_EWCR_EWIE                      IWDG_EWCR_EWIE_Msk                      /*!< Watchdog early wakeup comparator value */
4815 
4816 /******************************************************************************/
4817 /*                                                                            */
4818 /*                          LCD Controller (LCD)                              */
4819 /*                                                                            */
4820 /******************************************************************************/
4821 
4822 /*******************  Bit definition for LCD_CR register  *********************/
4823 #define LCD_CR_LCDEN_Pos            (0U)
4824 #define LCD_CR_LCDEN_Msk            (0x1UL << LCD_CR_LCDEN_Pos)                /*!< 0x00000001 */
4825 #define LCD_CR_LCDEN                LCD_CR_LCDEN_Msk                           /*!< LCD Enable Bit */
4826 #define LCD_CR_VSEL_Pos             (1U)
4827 #define LCD_CR_VSEL_Msk             (0x1UL << LCD_CR_VSEL_Pos)                 /*!< 0x00000002 */
4828 #define LCD_CR_VSEL                 LCD_CR_VSEL_Msk                            /*!< Voltage source selector Bit */
4829 
4830 #define LCD_CR_DUTY_Pos             (2U)
4831 #define LCD_CR_DUTY_Msk             (0x7UL << LCD_CR_DUTY_Pos)                 /*!< 0x0000001C */
4832 #define LCD_CR_DUTY                 LCD_CR_DUTY_Msk                            /*!< DUTY[2:0] bits (Duty selector) */
4833 #define LCD_CR_DUTY_0               (0x1UL << LCD_CR_DUTY_Pos)                 /*!< 0x00000004 */
4834 #define LCD_CR_DUTY_1               (0x2UL << LCD_CR_DUTY_Pos)                 /*!< 0x00000008 */
4835 #define LCD_CR_DUTY_2               (0x4UL << LCD_CR_DUTY_Pos)                 /*!< 0x00000010 */
4836 
4837 #define LCD_CR_BIAS_Pos             (5U)
4838 #define LCD_CR_BIAS_Msk             (0x3UL << LCD_CR_BIAS_Pos)                 /*!< 0x00000060 */
4839 #define LCD_CR_BIAS                 LCD_CR_BIAS_Msk                            /*!< BIAS[1:0] bits (Bias selector) */
4840 #define LCD_CR_BIAS_0               (0x1UL << LCD_CR_BIAS_Pos)                 /*!< 0x00000020 */
4841 #define LCD_CR_BIAS_1               (0x2UL << LCD_CR_BIAS_Pos)                 /*!< 0x00000040 */
4842 
4843 #define LCD_CR_MUX_SEG_Pos          (7U)
4844 #define LCD_CR_MUX_SEG_Msk          (0x1UL << LCD_CR_MUX_SEG_Pos)              /*!< 0x00000080 */
4845 #define LCD_CR_MUX_SEG              LCD_CR_MUX_SEG_Msk                         /*!< Mux Segment Enable Bit */
4846 #define LCD_CR_BUFEN_Pos            (8U)
4847 #define LCD_CR_BUFEN_Msk            (0x1UL << LCD_CR_BUFEN_Pos)                /*!< 0x00000100 */
4848 #define LCD_CR_BUFEN                LCD_CR_BUFEN_Msk                           /*!< Voltage output buffer enable */
4849 
4850 /*******************  Bit definition for LCD_FCR register  ********************/
4851 #define LCD_FCR_HD_Pos              (0U)
4852 #define LCD_FCR_HD_Msk              (0x1UL << LCD_FCR_HD_Pos)                  /*!< 0x00000001 */
4853 #define LCD_FCR_HD                  LCD_FCR_HD_Msk                             /*!< High Drive Enable Bit */
4854 #define LCD_FCR_SOFIE_Pos           (1U)
4855 #define LCD_FCR_SOFIE_Msk           (0x1UL << LCD_FCR_SOFIE_Pos)               /*!< 0x00000002 */
4856 #define LCD_FCR_SOFIE               LCD_FCR_SOFIE_Msk                          /*!< Start of Frame Interrupt Enable Bit */
4857 #define LCD_FCR_UDDIE_Pos           (3U)
4858 #define LCD_FCR_UDDIE_Msk           (0x1UL << LCD_FCR_UDDIE_Pos)               /*!< 0x00000008 */
4859 #define LCD_FCR_UDDIE               LCD_FCR_UDDIE_Msk                          /*!< Update Display Done Interrupt Enable Bit */
4860 
4861 #define LCD_FCR_PON_Pos             (4U)
4862 #define LCD_FCR_PON_Msk             (0x7UL << LCD_FCR_PON_Pos)                 /*!< 0x00000070 */
4863 #define LCD_FCR_PON                 LCD_FCR_PON_Msk                            /*!< PON[2:0] bits (Pulse ON Duration) */
4864 #define LCD_FCR_PON_0               (0x1UL << LCD_FCR_PON_Pos)                 /*!< 0x00000010 */
4865 #define LCD_FCR_PON_1               (0x2UL << LCD_FCR_PON_Pos)                 /*!< 0x00000020 */
4866 #define LCD_FCR_PON_2               (0x4UL << LCD_FCR_PON_Pos)                 /*!< 0x00000040 */
4867 
4868 #define LCD_FCR_DEAD_Pos            (7U)
4869 #define LCD_FCR_DEAD_Msk            (0x7UL << LCD_FCR_DEAD_Pos)                /*!< 0x00000380 */
4870 #define LCD_FCR_DEAD                LCD_FCR_DEAD_Msk                           /*!< DEAD[2:0] bits (DEAD Time) */
4871 #define LCD_FCR_DEAD_0              (0x1UL << LCD_FCR_DEAD_Pos)                /*!< 0x00000080 */
4872 #define LCD_FCR_DEAD_1              (0x2UL << LCD_FCR_DEAD_Pos)                /*!< 0x00000100 */
4873 #define LCD_FCR_DEAD_2              (0x4UL << LCD_FCR_DEAD_Pos)                /*!< 0x00000200 */
4874 
4875 #define LCD_FCR_CC_Pos              (10U)
4876 #define LCD_FCR_CC_Msk              (0x7UL << LCD_FCR_CC_Pos)                  /*!< 0x00001C00 */
4877 #define LCD_FCR_CC                  LCD_FCR_CC_Msk                             /*!< CC[2:0] bits (Contrast Control) */
4878 #define LCD_FCR_CC_0                (0x1UL << LCD_FCR_CC_Pos)                  /*!< 0x00000400 */
4879 #define LCD_FCR_CC_1                (0x2UL << LCD_FCR_CC_Pos)                  /*!< 0x00000800 */
4880 #define LCD_FCR_CC_2                (0x4UL << LCD_FCR_CC_Pos)                  /*!< 0x00001000 */
4881 
4882 #define LCD_FCR_BLINKF_Pos          (13U)
4883 #define LCD_FCR_BLINKF_Msk          (0x7UL << LCD_FCR_BLINKF_Pos)              /*!< 0x0000E000 */
4884 #define LCD_FCR_BLINKF              LCD_FCR_BLINKF_Msk                         /*!< BLINKF[2:0] bits (Blink Frequency) */
4885 #define LCD_FCR_BLINKF_0            (0x1UL << LCD_FCR_BLINKF_Pos)              /*!< 0x00002000 */
4886 #define LCD_FCR_BLINKF_1            (0x2UL << LCD_FCR_BLINKF_Pos)              /*!< 0x00004000 */
4887 #define LCD_FCR_BLINKF_2            (0x4UL << LCD_FCR_BLINKF_Pos)              /*!< 0x00008000 */
4888 
4889 #define LCD_FCR_BLINK_Pos           (16U)
4890 #define LCD_FCR_BLINK_Msk           (0x3UL << LCD_FCR_BLINK_Pos)               /*!< 0x00030000 */
4891 #define LCD_FCR_BLINK               LCD_FCR_BLINK_Msk                          /*!< BLINK[1:0] bits (Blink Enable) */
4892 #define LCD_FCR_BLINK_0             (0x1UL << LCD_FCR_BLINK_Pos)               /*!< 0x00010000 */
4893 #define LCD_FCR_BLINK_1             (0x2UL << LCD_FCR_BLINK_Pos)               /*!< 0x00020000 */
4894 
4895 #define LCD_FCR_DIV_Pos             (18U)
4896 #define LCD_FCR_DIV_Msk             (0xFUL << LCD_FCR_DIV_Pos)                 /*!< 0x003C0000 */
4897 #define LCD_FCR_DIV                 LCD_FCR_DIV_Msk                            /*!< DIV[3:0] bits (Divider) */
4898 #define LCD_FCR_PS_Pos              (22U)
4899 #define LCD_FCR_PS_Msk              (0xFUL << LCD_FCR_PS_Pos)                  /*!< 0x03C00000 */
4900 #define LCD_FCR_PS                  LCD_FCR_PS_Msk                             /*!< PS[3:0] bits (Prescaler) */
4901 
4902 /*******************  Bit definition for LCD_SR register  *********************/
4903 #define LCD_SR_ENS_Pos              (0U)
4904 #define LCD_SR_ENS_Msk              (0x1UL << LCD_SR_ENS_Pos)                  /*!< 0x00000001 */
4905 #define LCD_SR_ENS                  LCD_SR_ENS_Msk                             /*!< LCD Enabled Bit */
4906 #define LCD_SR_SOF_Pos              (1U)
4907 #define LCD_SR_SOF_Msk              (0x1UL << LCD_SR_SOF_Pos)                  /*!< 0x00000002 */
4908 #define LCD_SR_SOF                  LCD_SR_SOF_Msk                             /*!< Start Of Frame Flag Bit */
4909 #define LCD_SR_UDR_Pos              (2U)
4910 #define LCD_SR_UDR_Msk              (0x1UL << LCD_SR_UDR_Pos)                  /*!< 0x00000004 */
4911 #define LCD_SR_UDR                  LCD_SR_UDR_Msk                             /*!< Update Display Request Bit */
4912 #define LCD_SR_UDD_Pos              (3U)
4913 #define LCD_SR_UDD_Msk              (0x1UL << LCD_SR_UDD_Pos)                  /*!< 0x00000008 */
4914 #define LCD_SR_UDD                  LCD_SR_UDD_Msk                             /*!< Update Display Done Flag Bit */
4915 #define LCD_SR_RDY_Pos              (4U)
4916 #define LCD_SR_RDY_Msk              (0x1UL << LCD_SR_RDY_Pos)                  /*!< 0x00000010 */
4917 #define LCD_SR_RDY                  LCD_SR_RDY_Msk                             /*!< Ready Flag Bit */
4918 #define LCD_SR_FCRSR_Pos            (5U)
4919 #define LCD_SR_FCRSR_Msk            (0x1UL << LCD_SR_FCRSR_Pos)                /*!< 0x00000020 */
4920 #define LCD_SR_FCRSR                LCD_SR_FCRSR_Msk                           /*!< LCD FCR Register Synchronization Flag Bit */
4921 
4922 /*******************  Bit definition for LCD_CLR register  ********************/
4923 #define LCD_CLR_SOFC_Pos            (1U)
4924 #define LCD_CLR_SOFC_Msk            (0x1UL << LCD_CLR_SOFC_Pos)                /*!< 0x00000002 */
4925 #define LCD_CLR_SOFC                LCD_CLR_SOFC_Msk                           /*!< Start Of Frame Flag Clear Bit */
4926 #define LCD_CLR_UDDC_Pos            (3U)
4927 #define LCD_CLR_UDDC_Msk            (0x1UL << LCD_CLR_UDDC_Pos)                /*!< 0x00000008 */
4928 #define LCD_CLR_UDDC                LCD_CLR_UDDC_Msk                           /*!< Update Display Done Flag Clear Bit */
4929 
4930 /*******************  Bit definition for LCD_RAM register  ********************/
4931 #define LCD_RAM_SEGMENT_DATA_Pos    (0U)
4932 #define LCD_RAM_SEGMENT_DATA_Msk    (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos) /*!< 0xFFFFFFFF */
4933 #define LCD_RAM_SEGMENT_DATA        LCD_RAM_SEGMENT_DATA_Msk                   /*!< Segment Data Bits */
4934 
4935 /******************************************************************************/
4936 /*                                                                            */
4937 /*                         Operational Amplifier (OPAMP)                      */
4938 /*                                                                            */
4939 /******************************************************************************/
4940 /*********************  Bit definition for OPAMPx_CSR register  ***************/
4941 #define OPAMP_CSR_OPAEN_Pos                 (0U)
4942 #define OPAMP_CSR_OPAEN_Msk                 (0x1UL << OPAMP_CSR_OPAEN_Pos)            /*!< 0x00000001 */
4943 #define OPAMP_CSR_OPAEN                     OPAMP_CSR_OPAEN_Msk                       /*!< OPAMP enable */
4944 
4945 #define OPAMP_CSR_OPALPM_Pos                (1U)
4946 #define OPAMP_CSR_OPALPM_Msk                (0x1UL << OPAMP_CSR_OPALPM_Pos)           /*!< 0x00000002 */
4947 #define OPAMP_CSR_OPALPM                    OPAMP_CSR_OPALPM_Msk                      /*!< Operational amplifier Low Power Mode */
4948 
4949 #define OPAMP_CSR_OPAMODE_Pos               (2U)
4950 #define OPAMP_CSR_OPAMODE_Msk               (0x3UL << OPAMP_CSR_OPAMODE_Pos)          /*!< 0x0000000C */
4951 #define OPAMP_CSR_OPAMODE                   OPAMP_CSR_OPAMODE_Msk                     /*!< Operational amplifier PGA mode */
4952 #define OPAMP_CSR_OPAMODE_0                 (0x1UL << OPAMP_CSR_OPAMODE_Pos)          /*!< 0x00000004 */
4953 #define OPAMP_CSR_OPAMODE_1                 (0x2UL << OPAMP_CSR_OPAMODE_Pos)          /*!< 0x00000008 */
4954 
4955 #define OPAMP_CSR_PGA_GAIN_Pos              (4U)
4956 #define OPAMP_CSR_PGA_GAIN_Msk              (0x3UL << OPAMP_CSR_PGA_GAIN_Pos)         /*!< 0x00000030 */
4957 #define OPAMP_CSR_PGA_GAIN                  OPAMP_CSR_PGA_GAIN_Msk                    /*!< Operational amplifier Programmable amplifier gain value */
4958 #define OPAMP_CSR_PGA_GAIN_0                (0x1UL << OPAMP_CSR_PGA_GAIN_Pos)         /*!< 0x00000010 */
4959 #define OPAMP_CSR_PGA_GAIN_1                (0x2UL << OPAMP_CSR_PGA_GAIN_Pos)         /*!< 0x00000020 */
4960 
4961 #define OPAMP_CSR_VM_SEL_Pos                (8U)
4962 #define OPAMP_CSR_VM_SEL_Msk                (0x3UL << OPAMP_CSR_VM_SEL_Pos)           /*!< 0x00000300 */
4963 #define OPAMP_CSR_VM_SEL                    OPAMP_CSR_VM_SEL_Msk                      /*!< Inverting input selection */
4964 #define OPAMP_CSR_VM_SEL_0                  (0x1UL << OPAMP_CSR_VM_SEL_Pos)           /*!< 0x00000100 */
4965 #define OPAMP_CSR_VM_SEL_1                  (0x2UL << OPAMP_CSR_VM_SEL_Pos)           /*!< 0x00000200 */
4966 
4967 #define OPAMP_CSR_VP_SEL_Pos                (10U)
4968 #define OPAMP_CSR_VP_SEL_Msk                (0x1UL << OPAMP_CSR_VP_SEL_Pos)           /*!< 0x00000400 */
4969 #define OPAMP_CSR_VP_SEL                    OPAMP_CSR_VP_SEL_Msk                      /*!< Non inverted input selection */
4970 
4971 #define OPAMP_CSR_CALON_Pos                 (12U)
4972 #define OPAMP_CSR_CALON_Msk                 (0x1UL << OPAMP_CSR_CALON_Pos)            /*!< 0x00001000 */
4973 #define OPAMP_CSR_CALON                     OPAMP_CSR_CALON_Msk                       /*!< Calibration mode enable */
4974 
4975 #define OPAMP_CSR_CALSEL_Pos                (13U)
4976 #define OPAMP_CSR_CALSEL_Msk                (0x1UL << OPAMP_CSR_CALSEL_Pos)           /*!< 0x00002000 */
4977 #define OPAMP_CSR_CALSEL                    OPAMP_CSR_CALSEL_Msk                      /*!< Calibration selection */
4978 
4979 #define OPAMP_CSR_USERTRIM_Pos              (14U)
4980 #define OPAMP_CSR_USERTRIM_Msk              (0x1UL << OPAMP_CSR_USERTRIM_Pos)         /*!< 0x00004000 */
4981 #define OPAMP_CSR_USERTRIM                  OPAMP_CSR_USERTRIM_Msk                    /*!< User trimming enable */
4982 
4983 #define OPAMP_CSR_CALOUT_Pos                (15U)
4984 #define OPAMP_CSR_CALOUT_Msk                (0x1UL << OPAMP_CSR_CALOUT_Pos)           /*!< 0x00008000 */
4985 #define OPAMP_CSR_CALOUT                    OPAMP_CSR_CALOUT_Msk                      /*!< Operational amplifier calibration output */
4986 
4987 #define OPAMP_CSR_OPARANGE_Pos              (31U)
4988 #define OPAMP_CSR_OPARANGE_Msk              (0x1UL << OPAMP_CSR_OPARANGE_Pos)         /*!< 0x80000000 */
4989 #define OPAMP_CSR_OPARANGE                  OPAMP_CSR_OPARANGE_Msk                    /*!< Operational amplifier range setting */
4990 
4991 /*******************  Bit definition for OPAMPx_OTR register  ******************/
4992 #define OPAMP_OTR_TRIMOFFSETN_Pos           (0U)
4993 #define OPAMP_OTR_TRIMOFFSETN_Msk           (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos)     /*!< 0x0000001F */
4994 #define OPAMP_OTR_TRIMOFFSETN               OPAMP_OTR_TRIMOFFSETN_Msk                 /*!< Trim for NMOS differential pairs */
4995 #define OPAMP_OTR_TRIMOFFSETP_Pos           (8U)
4996 #define OPAMP_OTR_TRIMOFFSETP_Msk           (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos)     /*!< 0x00001F00 */
4997 #define OPAMP_OTR_TRIMOFFSETP               OPAMP_OTR_TRIMOFFSETP_Msk                 /*!< Trim for PMOS differential pairs */
4998 
4999 /*******************  Bit definition for OPAMPx_LPOTR register  ****************/
5000 #define OPAMP_LPOTR_TRIMLPOFFSETN_Pos       (0U)
5001 #define OPAMP_LPOTR_TRIMLPOFFSETN_Msk       (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
5002 #define OPAMP_LPOTR_TRIMLPOFFSETN           OPAMP_LPOTR_TRIMLPOFFSETN_Msk             /*!< Trim for NMOS differential pairs */
5003 #define OPAMP_LPOTR_TRIMLPOFFSETP_Pos       (8U)
5004 #define OPAMP_LPOTR_TRIMLPOFFSETP_Msk       (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
5005 #define OPAMP_LPOTR_TRIMLPOFFSETP           OPAMP_LPOTR_TRIMLPOFFSETP_Msk             /*!< Trim for PMOS differential pairs */
5006 
5007 /******************************************************************************/
5008 /*                                                                            */
5009 /*                             Power Control                                  */
5010 /*                                                                            */
5011 /******************************************************************************/
5012 
5013 /********************  Bit definition for PWR_CR1 register  *******************/
5014 #define PWR_CR1_LPMS_Pos               (0U)
5015 #define PWR_CR1_LPMS_Msk               (0x7UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000007 */
5016 #define PWR_CR1_LPMS                   PWR_CR1_LPMS_Msk                        /*!< LPMS[2:0] Low-power mode selection field     */
5017 #define PWR_CR1_LPMS_0                 (0x1UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000001 */
5018 #define PWR_CR1_LPMS_1                 (0x2UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000002 */
5019 #define PWR_CR1_LPMS_2                 (0x4UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000004 */
5020 
5021 #define PWR_CR1_FPD_STOP_Pos           (3U)
5022 #define PWR_CR1_FPD_STOP_Msk           (0x1UL << PWR_CR1_FPD_STOP_Pos)         /*!< 0x00000008 */
5023 #define PWR_CR1_FPD_STOP               PWR_CR1_FPD_STOP_Msk                    /*!< Flash power down mode during stop */
5024 #define PWR_CR1_FPD_LPRUN_Pos          (4U)
5025 #define PWR_CR1_FPD_LPRUN_Msk          (0x1UL << PWR_CR1_FPD_LPRUN_Pos)        /*!< 0x00000010 */
5026 #define PWR_CR1_FPD_LPRUN              PWR_CR1_FPD_LPRUN_Msk                   /*!< Flash power down mode during low power run */
5027 #define PWR_CR1_FPD_LPSLP_Pos          (5U)
5028 #define PWR_CR1_FPD_LPSLP_Msk          (0x1UL << PWR_CR1_FPD_LPSLP_Pos)        /*!< 0x00000020 */
5029 #define PWR_CR1_FPD_LPSLP              PWR_CR1_FPD_LPSLP_Msk                   /*!< Flash power down mode during low power sleep */
5030 #define PWR_CR1_DBP_Pos                (8U)
5031 #define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */
5032 #define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable backup protection */
5033 #define PWR_CR1_VOS_Pos                (9U)
5034 #define PWR_CR1_VOS_Msk                (0x3UL << PWR_CR1_VOS_Pos)              /*!< 0x00000600 */
5035 #define PWR_CR1_VOS                    PWR_CR1_VOS_Msk                         /*!< VOS[1:0] VOltage Scaling range Selection field     */
5036 #define PWR_CR1_VOS_0                  (0x1UL << PWR_CR1_VOS_Pos)              /*!< 0x00000200 */
5037 #define PWR_CR1_VOS_1                  (0x2UL << PWR_CR1_VOS_Pos)              /*!< 0x00000400 */
5038 #define PWR_CR1_LPR_Pos                (14U)
5039 #define PWR_CR1_LPR_Msk                (0x1UL << PWR_CR1_LPR_Pos)              /*!< 0x00004000 */
5040 #define PWR_CR1_LPR                    PWR_CR1_LPR_Msk                         /*!< Low Power Run */
5041 
5042 /********************  Bit definition for PWR_CR2 register  *******************/
5043 #define PWR_CR2_PVDE_Pos               (0U)
5044 #define PWR_CR2_PVDE_Msk               (0x1UL << PWR_CR2_PVDE_Pos)             /*!< 0x00000001 */
5045 #define PWR_CR2_PVDE                   PWR_CR2_PVDE_Msk                        /*!< Programmable Voltage detector enable */
5046 #define PWR_CR2_PLS_Pos                (1U)
5047 #define PWR_CR2_PLS_Msk                (0x7UL << PWR_CR2_PLS_Pos)              /*!< 0x0000000E */
5048 #define PWR_CR2_PLS                    PWR_CR2_PLS_Msk                         /*!< Power Voltage Detector Level selection */
5049 #define PWR_CR2_PLS_0                  (0x1UL << PWR_CR2_PLS_Pos)              /*!< 0x00000002 */
5050 #define PWR_CR2_PLS_1                  (0x2UL << PWR_CR2_PLS_Pos)              /*!< 0x00000004 */
5051 #define PWR_CR2_PLS_2                  (0x4UL << PWR_CR2_PLS_Pos)              /*!< 0x00000008 */
5052 #define PWR_CR2_PVME1_Pos              (4U)
5053 #define PWR_CR2_PVME1_Msk              (0x1UL << PWR_CR2_PVME1_Pos)            /*!< 0x00000010 */
5054 #define PWR_CR2_PVME1                  PWR_CR2_PVME1_Msk                       /*!< Peripheral Voltage Monitoring Enable of VDDUSB */
5055 #define PWR_CR2_PVME3_Pos              (5U)
5056 #define PWR_CR2_PVME3_Msk              (0x1UL << PWR_CR2_PVME3_Pos)            /*!< 0x00000020 */
5057 #define PWR_CR2_PVME3                  PWR_CR2_PVME3_Msk                       /*!< Peripheral Voltage Monitoring Enable of VDDADC */
5058 #define PWR_CR2_PVME4_Pos              (6U)
5059 #define PWR_CR2_PVME4_Msk              (0x1UL << PWR_CR2_PVME4_Pos)            /*!< 0x00000040 */
5060 #define PWR_CR2_PVME4                  PWR_CR2_PVME4_Msk                       /*!< Peripheral Voltage Monitoring Enable of VDDDAC */
5061 #define PWR_CR2_USV_Pos                (10U)
5062 #define PWR_CR2_USV_Msk                (0x1UL << PWR_CR2_USV_Pos)              /*!< 0x00000400 */
5063 #define PWR_CR2_USV                    PWR_CR2_USV_Msk                         /*!< USB Supply Valid */
5064 
5065 /********************  Bit definition for PWR_CR3 register  *******************/
5066 #define PWR_CR3_EWUP1_Pos              (0U)
5067 #define PWR_CR3_EWUP1_Msk              (0x1UL << PWR_CR3_EWUP1_Pos)            /*!< 0x00000001 */
5068 #define PWR_CR3_EWUP1                  PWR_CR3_EWUP1_Msk                       /*!< Enable external WKUP pin 1 */
5069 #define PWR_CR3_EWUP2_Pos              (1U)
5070 #define PWR_CR3_EWUP2_Msk              (0x1UL << PWR_CR3_EWUP2_Pos)            /*!< 0x00000002 */
5071 #define PWR_CR3_EWUP2                  PWR_CR3_EWUP2_Msk                       /*!< Enable external WKUP pin 2 */
5072 #define PWR_CR3_EWUP3_Pos              (2U)
5073 #define PWR_CR3_EWUP3_Msk              (0x1UL << PWR_CR3_EWUP3_Pos)            /*!< 0x00000004 */
5074 #define PWR_CR3_EWUP3                  PWR_CR3_EWUP3_Msk                       /*!< Enable external WKUP pin 3 */
5075 #define PWR_CR3_EWUP4_Pos              (3U)
5076 #define PWR_CR3_EWUP4_Msk              (0x1UL << PWR_CR3_EWUP4_Pos)            /*!< 0x00000008 */
5077 #define PWR_CR3_EWUP4                  PWR_CR3_EWUP4_Msk                       /*!< Enable external WKUP pin 4 */
5078 #define PWR_CR3_EWUP5_Pos              (4U)
5079 #define PWR_CR3_EWUP5_Msk              (0x1UL << PWR_CR3_EWUP5_Pos)            /*!< 0x00000010 */
5080 #define PWR_CR3_EWUP5                  PWR_CR3_EWUP5_Msk                       /*!< Enable external WKUP pin 5 */
5081 #define PWR_CR3_EWUP7_Pos              (6U)
5082 #define PWR_CR3_EWUP7_Msk              (0x1UL << PWR_CR3_EWUP7_Pos)            /*!< 0x00000040 */
5083 #define PWR_CR3_EWUP7                  PWR_CR3_EWUP7_Msk                       /*!< Enable external WKUP pin 7 */
5084 
5085 #define PWR_CR3_RRS_Pos                (8U)
5086 #define PWR_CR3_RRS_Msk                (0x1UL << PWR_CR3_RRS_Pos)              /*!< 0x00000100 */
5087 #define PWR_CR3_RRS                    PWR_CR3_RRS_Msk                         /*!< Ram retention in STANDBY mode */
5088 #define PWR_CR3_ENULP_Pos              (9U)
5089 #define PWR_CR3_ENULP_Msk              (0x1UL << PWR_CR3_ENULP_Pos)            /*!< 0x00000200 */
5090 #define PWR_CR3_ENULP                  PWR_CR3_ENULP_Msk                       /*!< Enable ULP BORL, BORH and PVD (resistor bridge sampling) for STOP2 and all Standby modes */
5091 #define PWR_CR3_APC_Pos                (10U)
5092 #define PWR_CR3_APC_Msk                (0x1UL << PWR_CR3_APC_Pos)              /*!< 0x00000400 */
5093 #define PWR_CR3_APC                    PWR_CR3_APC_Msk                         /*!< Apply pull-up and pull-down configuration */
5094 #define PWR_CR3_EIWUL_Pos              (15U)
5095 #define PWR_CR3_EIWUL_Msk              (0x1UL << PWR_CR3_EIWUL_Pos)            /*!< 0x00008000 */
5096 #define PWR_CR3_EIWUL                  PWR_CR3_EIWUL_Msk                       /*!< Enable Internal Wake-up line */
5097 
5098 /********************  Bit definition for PWR_CR4 register  ********************/
5099 #define PWR_CR4_WP1_Pos                (0U)
5100 #define PWR_CR4_WP1_Msk                (0x1UL << PWR_CR4_WP1_Pos)              /*!< 0x00000001 */
5101 #define PWR_CR4_WP1                    PWR_CR4_WP1_Msk                         /*!< Wake-Up pin 1 polarity */
5102 #define PWR_CR4_WP2_Pos                (1U)
5103 #define PWR_CR4_WP2_Msk                (0x1UL << PWR_CR4_WP2_Pos)              /*!< 0x00000002 */
5104 #define PWR_CR4_WP2                    PWR_CR4_WP2_Msk                         /*!< Wake-Up pin 2 polarity */
5105 #define PWR_CR4_WP3_Pos                (2U)
5106 #define PWR_CR4_WP3_Msk                (0x1UL << PWR_CR4_WP3_Pos)              /*!< 0x00000004 */
5107 #define PWR_CR4_WP3                    PWR_CR4_WP3_Msk                         /*!< Wake-Up pin 3 polarity */
5108 #define PWR_CR4_WP4_Pos                (3U)
5109 #define PWR_CR4_WP4_Msk                (0x1UL << PWR_CR4_WP4_Pos)              /*!< 0x00000008 */
5110 #define PWR_CR4_WP4                    PWR_CR4_WP4_Msk                         /*!< Wake-Up pin 4 polarity */
5111 #define PWR_CR4_WP5_Pos                (4U)
5112 #define PWR_CR4_WP5_Msk                (0x1UL << PWR_CR4_WP5_Pos)              /*!< 0x00000010 */
5113 #define PWR_CR4_WP5                    PWR_CR4_WP5_Msk                         /*!< Wake-Up pin 5 polarity */
5114 #define PWR_CR4_WP7_Pos                (6U)
5115 #define PWR_CR4_WP7_Msk                (0x1UL << PWR_CR4_WP7_Pos)              /*!< 0x00000040 */
5116 #define PWR_CR4_WP7                    PWR_CR4_WP7_Msk                         /*!< Wake-Up pin 7 polarity */
5117 #define PWR_CR4_VBE_Pos                (8U)
5118 #define PWR_CR4_VBE_Msk                (0x1UL << PWR_CR4_VBE_Pos)              /*!< 0x00000100 */
5119 #define PWR_CR4_VBE                    PWR_CR4_VBE_Msk                         /*!< VBAT Battery charging Enable */
5120 #define PWR_CR4_VBRS_Pos               (9U)
5121 #define PWR_CR4_VBRS_Msk               (0x1UL << PWR_CR4_VBRS_Pos)             /*!< 0x00000200 */
5122 #define PWR_CR4_VBRS                   PWR_CR4_VBRS_Msk                        /*!< VBAT Battery charging Resistor Selection */
5123 
5124 /********************  Bit definition for PWR_SR1 register  ********************/
5125 #define PWR_SR1_WUF1_Pos               (0U)
5126 #define PWR_SR1_WUF1_Msk               (0x1UL << PWR_SR1_WUF1_Pos)             /*!< 0x00000001 */
5127 #define PWR_SR1_WUF1                   PWR_SR1_WUF1_Msk                        /*!< Wakeup Flag 1 */
5128 #define PWR_SR1_WUF2_Pos               (1U)
5129 #define PWR_SR1_WUF2_Msk               (0x1UL << PWR_SR1_WUF2_Pos)             /*!< 0x00000002 */
5130 #define PWR_SR1_WUF2                   PWR_SR1_WUF2_Msk                        /*!< Wakeup Flag 2 */
5131 #define PWR_SR1_WUF3_Pos               (2U)
5132 #define PWR_SR1_WUF3_Msk               (0x1UL << PWR_SR1_WUF3_Pos)             /*!< 0x00000004 */
5133 #define PWR_SR1_WUF3                   PWR_SR1_WUF3_Msk                        /*!< Wakeup Flag 3 */
5134 #define PWR_SR1_WUF4_Pos               (3U)
5135 #define PWR_SR1_WUF4_Msk               (0x1UL << PWR_SR1_WUF4_Pos)             /*!< 0x00000008 */
5136 #define PWR_SR1_WUF4                   PWR_SR1_WUF4_Msk                        /*!< Wakeup Flag 4 */
5137 #define PWR_SR1_WUF5_Pos               (4U)
5138 #define PWR_SR1_WUF5_Msk               (0x1UL << PWR_SR1_WUF5_Pos)             /*!< 0x00000010 */
5139 #define PWR_SR1_WUF5                   PWR_SR1_WUF5_Msk                        /*!< Wakeup Flag 5 */
5140 #define PWR_SR1_WUF7_Pos               (6U)
5141 #define PWR_SR1_WUF7_Msk               (0x1UL << PWR_SR1_WUF7_Pos)             /*!< 0x00000040 */
5142 #define PWR_SR1_WUF7                   PWR_SR1_WUF7_Msk                        /*!< Wakeup Flag 7 */
5143 
5144 #define PWR_SR1_SBF_Pos                (8U)
5145 #define PWR_SR1_SBF_Msk                (0x1UL << PWR_SR1_SBF_Pos)              /*!< 0x00000100 */
5146 #define PWR_SR1_SBF                    PWR_SR1_SBF_Msk                         /*!< Standby Flag  */
5147 
5148 #define PWR_SR1_STOPF_Pos              (9U)
5149 #define PWR_SR1_STOPF_Msk              (0x7UL << PWR_SR1_STOPF_Pos)            /*!< 0x00000E00 */
5150 #define PWR_SR1_STOPF                  PWR_SR1_STOPF_Msk                       /*!< STOPF[2:0] Stop Flags */
5151 #define PWR_SR1_STOPF_0                (0x1UL << PWR_SR1_STOPF_Pos)            /*!< 0x00000200 */
5152 #define PWR_SR1_STOPF_1                (0x2UL << PWR_SR1_STOPF_Pos)            /*!< 0x00000400 */
5153 #define PWR_SR1_STOPF_2                (0x4UL << PWR_SR1_STOPF_Pos)            /*!< 0x00000800 */
5154 #define PWR_SR1_WUFI_Pos               (15U)
5155 #define PWR_SR1_WUFI_Msk               (0x1UL << PWR_SR1_WUFI_Pos)             /*!< 0x00008000 */
5156 #define PWR_SR1_WUFI                   PWR_SR1_WUFI_Msk                        /*!< Wakeup Flag Internal */
5157 
5158 /********************  Bit definition for PWR_SR2 register  ********************/
5159 #define PWR_SR2_FLASH_RDY_Pos          (7U)
5160 #define PWR_SR2_FLASH_RDY_Msk          (0x1UL << PWR_SR2_FLASH_RDY_Pos)        /*!< 0x00000080 */
5161 #define PWR_SR2_FLASH_RDY              PWR_SR2_FLASH_RDY_Msk                   /*!< Flash Ready */
5162 #define PWR_SR2_REGLPS_Pos             (8U)
5163 #define PWR_SR2_REGLPS_Msk             (0x1UL << PWR_SR2_REGLPS_Pos)           /*!< 0x00000100 */
5164 #define PWR_SR2_REGLPS                 PWR_SR2_REGLPS_Msk                      /*!< Regulator Low Power started    */
5165 #define PWR_SR2_REGLPF_Pos             (9U)
5166 #define PWR_SR2_REGLPF_Msk             (0x1UL << PWR_SR2_REGLPF_Pos)           /*!< 0x00000200 */
5167 #define PWR_SR2_REGLPF                 PWR_SR2_REGLPF_Msk                      /*!< Regulator Low Power flag    */
5168 #define PWR_SR2_VOSF_Pos               (10U)
5169 #define PWR_SR2_VOSF_Msk               (0x1UL << PWR_SR2_VOSF_Pos)             /*!< 0x00000400 */
5170 #define PWR_SR2_VOSF                   PWR_SR2_VOSF_Msk                        /*!< VOltage Scaling Flag    */
5171 #define PWR_SR2_PVDO_Pos               (11U)
5172 #define PWR_SR2_PVDO_Msk               (0x1UL << PWR_SR2_PVDO_Pos)             /*!< 0x00000800 */
5173 #define PWR_SR2_PVDO                   PWR_SR2_PVDO_Msk                        /*!< Power Voltage Detector Output    */
5174 #define PWR_SR2_PVMO1_Pos              (12U)
5175 #define PWR_SR2_PVMO1_Msk              (0x1UL << PWR_SR2_PVMO1_Pos)            /*!< 0x00001000 */
5176 #define PWR_SR2_PVMO1                  PWR_SR2_PVMO1_Msk                       /*!< PVMO USB & PVME USB    */
5177 #define PWR_SR2_PVMO3_Pos              (14U)
5178 #define PWR_SR2_PVMO3_Msk              (0x1UL << PWR_SR2_PVMO3_Pos)            /*!< 0x00004000 */
5179 #define PWR_SR2_PVMO3                  PWR_SR2_PVMO3_Msk                       /*!< PVMO ADC & PVME ADC    */
5180 #define PWR_SR2_PVMO4_Pos              (15U)
5181 #define PWR_SR2_PVMO4_Msk              (0x1UL << PWR_SR2_PVMO4_Pos)            /*!< 0x00008000 */
5182 #define PWR_SR2_PVMO4                  PWR_SR2_PVMO4_Msk                       /*!< PVMO DAC & PVME DAC    */
5183 
5184 /********************  Bit definition for PWR_SCR register  ********************/
5185 #define PWR_SCR_CWUF1_Pos              (0U)
5186 #define PWR_SCR_CWUF1_Msk              (0x1UL << PWR_SCR_CWUF1_Pos)            /*!< 0x00000001 */
5187 #define PWR_SCR_CWUF1                  PWR_SCR_CWUF1_Msk                       /*!< Clear Wake-up Flag 1 */
5188 #define PWR_SCR_CWUF2_Pos              (1U)
5189 #define PWR_SCR_CWUF2_Msk              (0x1UL << PWR_SCR_CWUF2_Pos)            /*!< 0x00000002 */
5190 #define PWR_SCR_CWUF2                  PWR_SCR_CWUF2_Msk                       /*!< Clear Wake-up Flag 2 */
5191 #define PWR_SCR_CWUF3_Pos              (2U)
5192 #define PWR_SCR_CWUF3_Msk              (0x1UL << PWR_SCR_CWUF3_Pos)            /*!< 0x00000004 */
5193 #define PWR_SCR_CWUF3                  PWR_SCR_CWUF3_Msk                       /*!< Clear Wake-up Flag 3 */
5194 #define PWR_SCR_CWUF4_Pos              (3U)
5195 #define PWR_SCR_CWUF4_Msk              (0x1UL << PWR_SCR_CWUF4_Pos)            /*!< 0x00000008 */
5196 #define PWR_SCR_CWUF4                  PWR_SCR_CWUF4_Msk                       /*!< Clear Wake-up Flag 4 */
5197 #define PWR_SCR_CWUF5_Pos              (4U)
5198 #define PWR_SCR_CWUF5_Msk              (0x1UL << PWR_SCR_CWUF5_Pos)            /*!< 0x00000010 */
5199 #define PWR_SCR_CWUF5                  PWR_SCR_CWUF5_Msk                       /*!< Clear Wake-up Flag 5 */
5200 #define PWR_SCR_CWUF7_Pos              (6U)
5201 #define PWR_SCR_CWUF7_Msk              (0x1UL << PWR_SCR_CWUF7_Pos)            /*!< 0x00000040 */
5202 #define PWR_SCR_CWUF7                  PWR_SCR_CWUF7_Msk                       /*!< Clear Wake-up Flag 7 */
5203 #define PWR_SCR_CSBF_Pos               (8U)
5204 #define PWR_SCR_CSBF_Msk               (0x1UL << PWR_SCR_CSBF_Pos)             /*!< 0x00000100 */
5205 #define PWR_SCR_CSBF                   PWR_SCR_CSBF_Msk                        /*!< Clear Standby Flag  */
5206 
5207 /********************  Bit definition for PWR_PUCRA register  *****************/
5208 #define PWR_PUCRA_PU0_Pos         (0U)
5209 #define PWR_PUCRA_PU0_Msk         (0x1UL << PWR_PUCRA_PU0_Pos)                 /*!< 0x00000001 */
5210 #define PWR_PUCRA_PU0             PWR_PUCRA_PU0_Msk                            /*!< Pin PA0 Pull-Up set */
5211 #define PWR_PUCRA_PU1_Pos         (1U)
5212 #define PWR_PUCRA_PU1_Msk         (0x1UL << PWR_PUCRA_PU1_Pos)                 /*!< 0x00000002 */
5213 #define PWR_PUCRA_PU1             PWR_PUCRA_PU1_Msk                            /*!< Pin PA1 Pull-Up set */
5214 #define PWR_PUCRA_PU2_Pos         (2U)
5215 #define PWR_PUCRA_PU2_Msk         (0x1UL << PWR_PUCRA_PU2_Pos)                 /*!< 0x00000004 */
5216 #define PWR_PUCRA_PU2             PWR_PUCRA_PU2_Msk                            /*!< Pin PA2 Pull-Up set */
5217 #define PWR_PUCRA_PU3_Pos         (3U)
5218 #define PWR_PUCRA_PU3_Msk         (0x1UL << PWR_PUCRA_PU3_Pos)                 /*!< 0x00000008 */
5219 #define PWR_PUCRA_PU3             PWR_PUCRA_PU3_Msk                            /*!< Pin PA3 Pull-Up set */
5220 #define PWR_PUCRA_PU4_Pos         (4U)
5221 #define PWR_PUCRA_PU4_Msk         (0x1UL << PWR_PUCRA_PU4_Pos)                 /*!< 0x00000010 */
5222 #define PWR_PUCRA_PU4             PWR_PUCRA_PU4_Msk                            /*!< Pin PA4 Pull-Up set */
5223 #define PWR_PUCRA_PU5_Pos         (5U)
5224 #define PWR_PUCRA_PU5_Msk         (0x1UL << PWR_PUCRA_PU5_Pos)                 /*!< 0x00000020 */
5225 #define PWR_PUCRA_PU5             PWR_PUCRA_PU5_Msk                            /*!< Pin PA5 Pull-Up set */
5226 #define PWR_PUCRA_PU6_Pos         (6U)
5227 #define PWR_PUCRA_PU6_Msk         (0x1UL << PWR_PUCRA_PU6_Pos)                 /*!< 0x00000040 */
5228 #define PWR_PUCRA_PU6             PWR_PUCRA_PU6_Msk                            /*!< Pin PA6 Pull-Up set */
5229 #define PWR_PUCRA_PU7_Pos         (7U)
5230 #define PWR_PUCRA_PU7_Msk         (0x1UL << PWR_PUCRA_PU7_Pos)                 /*!< 0x00000080 */
5231 #define PWR_PUCRA_PU7             PWR_PUCRA_PU7_Msk                            /*!< Pin PA7 Pull-Up set */
5232 #define PWR_PUCRA_PU8_Pos         (8U)
5233 #define PWR_PUCRA_PU8_Msk         (0x1UL << PWR_PUCRA_PU8_Pos)                 /*!< 0x00000100 */
5234 #define PWR_PUCRA_PU8             PWR_PUCRA_PU8_Msk                            /*!< Pin PA8 Pull-Up set */
5235 #define PWR_PUCRA_PU9_Pos         (9U)
5236 #define PWR_PUCRA_PU9_Msk         (0x1UL << PWR_PUCRA_PU9_Pos)                 /*!< 0x00000200 */
5237 #define PWR_PUCRA_PU9             PWR_PUCRA_PU9_Msk                            /*!< Pin PA9 Pull-Up set */
5238 #define PWR_PUCRA_PU10_Pos        (10U)
5239 #define PWR_PUCRA_PU10_Msk        (0x1UL << PWR_PUCRA_PU10_Pos)                /*!< 0x00000400 */
5240 #define PWR_PUCRA_PU10            PWR_PUCRA_PU10_Msk                           /*!< Pin PA10 Pull-Up set */
5241 #define PWR_PUCRA_PU11_Pos        (11U)
5242 #define PWR_PUCRA_PU11_Msk        (0x1UL << PWR_PUCRA_PU11_Pos)                /*!< 0x00000800 */
5243 #define PWR_PUCRA_PU11            PWR_PUCRA_PU11_Msk                           /*!< Pin PA11 Pull-Up set */
5244 #define PWR_PUCRA_PU12_Pos        (12U)
5245 #define PWR_PUCRA_PU12_Msk        (0x1UL << PWR_PUCRA_PU12_Pos)                /*!< 0x00001000 */
5246 #define PWR_PUCRA_PU12            PWR_PUCRA_PU12_Msk                           /*!< Pin PA12 Pull-Up set */
5247 #define PWR_PUCRA_PU13_Pos        (13U)
5248 #define PWR_PUCRA_PU13_Msk        (0x1UL << PWR_PUCRA_PU13_Pos)                /*!< 0x00002000 */
5249 #define PWR_PUCRA_PU13            PWR_PUCRA_PU13_Msk                           /*!< Pin PA13 Pull-Up set */
5250 #define PWR_PUCRA_PU14_Pos        (14U)
5251 #define PWR_PUCRA_PU14_Msk        (0x1UL << PWR_PUCRA_PU14_Pos)                /*!< 0x00004000 */
5252 #define PWR_PUCRA_PU14            PWR_PUCRA_PU14_Msk                           /*!< Pin PA14 Pull-Up set */
5253 #define PWR_PUCRA_PU15_Pos        (15U)
5254 #define PWR_PUCRA_PU15_Msk        (0x1UL << PWR_PUCRA_PU15_Pos)                /*!< 0x00008000 */
5255 #define PWR_PUCRA_PU15            PWR_PUCRA_PU15_Msk                           /*!< Pin PA15 Pull-Up set */
5256 
5257 /********************  Bit definition for PWR_PDCRA register  *****************/
5258 #define PWR_PDCRA_PD0_Pos         (0U)
5259 #define PWR_PDCRA_PD0_Msk         (0x1UL << PWR_PDCRA_PD0_Pos)                 /*!< 0x00000001 */
5260 #define PWR_PDCRA_PD0             PWR_PDCRA_PD0_Msk                            /*!< Pin PA0 Pull-Down set */
5261 #define PWR_PDCRA_PD1_Pos         (1U)
5262 #define PWR_PDCRA_PD1_Msk         (0x1UL << PWR_PDCRA_PD1_Pos)                 /*!< 0x00000002 */
5263 #define PWR_PDCRA_PD1             PWR_PDCRA_PD1_Msk                            /*!< Pin PA1 Pull-Down set */
5264 #define PWR_PDCRA_PD2_Pos         (2U)
5265 #define PWR_PDCRA_PD2_Msk         (0x1UL << PWR_PDCRA_PD2_Pos)                 /*!< 0x00000004 */
5266 #define PWR_PDCRA_PD2             PWR_PDCRA_PD2_Msk                            /*!< Pin PA2 Pull-Down set */
5267 #define PWR_PDCRA_PD3_Pos         (3U)
5268 #define PWR_PDCRA_PD3_Msk         (0x1UL << PWR_PDCRA_PD3_Pos)                 /*!< 0x00000008 */
5269 #define PWR_PDCRA_PD3             PWR_PDCRA_PD3_Msk                            /*!< Pin PA3 Pull-Down set */
5270 #define PWR_PDCRA_PD4_Pos         (4U)
5271 #define PWR_PDCRA_PD4_Msk         (0x1UL << PWR_PDCRA_PD4_Pos)                 /*!< 0x00000010 */
5272 #define PWR_PDCRA_PD4             PWR_PDCRA_PD4_Msk                            /*!< Pin PA4 Pull-Down set */
5273 #define PWR_PDCRA_PD5_Pos         (5U)
5274 #define PWR_PDCRA_PD5_Msk         (0x1UL << PWR_PDCRA_PD5_Pos)                 /*!< 0x00000020 */
5275 #define PWR_PDCRA_PD5             PWR_PDCRA_PD5_Msk                            /*!< Pin PA5 Pull-Down set */
5276 #define PWR_PDCRA_PD6_Pos         (6U)
5277 #define PWR_PDCRA_PD6_Msk         (0x1UL << PWR_PDCRA_PD6_Pos)                 /*!< 0x00000040 */
5278 #define PWR_PDCRA_PD6             PWR_PDCRA_PD6_Msk                            /*!< Pin PA6 Pull-Down set */
5279 #define PWR_PDCRA_PD7_Pos         (7U)
5280 #define PWR_PDCRA_PD7_Msk         (0x1UL << PWR_PDCRA_PD7_Pos)                 /*!< 0x00000080 */
5281 #define PWR_PDCRA_PD7             PWR_PDCRA_PD7_Msk                            /*!< Pin PA7 Pull-Down set */
5282 #define PWR_PDCRA_PD8_Pos         (8U)
5283 #define PWR_PDCRA_PD8_Msk         (0x1UL << PWR_PDCRA_PD8_Pos)                 /*!< 0x00000100 */
5284 #define PWR_PDCRA_PD8             PWR_PDCRA_PD8_Msk                            /*!< Pin PA8 Pull-Down set */
5285 #define PWR_PDCRA_PD9_Pos         (9U)
5286 #define PWR_PDCRA_PD9_Msk         (0x1UL << PWR_PDCRA_PD9_Pos)                 /*!< 0x00000200 */
5287 #define PWR_PDCRA_PD9             PWR_PDCRA_PD9_Msk                            /*!< Pin PA9 Pull-Down set */
5288 #define PWR_PDCRA_PD10_Pos        (10U)
5289 #define PWR_PDCRA_PD10_Msk        (0x1UL << PWR_PDCRA_PD10_Pos)                /*!< 0x00000400 */
5290 #define PWR_PDCRA_PD10            PWR_PDCRA_PD10_Msk                           /*!< Pin PA10 Pull-Down set */
5291 #define PWR_PDCRA_PD11_Pos        (11U)
5292 #define PWR_PDCRA_PD11_Msk        (0x1UL << PWR_PDCRA_PD11_Pos)                /*!< 0x00000800 */
5293 #define PWR_PDCRA_PD11            PWR_PDCRA_PD11_Msk                           /*!< Pin PA11 Pull-Down set */
5294 #define PWR_PDCRA_PD12_Pos        (12U)
5295 #define PWR_PDCRA_PD12_Msk        (0x1UL << PWR_PDCRA_PD12_Pos)                /*!< 0x00001000 */
5296 #define PWR_PDCRA_PD12            PWR_PDCRA_PD12_Msk                           /*!< Pin PA12 Pull-Down set */
5297 #define PWR_PDCRA_PD13_Pos        (13U)
5298 #define PWR_PDCRA_PD13_Msk        (0x1UL << PWR_PDCRA_PD13_Pos)                /*!< 0x00002000 */
5299 #define PWR_PDCRA_PD13            PWR_PDCRA_PD13_Msk                           /*!< Pin PA13 Pull-Down set */
5300 #define PWR_PDCRA_PD14_Pos        (14U)
5301 #define PWR_PDCRA_PD14_Msk        (0x1UL << PWR_PDCRA_PD14_Pos)                /*!< 0x00004000 */
5302 #define PWR_PDCRA_PD14            PWR_PDCRA_PD14_Msk                           /*!< Pin PA14 Pull-Down set */
5303 #define PWR_PDCRA_PD15_Pos        (15U)
5304 #define PWR_PDCRA_PD15_Msk        (0x1UL << PWR_PDCRA_PD15_Pos)                /*!< 0x00008000 */
5305 #define PWR_PDCRA_PD15            PWR_PDCRA_PD15_Msk                           /*!< Pin PA15 Pull-Down set */
5306 
5307 /********************  Bit definition for PWR_PUCRB register  *****************/
5308 #define PWR_PUCRB_PU0_Pos         (0U)
5309 #define PWR_PUCRB_PU0_Msk         (0x1UL << PWR_PUCRB_PU0_Pos)                 /*!< 0x00000001 */
5310 #define PWR_PUCRB_PU0             PWR_PUCRB_PU0_Msk                            /*!< Pin PB0 Pull-Up set */
5311 #define PWR_PUCRB_PU1_Pos         (1U)
5312 #define PWR_PUCRB_PU1_Msk         (0x1UL << PWR_PUCRB_PU1_Pos)                 /*!< 0x00000002 */
5313 #define PWR_PUCRB_PU1             PWR_PUCRB_PU1_Msk                            /*!< Pin PB1 Pull-Up set */
5314 #define PWR_PUCRB_PU2_Pos         (2U)
5315 #define PWR_PUCRB_PU2_Msk         (0x1UL << PWR_PUCRB_PU2_Pos)                 /*!< 0x00000004 */
5316 #define PWR_PUCRB_PU2             PWR_PUCRB_PU2_Msk                            /*!< Pin PB2 Pull-Up set */
5317 #define PWR_PUCRB_PU3_Pos         (3U)
5318 #define PWR_PUCRB_PU3_Msk         (0x1UL << PWR_PUCRB_PU3_Pos)                 /*!< 0x00000008 */
5319 #define PWR_PUCRB_PU3             PWR_PUCRB_PU3_Msk                            /*!< Pin PB3 Pull-Up set */
5320 #define PWR_PUCRB_PU4_Pos         (4U)
5321 #define PWR_PUCRB_PU4_Msk         (0x1UL << PWR_PUCRB_PU4_Pos)                 /*!< 0x00000010 */
5322 #define PWR_PUCRB_PU4             PWR_PUCRB_PU4_Msk                            /*!< Pin PB4 Pull-Up set */
5323 #define PWR_PUCRB_PU5_Pos         (5U)
5324 #define PWR_PUCRB_PU5_Msk         (0x1UL << PWR_PUCRB_PU5_Pos)                 /*!< 0x00000020 */
5325 #define PWR_PUCRB_PU5             PWR_PUCRB_PU5_Msk                            /*!< Pin PB5 Pull-Up set */
5326 #define PWR_PUCRB_PU6_Pos         (6U)
5327 #define PWR_PUCRB_PU6_Msk         (0x1UL << PWR_PUCRB_PU6_Pos)                 /*!< 0x00000040 */
5328 #define PWR_PUCRB_PU6             PWR_PUCRB_PU6_Msk                            /*!< Pin PB6 Pull-Up set */
5329 #define PWR_PUCRB_PU7_Pos         (7U)
5330 #define PWR_PUCRB_PU7_Msk         (0x1UL << PWR_PUCRB_PU7_Pos)                 /*!< 0x00000080 */
5331 #define PWR_PUCRB_PU7             PWR_PUCRB_PU7_Msk                            /*!< Pin PB7 Pull-Up set */
5332 #define PWR_PUCRB_PU8_Pos         (8U)
5333 #define PWR_PUCRB_PU8_Msk         (0x1UL << PWR_PUCRB_PU8_Pos)                 /*!< 0x00000100 */
5334 #define PWR_PUCRB_PU8             PWR_PUCRB_PU8_Msk                            /*!< Pin PB8 Pull-Up set */
5335 #define PWR_PUCRB_PU9_Pos         (9U)
5336 #define PWR_PUCRB_PU9_Msk         (0x1UL << PWR_PUCRB_PU9_Pos)                 /*!< 0x00000200 */
5337 #define PWR_PUCRB_PU9             PWR_PUCRB_PU9_Msk                            /*!< Pin PB9 Pull-Up set */
5338 #define PWR_PUCRB_PU10_Pos        (10U)
5339 #define PWR_PUCRB_PU10_Msk        (0x1UL << PWR_PUCRB_PU10_Pos)                /*!< 0x00000400 */
5340 #define PWR_PUCRB_PU10            PWR_PUCRB_PU10_Msk                           /*!< Pin PB10 Pull-Up set */
5341 #define PWR_PUCRB_PU11_Pos        (11U)
5342 #define PWR_PUCRB_PU11_Msk        (0x1UL << PWR_PUCRB_PU11_Pos)                /*!< 0x00000800 */
5343 #define PWR_PUCRB_PU11            PWR_PUCRB_PU11_Msk                           /*!< Pin PB11 Pull-Up set */
5344 #define PWR_PUCRB_PU12_Pos        (12U)
5345 #define PWR_PUCRB_PU12_Msk        (0x1UL << PWR_PUCRB_PU12_Pos)                /*!< 0x00001000 */
5346 #define PWR_PUCRB_PU12            PWR_PUCRB_PU12_Msk                           /*!< Pin PB12 Pull-Up set */
5347 #define PWR_PUCRB_PU13_Pos        (13U)
5348 #define PWR_PUCRB_PU13_Msk        (0x1UL << PWR_PUCRB_PU13_Pos)                /*!< 0x00002000 */
5349 #define PWR_PUCRB_PU13            PWR_PUCRB_PU13_Msk                           /*!< Pin PB13 Pull-Up set */
5350 #define PWR_PUCRB_PU14_Pos        (14U)
5351 #define PWR_PUCRB_PU14_Msk        (0x1UL << PWR_PUCRB_PU14_Pos)                /*!< 0x00004000 */
5352 #define PWR_PUCRB_PU14            PWR_PUCRB_PU14_Msk                           /*!< Pin PB14 Pull-Up set */
5353 #define PWR_PUCRB_PU15_Pos        (15U)
5354 #define PWR_PUCRB_PU15_Msk        (0x1UL << PWR_PUCRB_PU15_Pos)                /*!< 0x00008000 */
5355 #define PWR_PUCRB_PU15            PWR_PUCRB_PU15_Msk                           /*!< Pin PB15 Pull-Up set */
5356 
5357 /********************  Bit definition for PWR_PDCRB register  *****************/
5358 #define PWR_PDCRB_PD0_Pos         (0U)
5359 #define PWR_PDCRB_PD0_Msk         (0x1UL << PWR_PDCRB_PD0_Pos)                 /*!< 0x00000001 */
5360 #define PWR_PDCRB_PD0             PWR_PDCRB_PD0_Msk                            /*!< Pin PB0 Pull-Down set */
5361 #define PWR_PDCRB_PD1_Pos         (1U)
5362 #define PWR_PDCRB_PD1_Msk         (0x1UL << PWR_PDCRB_PD1_Pos)                 /*!< 0x00000002 */
5363 #define PWR_PDCRB_PD1             PWR_PDCRB_PD1_Msk                            /*!< Pin PB1 Pull-Down set */
5364 #define PWR_PDCRB_PD2_Pos         (2U)
5365 #define PWR_PDCRB_PD2_Msk         (0x1UL << PWR_PDCRB_PD2_Pos)                 /*!< 0x00000004 */
5366 #define PWR_PDCRB_PD2             PWR_PDCRB_PD2_Msk                            /*!< Pin PB2 Pull-Down set */
5367 #define PWR_PDCRB_PD3_Pos         (3U)
5368 #define PWR_PDCRB_PD3_Msk         (0x1UL << PWR_PDCRB_PD3_Pos)                 /*!< 0x00000008 */
5369 #define PWR_PDCRB_PD3             PWR_PDCRB_PD3_Msk                            /*!< Pin PB3 Pull-Down set */
5370 #define PWR_PDCRB_PD4_Pos         (4U)
5371 #define PWR_PDCRB_PD4_Msk         (0x1UL << PWR_PDCRB_PD4_Pos)                 /*!< 0x00000010 */
5372 #define PWR_PDCRB_PD4             PWR_PDCRB_PD4_Msk                            /*!< Pin PB4 Pull-Down set */
5373 #define PWR_PDCRB_PD5_Pos         (5U)
5374 #define PWR_PDCRB_PD5_Msk         (0x1UL << PWR_PDCRB_PD5_Pos)                 /*!< 0x00000020 */
5375 #define PWR_PDCRB_PD5             PWR_PDCRB_PD5_Msk                            /*!< Pin PB5 Pull-Down set */
5376 #define PWR_PDCRB_PD6_Pos         (6U)
5377 #define PWR_PDCRB_PD6_Msk         (0x1UL << PWR_PDCRB_PD6_Pos)                 /*!< 0x00000040 */
5378 #define PWR_PDCRB_PD6             PWR_PDCRB_PD6_Msk                            /*!< Pin PB6 Pull-Down set */
5379 #define PWR_PDCRB_PD7_Pos         (7U)
5380 #define PWR_PDCRB_PD7_Msk         (0x1UL << PWR_PDCRB_PD7_Pos)                 /*!< 0x00000080 */
5381 #define PWR_PDCRB_PD7             PWR_PDCRB_PD7_Msk                            /*!< Pin PB7 Pull-Down set */
5382 #define PWR_PDCRB_PD8_Pos         (8U)
5383 #define PWR_PDCRB_PD8_Msk         (0x1UL << PWR_PDCRB_PD8_Pos)                 /*!< 0x00000100 */
5384 #define PWR_PDCRB_PD8             PWR_PDCRB_PD8_Msk                            /*!< Pin PB8 Pull-Down set */
5385 #define PWR_PDCRB_PD9_Pos         (9U)
5386 #define PWR_PDCRB_PD9_Msk         (0x1UL << PWR_PDCRB_PD9_Pos)                 /*!< 0x00000200 */
5387 #define PWR_PDCRB_PD9             PWR_PDCRB_PD9_Msk                            /*!< Pin PB9 Pull-Down set */
5388 #define PWR_PDCRB_PD10_Pos        (10U)
5389 #define PWR_PDCRB_PD10_Msk        (0x1UL << PWR_PDCRB_PD10_Pos)                /*!< 0x00000400 */
5390 #define PWR_PDCRB_PD10            PWR_PDCRB_PD10_Msk                           /*!< Pin PB10 Pull-Down set */
5391 #define PWR_PDCRB_PD11_Pos        (11U)
5392 #define PWR_PDCRB_PD11_Msk        (0x1UL << PWR_PDCRB_PD11_Pos)                /*!< 0x00000800 */
5393 #define PWR_PDCRB_PD11            PWR_PDCRB_PD11_Msk                           /*!< Pin PB11 Pull-Down set */
5394 #define PWR_PDCRB_PD12_Pos        (12U)
5395 #define PWR_PDCRB_PD12_Msk        (0x1UL << PWR_PDCRB_PD12_Pos)                /*!< 0x00001000 */
5396 #define PWR_PDCRB_PD12            PWR_PDCRB_PD12_Msk                           /*!< Pin PB12 Pull-Down set */
5397 #define PWR_PDCRB_PD13_Pos        (13U)
5398 #define PWR_PDCRB_PD13_Msk        (0x1UL << PWR_PDCRB_PD13_Pos)                /*!< 0x00002000 */
5399 #define PWR_PDCRB_PD13            PWR_PDCRB_PD13_Msk                           /*!< Pin PB13 Pull-Down set */
5400 #define PWR_PDCRB_PD14_Pos        (14U)
5401 #define PWR_PDCRB_PD14_Msk        (0x1UL << PWR_PDCRB_PD14_Pos)                /*!< 0x00004000 */
5402 #define PWR_PDCRB_PD14            PWR_PDCRB_PD14_Msk                           /*!< Pin PB14 Pull-Down set */
5403 #define PWR_PDCRB_PD15_Pos        (15U)
5404 #define PWR_PDCRB_PD15_Msk        (0x1UL << PWR_PDCRB_PD15_Pos)                /*!< 0x00008000 */
5405 #define PWR_PDCRB_PD15            PWR_PDCRB_PD15_Msk                           /*!< Pin PB15 Pull-Down set */
5406 
5407 /********************  Bit definition for PWR_PUCRC register  *****************/
5408 #define PWR_PUCRC_PU0_Pos         (0U)
5409 #define PWR_PUCRC_PU0_Msk         (0x1UL << PWR_PUCRC_PU0_Pos)                 /*!< 0x00000001 */
5410 #define PWR_PUCRC_PU0             PWR_PUCRC_PU0_Msk                            /*!< Pin PC0 Pull-Up set */
5411 #define PWR_PUCRC_PU1_Pos         (1U)
5412 #define PWR_PUCRC_PU1_Msk         (0x1UL << PWR_PUCRC_PU1_Pos)                 /*!< 0x00000002 */
5413 #define PWR_PUCRC_PU1             PWR_PUCRC_PU1_Msk                            /*!< Pin PC1 Pull-Up set */
5414 #define PWR_PUCRC_PU2_Pos         (2U)
5415 #define PWR_PUCRC_PU2_Msk         (0x1UL << PWR_PUCRC_PU2_Pos)                 /*!< 0x00000004 */
5416 #define PWR_PUCRC_PU2             PWR_PUCRC_PU2_Msk                            /*!< Pin PC2 Pull-Up set */
5417 #define PWR_PUCRC_PU3_Pos         (3U)
5418 #define PWR_PUCRC_PU3_Msk         (0x1UL << PWR_PUCRC_PU3_Pos)                 /*!< 0x00000008 */
5419 #define PWR_PUCRC_PU3             PWR_PUCRC_PU3_Msk                            /*!< Pin PC3 Pull-Up set */
5420 #define PWR_PUCRC_PU4_Pos         (4U)
5421 #define PWR_PUCRC_PU4_Msk         (0x1UL << PWR_PUCRC_PU4_Pos)                 /*!< 0x00000010 */
5422 #define PWR_PUCRC_PU4             PWR_PUCRB_PD4_Msk                            /*!< Pin PC4 Pull-Up set */
5423 #define PWR_PUCRC_PU5_Pos         (5U)
5424 #define PWR_PUCRC_PU5_Msk         (0x1UL << PWR_PUCRC_PU5_Pos)                 /*!< 0x00000020 */
5425 #define PWR_PUCRC_PU5             PWR_PUCRC_PU5_Msk                            /*!< Pin PC5 Pull-Up set */
5426 #define PWR_PUCRC_PU6_Pos         (6U)
5427 #define PWR_PUCRC_PU6_Msk         (0x1UL << PWR_PUCRC_PU6_Pos)                 /*!< 0x00000040 */
5428 #define PWR_PUCRC_PU6             PWR_PUCRC_PU6_Msk                            /*!< Pin PC6 Pull-Up set */
5429 #define PWR_PUCRC_PU7_Pos         (7U)
5430 #define PWR_PUCRC_PU7_Msk         (0x1UL << PWR_PUCRC_PU7_Pos)                 /*!< 0x00000080 */
5431 #define PWR_PUCRC_PU7             PWR_PUCRC_PU7_Msk                            /*!< Pin PC7 Pull-Up set */
5432 #define PWR_PUCRC_PU8_Pos         (8U)
5433 #define PWR_PUCRC_PU8_Msk         (0x1UL << PWR_PUCRC_PU8_Pos)                 /*!< 0x00000100 */
5434 #define PWR_PUCRC_PU8             PWR_PUCRC_PU8_Msk                            /*!< Pin PC8 Pull-Up set */
5435 #define PWR_PUCRC_PU9_Pos         (9U)
5436 #define PWR_PUCRC_PU9_Msk         (0x1UL << PWR_PUCRC_PU9_Pos)                 /*!< 0x00000200 */
5437 #define PWR_PUCRC_PU9             PWR_PUCRC_PU9_Msk                            /*!< Pin PC9 Pull-Up set */
5438 #define PWR_PUCRC_PU10_Pos        (10U)
5439 #define PWR_PUCRC_PU10_Msk        (0x1UL << PWR_PUCRC_PU10_Pos)                /*!< 0x00000400 */
5440 #define PWR_PUCRC_PU10            PWR_PUCRC_PU10_Msk                           /*!< Pin PC10 Pull-Up set */
5441 #define PWR_PUCRC_PU11_Pos        (11U)
5442 #define PWR_PUCRC_PU11_Msk        (0x1UL << PWR_PUCRC_PU11_Pos)                /*!< 0x00000800 */
5443 #define PWR_PUCRC_PU11            PWR_PUCRC_PU11_Msk                           /*!< Pin PC11 Pull-Up set */
5444 #define PWR_PUCRC_PU12_Pos        (12U)
5445 #define PWR_PUCRC_PU12_Msk        (0x1UL << PWR_PUCRC_PU12_Pos)                /*!< 0x00001000 */
5446 #define PWR_PUCRC_PU12            PWR_PUCRC_PU12_Msk                           /*!< Pin PC12 Pull-Up set */
5447 #define PWR_PUCRC_PU13_Pos        (13U)
5448 #define PWR_PUCRC_PU13_Msk        (0x1UL << PWR_PUCRC_PU13_Pos)                /*!< 0x00002000 */
5449 #define PWR_PUCRC_PU13            PWR_PUCRC_PU13_Msk                           /*!< Pin PC13 Pull-Up set */
5450 #define PWR_PUCRC_PU14_Pos        (14U)
5451 #define PWR_PUCRC_PU14_Msk        (0x1UL << PWR_PUCRC_PU14_Pos)                /*!< 0x00004000 */
5452 #define PWR_PUCRC_PU14            PWR_PUCRC_PU14_Msk                           /*!< Pin PC14 Pull-Up set */
5453 #define PWR_PUCRC_PU15_Pos        (15U)
5454 #define PWR_PUCRC_PU15_Msk        (0x1UL << PWR_PUCRC_PU15_Pos)                /*!< 0x00008000 */
5455 #define PWR_PUCRC_PU15            PWR_PUCRC_PU15_Msk                           /*!< Pin PC15 Pull-Up set */
5456 
5457 /********************  Bit definition for PWR_PDCRC register  *****************/
5458 #define PWR_PDCRC_PD0_Pos         (0U)
5459 #define PWR_PDCRC_PD0_Msk         (0x1UL << PWR_PDCRC_PD0_Pos)                 /*!< 0x00000001 */
5460 #define PWR_PDCRC_PD0             PWR_PDCRC_PD0_Msk                            /*!< Pin PC0 Pull-Down set */
5461 #define PWR_PDCRC_PD1_Pos         (1U)
5462 #define PWR_PDCRC_PD1_Msk         (0x1UL << PWR_PDCRC_PD1_Pos)                 /*!< 0x00000002 */
5463 #define PWR_PDCRC_PD1             PWR_PDCRC_PD1_Msk                            /*!< Pin PC1 Pull-Down set */
5464 #define PWR_PDCRC_PD2_Pos         (2U)
5465 #define PWR_PDCRC_PD2_Msk         (0x1UL << PWR_PDCRC_PD2_Pos)                 /*!< 0x00000004 */
5466 #define PWR_PDCRC_PD2             PWR_PDCRC_PD2_Msk                            /*!< Pin PC2 Pull-Down set */
5467 #define PWR_PDCRC_PD3_Pos         (3U)
5468 #define PWR_PDCRC_PD3_Msk         (0x1UL << PWR_PDCRC_PD3_Pos)                 /*!< 0x00000008 */
5469 #define PWR_PDCRC_PD3             PWR_PDCRC_PD3_Msk                            /*!< Pin PC3 Pull-Down set */
5470 #define PWR_PDCRC_PD4_Pos         (4U)
5471 #define PWR_PDCRC_PD4_Msk         (0x1UL << PWR_PDCRC_PD4_Pos)                 /*!< 0x00000010 */
5472 #define PWR_PDCRC_PD4             PWR_PUCRB_PD4_Msk                            /*!< Pin PC4 Pull-Down set */
5473 #define PWR_PDCRC_PD5_Pos         (5U)
5474 #define PWR_PDCRC_PD5_Msk         (0x1UL << PWR_PDCRC_PD5_Pos)                 /*!< 0x00000020 */
5475 #define PWR_PDCRC_PD5             PWR_PDCRC_PD5_Msk                            /*!< Pin PC5 Pull-Down set */
5476 #define PWR_PDCRC_PD6_Pos         (6U)
5477 #define PWR_PDCRC_PD6_Msk         (0x1UL << PWR_PDCRC_PD6_Pos)                 /*!< 0x00000040 */
5478 #define PWR_PDCRC_PD6             PWR_PDCRC_PD6_Msk                            /*!< Pin PC6 Pull-Down set */
5479 #define PWR_PDCRC_PD7_Pos         (7U)
5480 #define PWR_PDCRC_PD7_Msk         (0x1UL << PWR_PDCRC_PD7_Pos)                 /*!< 0x00000080 */
5481 #define PWR_PDCRC_PD7             PWR_PDCRC_PD7_Msk                            /*!< Pin PC7 Pull-Down set */
5482 #define PWR_PDCRC_PD8_Pos         (8U)
5483 #define PWR_PDCRC_PD8_Msk         (0x1UL << PWR_PDCRC_PD8_Pos)                 /*!< 0x00000100 */
5484 #define PWR_PDCRC_PD8             PWR_PDCRC_PD8_Msk                            /*!< Pin PC8 Pull-Down set */
5485 #define PWR_PDCRC_PD9_Pos         (9U)
5486 #define PWR_PDCRC_PD9_Msk         (0x1UL << PWR_PDCRC_PD9_Pos)                 /*!< 0x00000200 */
5487 #define PWR_PDCRC_PD9             PWR_PDCRC_PD9_Msk                            /*!< Pin PC9 Pull-Down set */
5488 #define PWR_PDCRC_PD10_Pos        (10U)
5489 #define PWR_PDCRC_PD10_Msk        (0x1UL << PWR_PDCRC_PD10_Pos)                /*!< 0x00000400 */
5490 #define PWR_PDCRC_PD10            PWR_PDCRC_PD10_Msk                           /*!< Pin PC10 Pull-Down set */
5491 #define PWR_PDCRC_PD11_Pos        (11U)
5492 #define PWR_PDCRC_PD11_Msk        (0x1UL << PWR_PDCRC_PD11_Pos)                /*!< 0x00000800 */
5493 #define PWR_PDCRC_PD11            PWR_PDCRC_PD11_Msk                           /*!< Pin PC11 Pull-Down set */
5494 #define PWR_PDCRC_PD12_Pos        (12U)
5495 #define PWR_PDCRC_PD12_Msk        (0x1UL << PWR_PDCRC_PD12_Pos)                /*!< 0x00001000 */
5496 #define PWR_PDCRC_PD12            PWR_PDCRC_PD12_Msk                           /*!< Pin PC12 Pull-Down set */
5497 #define PWR_PDCRC_PD13_Pos        (13U)
5498 #define PWR_PDCRC_PD13_Msk        (0x1UL << PWR_PDCRC_PD13_Pos)                /*!< 0x00002000 */
5499 #define PWR_PDCRC_PD13            PWR_PDCRC_PD13_Msk                           /*!< Pin PC13 Pull-Down set */
5500 #define PWR_PDCRC_PD14_Pos        (14U)
5501 #define PWR_PDCRC_PD14_Msk        (0x1UL << PWR_PDCRC_PD14_Pos)                /*!< 0x00004000 */
5502 #define PWR_PDCRC_PD14            PWR_PDCRC_PD14_Msk                           /*!< Pin PC14 Pull-Down set */
5503 #define PWR_PDCRC_PD15_Pos        (15U)
5504 #define PWR_PDCRC_PD15_Msk        (0x1UL << PWR_PDCRC_PD15_Pos)                /*!< 0x00008000 */
5505 #define PWR_PDCRC_PD15            PWR_PDCRC_PD15_Msk                           /*!< Pin PC15 Pull-Down set */
5506 
5507 /********************  Bit definition for PWR_PUCRD register  *****************/
5508 #define PWR_PUCRD_PU0_Pos         (0U)
5509 #define PWR_PUCRD_PU0_Msk         (0x1UL << PWR_PUCRD_PU0_Pos)                 /*!< 0x00000001 */
5510 #define PWR_PUCRD_PU0             PWR_PUCRD_PU0_Msk                            /*!< Pin PD0 Pull-Up set */
5511 #define PWR_PUCRD_PU1_Pos         (1U)
5512 #define PWR_PUCRD_PU1_Msk         (0x1UL << PWR_PUCRD_PU1_Pos)                 /*!< 0x00000002 */
5513 #define PWR_PUCRD_PU1             PWR_PUCRD_PU1_Msk                            /*!< Pin PD1 Pull-Up set */
5514 #define PWR_PUCRD_PU2_Pos         (2U)
5515 #define PWR_PUCRD_PU2_Msk         (0x1UL << PWR_PUCRD_PU2_Pos)                 /*!< 0x00000004 */
5516 #define PWR_PUCRD_PU2             PWR_PUCRD_PU2_Msk                            /*!< Pin PD2 Pull-Up set */
5517 #define PWR_PUCRD_PU3_Pos         (3U)
5518 #define PWR_PUCRD_PU3_Msk         (0x1UL << PWR_PUCRD_PU3_Pos)                 /*!< 0x00000008 */
5519 #define PWR_PUCRD_PU3             PWR_PUCRD_PU3_Msk                            /*!< Pin PD3 Pull-Up set */
5520 #define PWR_PUCRD_PU4_Pos         (4U)
5521 #define PWR_PUCRD_PU4_Msk         (0x1UL << PWR_PUCRD_PU4_Pos)                 /*!< 0x00000010 */
5522 #define PWR_PUCRD_PU4             PWR_PUCRD_PU4_Msk                            /*!< Pin PD4 Pull-Up set */
5523 #define PWR_PUCRD_PU5_Pos         (5U)
5524 #define PWR_PUCRD_PU5_Msk         (0x1UL << PWR_PUCRD_PU5_Pos)                 /*!< 0x00000020 */
5525 #define PWR_PUCRD_PU5             PWR_PUCRD_PU5_Msk                            /*!< Pin PD5 Pull-Up set */
5526 #define PWR_PUCRD_PU6_Pos         (6U)
5527 #define PWR_PUCRD_PU6_Msk         (0x1UL << PWR_PUCRD_PU6_Pos)                 /*!< 0x00000040 */
5528 #define PWR_PUCRD_PU6             PWR_PUCRD_PU6_Msk                            /*!< Pin PD6 Pull-Up set */
5529 #define PWR_PUCRD_PU8_Pos         (8U)
5530 #define PWR_PUCRD_PU8_Msk         (0x1UL << PWR_PUCRD_PU8_Pos)                 /*!< 0x00000100 */
5531 #define PWR_PUCRD_PU8             PWR_PUCRD_PU8_Msk                            /*!< Pin PD8 Pull-Up set */
5532 #define PWR_PUCRD_PU9_Pos         (9U)
5533 #define PWR_PUCRD_PU9_Msk         (0x1UL << PWR_PUCRD_PU9_Pos)                 /*!< 0x00000200 */
5534 #define PWR_PUCRD_PU9             PWR_PUCRD_PU9_Msk                            /*!< Pin PD9 Pull-Up set */
5535 #define PWR_PUCRD_PU10_Pos        (10U)
5536 #define PWR_PUCRD_PU10_Msk        (0x1UL << PWR_PUCRD_PU10_Pos)                /*!< 0x00000400 */
5537 #define PWR_PUCRD_PU10            PWR_PUCRD_PU10_Msk                           /*!< Pin PD10 Pull-Up set */
5538 #define PWR_PUCRD_PU11_Pos        (11U)
5539 #define PWR_PUCRD_PU11_Msk        (0x1UL << PWR_PUCRD_PU11_Pos)                /*!< 0x00000800 */
5540 #define PWR_PUCRD_PU11            PWR_PUCRD_PU11_Msk                           /*!< Pin PD11 Pull-Up set */
5541 #define PWR_PUCRD_PU12_Pos        (12U)
5542 #define PWR_PUCRD_PU12_Msk        (0x1UL << PWR_PUCRD_PU12_Pos)                /*!< 0x00001000 */
5543 #define PWR_PUCRD_PU12            PWR_PUCRD_PU12_Msk                           /*!< Pin PD12 Pull-Up set */
5544 #define PWR_PUCRD_PU13_Pos        (13U)
5545 #define PWR_PUCRD_PU13_Msk        (0x1UL << PWR_PUCRD_PU13_Pos)                /*!< 0x00002000 */
5546 #define PWR_PUCRD_PU13            PWR_PUCRD_PU13_Msk                           /*!< Pin PD13 Pull-Up set */
5547 
5548 /********************  Bit definition for PWR_PDCRD register  *****************/
5549 #define PWR_PDCRD_PD0_Pos         (0U)
5550 #define PWR_PDCRD_PD0_Msk         (0x1UL << PWR_PDCRD_PD0_Pos)                 /*!< 0x00000001 */
5551 #define PWR_PDCRD_PD0             PWR_PDCRD_PD0_Msk                            /*!< Pin PD0 Pull-Down set */
5552 #define PWR_PDCRD_PD1_Pos         (1U)
5553 #define PWR_PDCRD_PD1_Msk         (0x1UL << PWR_PDCRD_PD1_Pos)                 /*!< 0x00000002 */
5554 #define PWR_PDCRD_PD1             PWR_PDCRD_PD1_Msk                            /*!< Pin PD1 Pull-Down set */
5555 #define PWR_PDCRD_PD2_Pos         (2U)
5556 #define PWR_PDCRD_PD2_Msk         (0x1UL << PWR_PDCRD_PD2_Pos)                 /*!< 0x00000004 */
5557 #define PWR_PDCRD_PD2             PWR_PDCRD_PD2_Msk                            /*!< Pin PD2 Pull-Down set */
5558 #define PWR_PDCRD_PD3_Pos         (3U)
5559 #define PWR_PDCRD_PD3_Msk         (0x1UL << PWR_PDCRD_PD3_Pos)                 /*!< 0x00000008 */
5560 #define PWR_PDCRD_PD3             PWR_PDCRD_PD3_Msk                            /*!< Pin PD3 Pull-Down set */
5561 #define PWR_PDCRD_PD4_Pos         (4U)
5562 #define PWR_PDCRD_PD4_Msk         (0x1UL << PWR_PDCRD_PD4_Pos)                 /*!< 0x00000010 */
5563 #define PWR_PDCRD_PD4             PWR_PDCRD_PD4_Msk                            /*!< Pin PD4 Pull-Down set */
5564 #define PWR_PDCRD_PD5_Pos         (5U)
5565 #define PWR_PDCRD_PD5_Msk         (0x1UL << PWR_PDCRD_PD5_Pos)                 /*!< 0x00000020 */
5566 #define PWR_PDCRD_PD5             PWR_PDCRD_PD5_Msk                            /*!< Pin PD5 Pull-Down set */
5567 #define PWR_PDCRD_PD6_Pos         (6U)
5568 #define PWR_PDCRD_PD6_Msk         (0x1UL << PWR_PDCRD_PD6_Pos)                 /*!< 0x00000040 */
5569 #define PWR_PDCRD_PD6             PWR_PDCRD_PD6_Msk                            /*!< Pin PD6 Pull-Down set */
5570 #define PWR_PDCRD_PD8_Pos         (8U)
5571 #define PWR_PDCRD_PD8_Msk         (0x1UL << PWR_PDCRD_PD8_Pos)                 /*!< 0x00000100 */
5572 #define PWR_PDCRD_PD8             PWR_PDCRD_PD8_Msk                            /*!< Pin PD8 Pull-Down set */
5573 #define PWR_PDCRD_PD9_Pos         (9U)
5574 #define PWR_PDCRD_PD9_Msk         (0x1UL << PWR_PDCRD_PD9_Pos)                 /*!< 0x00000200 */
5575 #define PWR_PDCRD_PD9             PWR_PDCRD_PD9_Msk                            /*!< Pin PD9 Pull-Down set */
5576 #define PWR_PDCRD_PD10_Pos        (10U)
5577 #define PWR_PDCRD_PD10_Msk        (0x1UL << PWR_PDCRD_PD10_Pos)                /*!< 0x00000400 */
5578 #define PWR_PDCRD_PD10            PWR_PDCRD_PD10_Msk                           /*!< Pin PD10 Pull-Down set */
5579 #define PWR_PDCRD_PD11_Pos        (11U)
5580 #define PWR_PDCRD_PD11_Msk        (0x1UL << PWR_PDCRD_PD11_Pos)                /*!< 0x00000800 */
5581 #define PWR_PDCRD_PD11            PWR_PDCRD_PD11_Msk                           /*!< Pin PD11 Pull-Down set */
5582 #define PWR_PDCRD_PD12_Pos        (12U)
5583 #define PWR_PDCRD_PD12_Msk        (0x1UL << PWR_PDCRD_PD12_Pos)                /*!< 0x00001000 */
5584 #define PWR_PDCRD_PD12            PWR_PDCRD_PD12_Msk                           /*!< Pin PD12 Pull-Down set */
5585 #define PWR_PDCRD_PD13_Pos        (13U)
5586 #define PWR_PDCRD_PD13_Msk        (0x1UL << PWR_PDCRD_PD13_Pos)                /*!< 0x00002000 */
5587 #define PWR_PDCRD_PD13            PWR_PDCRD_PD13_Msk                           /*!< Pin PD13 Pull-Down set */
5588 
5589 /********************  Bit definition for PWR_PUCRE register  *****************/
5590 #define PWR_PUCRE_PU3_Pos         (3U)
5591 #define PWR_PUCRE_PU3_Msk         (0x1UL << PWR_PUCRE_PU3_Pos)                 /*!< 0x00000008 */
5592 #define PWR_PUCRE_PU3             PWR_PUCRE_PU3_Msk                            /*!< Pin PE3 Pull-Up set */
5593 #define PWR_PUCRE_PU7_Pos         (7U)
5594 #define PWR_PUCRE_PU7_Msk         (0x1UL << PWR_PUCRE_PU7_Pos)                 /*!< 0x00000080 */
5595 #define PWR_PUCRE_PU7             PWR_PUCRE_PU7_Msk                            /*!< Pin PE7 Pull-Up set */
5596 #define PWR_PUCRE_PU8_Pos         (8U)
5597 #define PWR_PUCRE_PU8_Msk         (0x1UL << PWR_PUCRE_PU8_Pos)                 /*!< 0x00000100 */
5598 #define PWR_PUCRE_PU8             PWR_PUCRE_PU8_Msk                            /*!< Pin PE8 Pull-Up set */
5599 #define PWR_PUCRE_PU9_Pos         (9U)
5600 #define PWR_PUCRE_PU9_Msk         (0x1UL << PWR_PUCRE_PU9_Pos)                 /*!< 0x00000200 */
5601 #define PWR_PUCRE_PU9             PWR_PUCRE_PU9_Msk                            /*!< Pin PE9 Pull-Up set */
5602 
5603 /********************  Bit definition for PWR_PDCRE register  *****************/
5604 #define PWR_PDCRE_PD3_Pos         (3U)
5605 #define PWR_PDCRE_PD3_Msk         (0x1UL << PWR_PDCRE_PD3_Pos)                 /*!< 0x00000008 */
5606 #define PWR_PDCRE_PD3             PWR_PDCRE_PD3_Msk                            /*!< Pin PE3 Pull-Down set */
5607 #define PWR_PDCRE_PD7_Pos         (7U)
5608 #define PWR_PDCRE_PD7_Msk         (0x1UL << PWR_PDCRE_PD7_Pos)                 /*!< 0x00000080 */
5609 #define PWR_PDCRE_PD7             PWR_PDCRE_PD7_Msk                            /*!< Pin PE7 Pull-Down set */
5610 #define PWR_PDCRE_PD8_Pos         (8U)
5611 #define PWR_PDCRE_PD8_Msk         (0x1UL << PWR_PDCRE_PD8_Pos)                 /*!< 0x00000100 */
5612 #define PWR_PDCRE_PD8             PWR_PDCRE_PD8_Msk                            /*!< Pin PE8 Pull-Down set */
5613 #define PWR_PDCRE_PD9_Pos         (9U)
5614 #define PWR_PDCRE_PD9_Msk         (0x1UL << PWR_PDCRE_PD9_Pos)                 /*!< 0x00000200 */
5615 #define PWR_PDCRE_PD9             PWR_PDCRE_PD9_Msk                            /*!< Pin PE9 Pull-Down set */
5616 
5617 /********************  Bit definition for PWR_PUCRF register  *****************/
5618 #define PWR_PUCRF_PU0_Pos         (0U)
5619 #define PWR_PUCRF_PU0_Msk         (0x1UL << PWR_PUCRF_PU0_Pos)                 /*!< 0x00000001 */
5620 #define PWR_PUCRF_PU0             PWR_PUCRF_PU0_Msk                            /*!< Pin PF0 Pull-Up set */
5621 #define PWR_PUCRF_PU1_Pos         (1U)
5622 #define PWR_PUCRF_PU1_Msk         (0x1UL << PWR_PUCRF_PU1_Pos)                 /*!< 0x00000002 */
5623 #define PWR_PUCRF_PU1             PWR_PUCRF_PU1_Msk                            /*!< Pin PF1 Pull-Up set */
5624 #define PWR_PUCRF_PU2_Pos         (2U)
5625 #define PWR_PUCRF_PU2_Msk         (0x1UL << PWR_PUCRF_PU2_Pos)                 /*!< 0x00000004 */
5626 #define PWR_PUCRF_PU2             PWR_PUCRF_PU2_Msk                            /*!< Pin PF2 Pull-Up set */
5627 #define PWR_PUCRF_PU3_Pos         (3U)
5628 #define PWR_PUCRF_PU3_Msk         (0x1UL << PWR_PUCRF_PU3_Pos)                 /*!< 0x00000008 */
5629 #define PWR_PUCRF_PU3             PWR_PUCRF_PU3_Msk                            /*!< Pin PF3 Pull-Up set */
5630 
5631 /********************  Bit definition for PWR_PDCRF register  *****************/
5632 #define PWR_PDCRF_PD0_Pos         (0U)
5633 #define PWR_PDCRF_PD0_Msk         (0x1UL << PWR_PDCRF_PD0_Pos)                 /*!< 0x00000001 */
5634 #define PWR_PDCRF_PD0             PWR_PDCRF_PD0_Msk                            /*!< Pin PF0 Pull-Down set */
5635 #define PWR_PDCRF_PD1_Pos         (1U)
5636 #define PWR_PDCRF_PD1_Msk         (0x1UL << PWR_PDCRF_PD1_Pos)                 /*!< 0x00000002 */
5637 #define PWR_PDCRF_PD1             PWR_PDCRF_PD1_Msk                            /*!< Pin PF1 Pull-Down set */
5638 #define PWR_PDCRF_PD2_Pos         (2U)
5639 #define PWR_PDCRF_PD2_Msk         (0x1UL << PWR_PDCRF_PD2_Pos)                 /*!< 0x00000004 */
5640 #define PWR_PDCRF_PD2             PWR_PDCRF_PD2_Msk                            /*!< Pin PF2 Pull-Down set */
5641 #define PWR_PDCRF_PD3_Pos         (3U)
5642 #define PWR_PDCRF_PD3_Msk         (0x1UL << PWR_PDCRF_PD3_Pos)                 /*!< 0x00000008 */
5643 #define PWR_PDCRF_PD3             PWR_PDCRF_PD3_Msk                            /*!< Pin PF3 Pull-Down set */
5644 
5645 
5646 /******************************************************************************/
5647 /*                                                                            */
5648 /*                           Reset and Clock Control                          */
5649 /*                                                                            */
5650 /******************************************************************************/
5651 
5652 /********************  Bit definition for RCC_CR register  ********************/
5653 #define RCC_CR_MSION_Pos                     (0U)
5654 #define RCC_CR_MSION_Msk                     (0x1UL << RCC_CR_MSION_Pos)       /*!< 0x00000001 */
5655 #define RCC_CR_MSION                         RCC_CR_MSION_Msk                  /*!< Internal Multi Speed oscillator (MSI) clock enable */
5656 #define RCC_CR_MSIRDY_Pos                    (1U)
5657 #define RCC_CR_MSIRDY_Msk                    (0x1UL << RCC_CR_MSIRDY_Pos)      /*!< 0x00000002 */
5658 #define RCC_CR_MSIRDY                        RCC_CR_MSIRDY_Msk                 /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
5659 #define RCC_CR_MSIPLLEN_Pos                  (2U)
5660 #define RCC_CR_MSIPLLEN_Msk                  (0x1UL << RCC_CR_MSIPLLEN_Pos)    /*!< 0x00000004 */
5661 #define RCC_CR_MSIPLLEN                      RCC_CR_MSIPLLEN_Msk               /*!< Internal Multi Speed oscillator (MSI) PLL enable */
5662 #define RCC_CR_MSIRGSEL_Pos                  (3U)
5663 #define RCC_CR_MSIRGSEL_Msk                  (0x1UL << RCC_CR_MSIRGSEL_Pos)    /*!< 0x00000008 */
5664 #define RCC_CR_MSIRGSEL                      RCC_CR_MSIRGSEL_Msk               /*!< Internal Multi Speed oscillator (MSI) range selection */
5665 
5666 /*!< MSIRANGE configuration : 12 frequency ranges available */
5667 #define RCC_CR_MSIRANGE_Pos                  (4U)
5668 #define RCC_CR_MSIRANGE_Msk                  (0xFUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000F0 */
5669 #define RCC_CR_MSIRANGE                      RCC_CR_MSIRANGE_Msk               /*!< Internal Multi Speed oscillator (MSI) clock Range */
5670 #define RCC_CR_MSIRANGE_0                    (0x0UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000000 */
5671 #define RCC_CR_MSIRANGE_1                    (0x1UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000010 */
5672 #define RCC_CR_MSIRANGE_2                    (0x2UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000020 */
5673 #define RCC_CR_MSIRANGE_3                    (0x3UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000030 */
5674 #define RCC_CR_MSIRANGE_4                    (0x4UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000040 */
5675 #define RCC_CR_MSIRANGE_5                    (0x5UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000050 */
5676 #define RCC_CR_MSIRANGE_6                    (0x6UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000060 */
5677 #define RCC_CR_MSIRANGE_7                    (0x7UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000070 */
5678 #define RCC_CR_MSIRANGE_8                    (0x8UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000080 */
5679 #define RCC_CR_MSIRANGE_9                    (0x9UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000090 */
5680 #define RCC_CR_MSIRANGE_10                   (0xAUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000A0 */
5681 #define RCC_CR_MSIRANGE_11                   (0xBUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000B0 */
5682 
5683 #define RCC_CR_HSION_Pos                     (8U)
5684 #define RCC_CR_HSION_Msk                     (0x1UL << RCC_CR_HSION_Pos)       /*!< 0x00000100 */
5685 #define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */
5686 #define RCC_CR_HSIKERON_Pos                  (9U)
5687 #define RCC_CR_HSIKERON_Msk                  (0x1UL << RCC_CR_HSIKERON_Pos)    /*!< 0x00000200 */
5688 #define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
5689 #define RCC_CR_HSIRDY_Pos                    (10U)
5690 #define RCC_CR_HSIRDY_Msk                    (0x1UL << RCC_CR_HSIRDY_Pos)      /*!< 0x00000400 */
5691 #define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */
5692 #define RCC_CR_HSIASFS_Pos                   (11U)
5693 #define RCC_CR_HSIASFS_Msk                   (0x1UL << RCC_CR_HSIASFS_Pos)     /*!< 0x00000800 */
5694 #define RCC_CR_HSIASFS                       RCC_CR_HSIASFS_Msk                /*!< HSI16 Automatic Start from Stop */
5695 
5696 #define RCC_CR_HSEON_Pos                     (16U)
5697 #define RCC_CR_HSEON_Msk                     (0x1UL << RCC_CR_HSEON_Pos)       /*!< 0x00010000 */
5698 #define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */
5699 #define RCC_CR_HSERDY_Pos                    (17U)
5700 #define RCC_CR_HSERDY_Msk                    (0x1UL << RCC_CR_HSERDY_Pos)      /*!< 0x00020000 */
5701 #define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */
5702 #define RCC_CR_HSEBYP_Pos                    (18U)
5703 #define RCC_CR_HSEBYP_Msk                    (0x1UL << RCC_CR_HSEBYP_Pos)      /*!< 0x00040000 */
5704 #define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed oscillator (HSE) clock bypass */
5705 #define RCC_CR_CSSON_Pos                     (19U)
5706 #define RCC_CR_CSSON_Msk                     (0x1UL << RCC_CR_CSSON_Pos)       /*!< 0x00080000 */
5707 #define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */
5708 
5709 #define RCC_CR_PLLON_Pos                     (24U)
5710 #define RCC_CR_PLLON_Msk                     (0x1UL << RCC_CR_PLLON_Pos)       /*!< 0x01000000 */
5711 #define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */
5712 #define RCC_CR_PLLRDY_Pos                    (25U)
5713 #define RCC_CR_PLLRDY_Msk                    (0x1UL << RCC_CR_PLLRDY_Pos)      /*!< 0x02000000 */
5714 #define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */
5715 
5716 /********************  Bit definition for RCC_ICSCR register  ***************/
5717 /*!< MSICAL configuration */
5718 #define RCC_ICSCR_MSICAL_Pos                 (0U)
5719 #define RCC_ICSCR_MSICAL_Msk                 (0xFFUL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x000000FF */
5720 #define RCC_ICSCR_MSICAL                     RCC_ICSCR_MSICAL_Msk              /*!< MSICAL[7:0] bits */
5721 #define RCC_ICSCR_MSICAL_0                   (0x01UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000001 */
5722 #define RCC_ICSCR_MSICAL_1                   (0x02UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000002 */
5723 #define RCC_ICSCR_MSICAL_2                   (0x04UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000004 */
5724 #define RCC_ICSCR_MSICAL_3                   (0x08UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000008 */
5725 #define RCC_ICSCR_MSICAL_4                   (0x10UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000010 */
5726 #define RCC_ICSCR_MSICAL_5                   (0x20UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000020 */
5727 #define RCC_ICSCR_MSICAL_6                   (0x40UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000040 */
5728 #define RCC_ICSCR_MSICAL_7                   (0x80UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000080 */
5729 
5730 /*!< MSITRIM configuration */
5731 #define RCC_ICSCR_MSITRIM_Pos                (8U)
5732 #define RCC_ICSCR_MSITRIM_Msk                (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */
5733 #define RCC_ICSCR_MSITRIM                    RCC_ICSCR_MSITRIM_Msk             /*!< MSITRIM[7:0] bits */
5734 #define RCC_ICSCR_MSITRIM_0                  (0x01UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000100 */
5735 #define RCC_ICSCR_MSITRIM_1                  (0x02UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000200 */
5736 #define RCC_ICSCR_MSITRIM_2                  (0x04UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000400 */
5737 #define RCC_ICSCR_MSITRIM_3                  (0x08UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000800 */
5738 #define RCC_ICSCR_MSITRIM_4                  (0x10UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00001000 */
5739 #define RCC_ICSCR_MSITRIM_5                  (0x20UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00002000 */
5740 #define RCC_ICSCR_MSITRIM_6                  (0x40UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00004000 */
5741 #define RCC_ICSCR_MSITRIM_7                  (0x80UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00008000 */
5742 
5743 /*!< HSICAL configuration */
5744 #define RCC_ICSCR_HSICAL_Pos                 (16U)
5745 #define RCC_ICSCR_HSICAL_Msk                 (0xFFUL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00FF0000 */
5746 #define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */
5747 #define RCC_ICSCR_HSICAL_0                   (0x01UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00010000 */
5748 #define RCC_ICSCR_HSICAL_1                   (0x02UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00020000 */
5749 #define RCC_ICSCR_HSICAL_2                   (0x04UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00040000 */
5750 #define RCC_ICSCR_HSICAL_3                   (0x08UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00080000 */
5751 #define RCC_ICSCR_HSICAL_4                   (0x10UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00100000 */
5752 #define RCC_ICSCR_HSICAL_5                   (0x20UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00200000 */
5753 #define RCC_ICSCR_HSICAL_6                   (0x40UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00400000 */
5754 #define RCC_ICSCR_HSICAL_7                   (0x80UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00800000 */
5755 
5756 /*!< HSITRIM configuration */
5757 #define RCC_ICSCR_HSITRIM_Pos                (24U)
5758 #define RCC_ICSCR_HSITRIM_Msk                (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
5759 #define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[6:0] bits */
5760 #define RCC_ICSCR_HSITRIM_0                  (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
5761 #define RCC_ICSCR_HSITRIM_1                  (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
5762 #define RCC_ICSCR_HSITRIM_2                  (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
5763 #define RCC_ICSCR_HSITRIM_3                  (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
5764 #define RCC_ICSCR_HSITRIM_4                  (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
5765 #define RCC_ICSCR_HSITRIM_5                  (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
5766 #define RCC_ICSCR_HSITRIM_6                  (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
5767 
5768 /********************  Bit definition for RCC_CFGR register  ***************/
5769 /*!< SW configuration */
5770 #define RCC_CFGR_SW_Pos                (0U)
5771 #define RCC_CFGR_SW_Msk                (0x7UL << RCC_CFGR_SW_Pos)              /*!< 0x00000007 */
5772 #define RCC_CFGR_SW                    RCC_CFGR_SW_Msk                         /*!< SW[2:0] bits (System clock Switch) */
5773 #define RCC_CFGR_SW_0                  (0x1UL << RCC_CFGR_SW_Pos)              /*!< 0x00000001 */
5774 #define RCC_CFGR_SW_1                  (0x2UL << RCC_CFGR_SW_Pos)              /*!< 0x00000002 */
5775 #define RCC_CFGR_SW_2                  (0x4UL << RCC_CFGR_SW_Pos)              /*!< 0x00000004 */
5776 
5777 /*!< SWS configuration */
5778 #define RCC_CFGR_SWS_Pos               (3U)
5779 #define RCC_CFGR_SWS_Msk               (0x7UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000038 */
5780 #define RCC_CFGR_SWS                   RCC_CFGR_SWS_Msk                        /*!< SWS[2:0] bits (System Clock Switch Status) */
5781 #define RCC_CFGR_SWS_0                 (0x1UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000008 */
5782 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
5783 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
5784 
5785 /*!< HPRE configuration */
5786 #define RCC_CFGR_HPRE_Pos              (8U)
5787 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */
5788 #define RCC_CFGR_HPRE                  RCC_CFGR_HPRE_Msk                       /*!< HPRE[3:0] bits (AHB prescaler) */
5789 #define RCC_CFGR_HPRE_0                (0x1UL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000100 */
5790 #define RCC_CFGR_HPRE_1                (0x2UL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000200 */
5791 #define RCC_CFGR_HPRE_2                (0x4UL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000400 */
5792 #define RCC_CFGR_HPRE_3                (0x8UL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000800 */
5793 
5794 /*!< PPRE configuration */
5795 #define RCC_CFGR_PPRE_Pos              (12U)
5796 #define RCC_CFGR_PPRE_Msk              (0x7UL << RCC_CFGR_PPRE_Pos)            /*!< 0x00007000 */
5797 #define RCC_CFGR_PPRE                  RCC_CFGR_PPRE_Msk                       /*!< PRE1[2:0] bits (APB prescaler) */
5798 #define RCC_CFGR_PPRE_0                (0x1UL << RCC_CFGR_PPRE_Pos)            /*!< 0x00001000 */
5799 #define RCC_CFGR_PPRE_1                (0x2UL << RCC_CFGR_PPRE_Pos)            /*!< 0x00002000 */
5800 #define RCC_CFGR_PPRE_2                (0x4UL << RCC_CFGR_PPRE_Pos)            /*!< 0x00004000 */
5801 
5802 /*!< STOPWUCK configuration */
5803 #define RCC_CFGR_STOPWUCK_Pos          (15U)
5804 #define RCC_CFGR_STOPWUCK_Msk          (0x1UL << RCC_CFGR_STOPWUCK_Pos)        /*!< 0x00008000 */
5805 #define RCC_CFGR_STOPWUCK              RCC_CFGR_STOPWUCK_Msk                   /*!< Wake Up from stop and CSS backup clock selection */
5806 
5807 /*!< MCOSEL configuration */
5808 #define RCC_CFGR_MCO2SEL_Pos            (16U)
5809 #define RCC_CFGR_MCO2SEL_Msk            (0xFUL << RCC_CFGR_MCO2SEL_Pos)        /*!< 0x000F0000 */
5810 #define RCC_CFGR_MCO2SEL                RCC_CFGR_MCO2SEL_Msk                   /*!< MCO2SEL [3:0] bits (Clock output selection) */
5811 #define RCC_CFGR_MCO2SEL_0              (0x1UL << RCC_CFGR_MCO2SEL_Pos)        /*!< 0x00010000 */
5812 #define RCC_CFGR_MCO2SEL_1              (0x2UL << RCC_CFGR_MCO2SEL_Pos)        /*!< 0x00020000 */
5813 #define RCC_CFGR_MCO2SEL_2              (0x4UL << RCC_CFGR_MCO2SEL_Pos)        /*!< 0x00040000 */
5814 #define RCC_CFGR_MCO2SEL_3              (0x8UL << RCC_CFGR_MCO2SEL_Pos)        /*!< 0x00080000 */
5815 
5816 /*!< MCO Prescaler configuration */
5817 #define RCC_CFGR_MCO2PRE_Pos            (20U)
5818 #define RCC_CFGR_MCO2PRE_Msk            (0xFUL << RCC_CFGR_MCO2PRE_Pos)        /*!< 0x00F00000 */
5819 #define RCC_CFGR_MCO2PRE                RCC_CFGR_MCO2PRE_Msk                   /*!< MCO1 prescaler [3:0] */
5820 #define RCC_CFGR_MCO2PRE_0              (0x1UL << RCC_CFGR_MCO2PRE_Pos)        /*!< 0x00100000 */
5821 #define RCC_CFGR_MCO2PRE_1              (0x2UL << RCC_CFGR_MCO2PRE_Pos)        /*!< 0x00200000 */
5822 #define RCC_CFGR_MCO2PRE_2              (0x4UL << RCC_CFGR_MCO2PRE_Pos)        /*!< 0x00400000 */
5823 #define RCC_CFGR_MCO2PRE_3              (0x8UL << RCC_CFGR_MCO2PRE_Pos)        /*!< 0x00800000 */
5824 
5825 /*!< MCOSEL configuration */
5826 #define RCC_CFGR_MCO1SEL_Pos            (24U)
5827 #define RCC_CFGR_MCO1SEL_Msk            (0xFUL << RCC_CFGR_MCO1SEL_Pos)        /*!< 0x0F000000 */
5828 #define RCC_CFGR_MCO1SEL                RCC_CFGR_MCO1SEL_Msk                   /*!< MCO1SEL [3:0] bits (Clock output selection) */
5829 #define RCC_CFGR_MCO1SEL_0              (0x1UL << RCC_CFGR_MCO1SEL_Pos)        /*!< 0x01000000 */
5830 #define RCC_CFGR_MCO1SEL_1              (0x2UL << RCC_CFGR_MCO1SEL_Pos)        /*!< 0x02000000 */
5831 #define RCC_CFGR_MCO1SEL_2              (0x4UL << RCC_CFGR_MCO1SEL_Pos)        /*!< 0x04000000 */
5832 #define RCC_CFGR_MCO1SEL_3              (0x8UL << RCC_CFGR_MCO1SEL_Pos)        /*!< 0x08000000 */
5833 
5834 /*!< MCO Prescaler configuration */
5835 #define RCC_CFGR_MCO1PRE_Pos            (28U)
5836 #define RCC_CFGR_MCO1PRE_Msk            (0xFUL << RCC_CFGR_MCO1PRE_Pos)        /*!< 0xF0000000 */
5837 #define RCC_CFGR_MCO1PRE                RCC_CFGR_MCO1PRE_Msk                   /*!< MCO1 prescaler [3:0] */
5838 #define RCC_CFGR_MCO1PRE_0              (0x1UL << RCC_CFGR_MCO1PRE_Pos)        /*!< 0x10000000 */
5839 #define RCC_CFGR_MCO1PRE_1              (0x2UL << RCC_CFGR_MCO1PRE_Pos)        /*!< 0x20000000 */
5840 #define RCC_CFGR_MCO1PRE_2              (0x4UL << RCC_CFGR_MCO1PRE_Pos)        /*!< 0x40000000 */
5841 #define RCC_CFGR_MCO1PRE_3              (0x8UL << RCC_CFGR_MCO1PRE_Pos)        /*!< 0x80000000 */
5842 
5843 /********************  Bit definition for RCC_PLLCFGR register  ***************/
5844 #define RCC_PLLCFGR_PLLSRC_Pos         (0U)
5845 #define RCC_PLLCFGR_PLLSRC_Msk         (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)       /*!< 0x00000003 */
5846 #define RCC_PLLCFGR_PLLSRC             RCC_PLLCFGR_PLLSRC_Msk
5847 #define RCC_PLLCFGR_PLLSRC_0           (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)       /*!< 0x00000001 */
5848 #define RCC_PLLCFGR_PLLSRC_1           (0x2UL << RCC_PLLCFGR_PLLSRC_Pos)       /*!< 0x00000002 */
5849 
5850 #define RCC_PLLCFGR_PLLM_Pos           (4U)
5851 #define RCC_PLLCFGR_PLLM_Msk           (0x7UL << RCC_PLLCFGR_PLLM_Pos)         /*!< 0x00000070 */
5852 #define RCC_PLLCFGR_PLLM               RCC_PLLCFGR_PLLM_Msk
5853 #define RCC_PLLCFGR_PLLM_0             (0x1UL << RCC_PLLCFGR_PLLM_Pos)         /*!< 0x00000010 */
5854 #define RCC_PLLCFGR_PLLM_1             (0x2UL << RCC_PLLCFGR_PLLM_Pos)         /*!< 0x00000020 */
5855 #define RCC_PLLCFGR_PLLM_2             (0x4UL << RCC_PLLCFGR_PLLM_Pos)         /*!< 0x00000040 */
5856 
5857 #define RCC_PLLCFGR_PLLN_Pos           (8U)
5858 #define RCC_PLLCFGR_PLLN_Msk           (0x7FUL << RCC_PLLCFGR_PLLN_Pos)        /*!< 0x00007F00 */
5859 #define RCC_PLLCFGR_PLLN               RCC_PLLCFGR_PLLN_Msk
5860 #define RCC_PLLCFGR_PLLN_0             (0x01UL << RCC_PLLCFGR_PLLN_Pos)        /*!< 0x00000100 */
5861 #define RCC_PLLCFGR_PLLN_1             (0x02UL << RCC_PLLCFGR_PLLN_Pos)        /*!< 0x00000200 */
5862 #define RCC_PLLCFGR_PLLN_2             (0x04UL << RCC_PLLCFGR_PLLN_Pos)        /*!< 0x00000400 */
5863 #define RCC_PLLCFGR_PLLN_3             (0x08UL << RCC_PLLCFGR_PLLN_Pos)        /*!< 0x00000800 */
5864 #define RCC_PLLCFGR_PLLN_4             (0x10UL << RCC_PLLCFGR_PLLN_Pos)        /*!< 0x00001000 */
5865 #define RCC_PLLCFGR_PLLN_5             (0x20UL << RCC_PLLCFGR_PLLN_Pos)        /*!< 0x00002000 */
5866 #define RCC_PLLCFGR_PLLN_6             (0x40UL << RCC_PLLCFGR_PLLN_Pos)        /*!< 0x00004000 */
5867 
5868 #define RCC_PLLCFGR_PLLPEN_Pos         (16U)
5869 #define RCC_PLLCFGR_PLLPEN_Msk         (0x1UL << RCC_PLLCFGR_PLLPEN_Pos)       /*!< 0x00010000 */
5870 #define RCC_PLLCFGR_PLLPEN             RCC_PLLCFGR_PLLPEN_Msk
5871 #define RCC_PLLCFGR_PLLP_Pos           (17U)
5872 #define RCC_PLLCFGR_PLLP_Msk           (0x1FUL << RCC_PLLCFGR_PLLP_Pos)        /*!< 0x003E0000 */
5873 #define RCC_PLLCFGR_PLLP               RCC_PLLCFGR_PLLP_Msk
5874 #define RCC_PLLCFGR_PLLP_0             (0x1UL << RCC_PLLCFGR_PLLP_Pos)         /*!< 0x00020000 */
5875 #define RCC_PLLCFGR_PLLP_1             (0x2UL << RCC_PLLCFGR_PLLP_Pos)         /*!< 0x00040000 */
5876 #define RCC_PLLCFGR_PLLP_2             (0x4UL << RCC_PLLCFGR_PLLP_Pos)         /*!< 0x00080000 */
5877 #define RCC_PLLCFGR_PLLP_3             (0x8UL << RCC_PLLCFGR_PLLP_Pos)         /*!< 0x00100000 */
5878 #define RCC_PLLCFGR_PLLP_4             (0x10UL << RCC_PLLCFGR_PLLP_Pos)        /*!< 0x00200000 */
5879 
5880 #define RCC_PLLCFGR_PLLQEN_Pos         (24U)
5881 #define RCC_PLLCFGR_PLLQEN_Msk         (0x1UL << RCC_PLLCFGR_PLLQEN_Pos)       /*!< 0x01000000 */
5882 #define RCC_PLLCFGR_PLLQEN             RCC_PLLCFGR_PLLQEN_Msk
5883 
5884 #define RCC_PLLCFGR_PLLQ_Pos           (25U)
5885 #define RCC_PLLCFGR_PLLQ_Msk           (0x7UL << RCC_PLLCFGR_PLLQ_Pos)         /*!< 0x0E000000 */
5886 #define RCC_PLLCFGR_PLLQ               RCC_PLLCFGR_PLLQ_Msk
5887 #define RCC_PLLCFGR_PLLQ_0             (0x1UL << RCC_PLLCFGR_PLLQ_Pos)         /*!< 0x02000000 */
5888 #define RCC_PLLCFGR_PLLQ_1             (0x2UL << RCC_PLLCFGR_PLLQ_Pos)         /*!< 0x04000000 */
5889 #define RCC_PLLCFGR_PLLQ_2             (0x4UL << RCC_PLLCFGR_PLLQ_Pos)         /*!< 0x08000000 */
5890 
5891 #define RCC_PLLCFGR_PLLREN_Pos         (28U)
5892 #define RCC_PLLCFGR_PLLREN_Msk         (0x1UL << RCC_PLLCFGR_PLLREN_Pos)       /*!< 0x01000000 */
5893 #define RCC_PLLCFGR_PLLREN             RCC_PLLCFGR_PLLREN_Msk
5894 #define RCC_PLLCFGR_PLLR_Pos           (29U)
5895 #define RCC_PLLCFGR_PLLR_Msk           (0x7UL << RCC_PLLCFGR_PLLR_Pos)         /*!< 0xE0000000 */
5896 #define RCC_PLLCFGR_PLLR               RCC_PLLCFGR_PLLR_Msk
5897 #define RCC_PLLCFGR_PLLR_0             (0x1UL << RCC_PLLCFGR_PLLR_Pos)         /*!< 0x20000000 */
5898 #define RCC_PLLCFGR_PLLR_1             (0x2UL << RCC_PLLCFGR_PLLR_Pos)         /*!< 0x40000000 */
5899 #define RCC_PLLCFGR_PLLR_2             (0x4UL << RCC_PLLCFGR_PLLR_Pos)         /*!< 0x80000000 */
5900 
5901 /********************  Bit definition for RCC_CIER register  ******************/
5902 #define RCC_CIER_LSIRDYIE_Pos          (0U)
5903 #define RCC_CIER_LSIRDYIE_Msk          (0x1UL << RCC_CIER_LSIRDYIE_Pos)        /*!< 0x00000001 */
5904 #define RCC_CIER_LSIRDYIE              RCC_CIER_LSIRDYIE_Msk
5905 #define RCC_CIER_LSERDYIE_Pos          (1U)
5906 #define RCC_CIER_LSERDYIE_Msk          (0x1UL << RCC_CIER_LSERDYIE_Pos)        /*!< 0x00000002 */
5907 #define RCC_CIER_LSERDYIE              RCC_CIER_LSERDYIE_Msk
5908 #define RCC_CIER_MSIRDYIE_Pos          (2U)
5909 #define RCC_CIER_MSIRDYIE_Msk          (0x1UL << RCC_CIER_MSIRDYIE_Pos)        /*!< 0x00000004 */
5910 #define RCC_CIER_MSIRDYIE              RCC_CIER_MSIRDYIE_Msk
5911 #define RCC_CIER_HSIRDYIE_Pos          (3U)
5912 #define RCC_CIER_HSIRDYIE_Msk          (0x1UL << RCC_CIER_HSIRDYIE_Pos)        /*!< 0x00000008 */
5913 #define RCC_CIER_HSIRDYIE              RCC_CIER_HSIRDYIE_Msk
5914 #define RCC_CIER_HSERDYIE_Pos          (4U)
5915 #define RCC_CIER_HSERDYIE_Msk          (0x1UL << RCC_CIER_HSERDYIE_Pos)        /*!< 0x00000010 */
5916 #define RCC_CIER_HSERDYIE              RCC_CIER_HSERDYIE_Msk
5917 #define RCC_CIER_PLLRDYIE_Pos          (5U)
5918 #define RCC_CIER_PLLRDYIE_Msk          (0x1UL << RCC_CIER_PLLRDYIE_Pos)        /*!< 0x00000020 */
5919 #define RCC_CIER_PLLRDYIE              RCC_CIER_PLLRDYIE_Msk
5920 
5921 #define RCC_CIER_LSECSSIE_Pos          (9U)
5922 #define RCC_CIER_LSECSSIE_Msk          (0x1UL << RCC_CIER_LSECSSIE_Pos)        /*!< 0x00000200 */
5923 #define RCC_CIER_LSECSSIE              RCC_CIER_LSECSSIE_Msk
5924 #define RCC_CIER_HSI48RDYIE_Pos        (10U)
5925 #define RCC_CIER_HSI48RDYIE_Msk        (0x1UL << RCC_CIER_HSI48RDYIE_Pos)      /*!< 0x00000400 */
5926 #define RCC_CIER_HSI48RDYIE            RCC_CIER_HSI48RDYIE_Msk
5927 /********************  Bit definition for RCC_CIFR register  ******************/
5928 #define RCC_CIFR_LSIRDYF_Pos           (0U)
5929 #define RCC_CIFR_LSIRDYF_Msk           (0x1UL << RCC_CIFR_LSIRDYF_Pos)         /*!< 0x00000001 */
5930 #define RCC_CIFR_LSIRDYF               RCC_CIFR_LSIRDYF_Msk
5931 #define RCC_CIFR_LSERDYF_Pos           (1U)
5932 #define RCC_CIFR_LSERDYF_Msk           (0x1UL << RCC_CIFR_LSERDYF_Pos)         /*!< 0x00000002 */
5933 #define RCC_CIFR_LSERDYF               RCC_CIFR_LSERDYF_Msk
5934 #define RCC_CIFR_MSIRDYF_Pos           (2U)
5935 #define RCC_CIFR_MSIRDYF_Msk           (0x1UL << RCC_CIFR_MSIRDYF_Pos)         /*!< 0x00000004 */
5936 #define RCC_CIFR_MSIRDYF               RCC_CIFR_MSIRDYF_Msk
5937 #define RCC_CIFR_HSIRDYF_Pos           (3U)
5938 #define RCC_CIFR_HSIRDYF_Msk           (0x1UL << RCC_CIFR_HSIRDYF_Pos)         /*!< 0x00000008 */
5939 #define RCC_CIFR_HSIRDYF               RCC_CIFR_HSIRDYF_Msk
5940 #define RCC_CIFR_HSERDYF_Pos           (4U)
5941 #define RCC_CIFR_HSERDYF_Msk           (0x1UL << RCC_CIFR_HSERDYF_Pos)         /*!< 0x00000010 */
5942 #define RCC_CIFR_HSERDYF               RCC_CIFR_HSERDYF_Msk
5943 #define RCC_CIFR_PLLRDYF_Pos           (5U)
5944 #define RCC_CIFR_PLLRDYF_Msk           (0x1UL << RCC_CIFR_PLLRDYF_Pos)         /*!< 0x00000020 */
5945 #define RCC_CIFR_PLLRDYF               RCC_CIFR_PLLRDYF_Msk
5946 
5947 #define RCC_CIFR_CSSF_Pos              (8U)
5948 #define RCC_CIFR_CSSF_Msk              (0x1UL << RCC_CIFR_CSSF_Pos)            /*!< 0x00000100 */
5949 #define RCC_CIFR_CSSF                  RCC_CIFR_CSSF_Msk
5950 #define RCC_CIFR_LSECSSF_Pos           (9U)
5951 #define RCC_CIFR_LSECSSF_Msk           (0x1UL << RCC_CIFR_LSECSSF_Pos)         /*!< 0x00000200 */
5952 #define RCC_CIFR_LSECSSF               RCC_CIFR_LSECSSF_Msk
5953 #define RCC_CIFR_HSI48RDYF_Pos         (10U)
5954 #define RCC_CIFR_HSI48RDYF_Msk         (0x1UL << RCC_CIFR_HSI48RDYF_Pos)       /*!< 0x00000400 */
5955 #define RCC_CIFR_HSI48RDYF             RCC_CIFR_HSI48RDYF_Msk
5956 /********************  Bit definition for RCC_CICR register  ******************/
5957 #define RCC_CICR_LSIRDYC_Pos           (0U)
5958 #define RCC_CICR_LSIRDYC_Msk           (0x1UL << RCC_CICR_LSIRDYC_Pos)         /*!< 0x00000001 */
5959 #define RCC_CICR_LSIRDYC               RCC_CICR_LSIRDYC_Msk
5960 #define RCC_CICR_LSERDYC_Pos           (1U)
5961 #define RCC_CICR_LSERDYC_Msk           (0x1UL << RCC_CICR_LSERDYC_Pos)         /*!< 0x00000002 */
5962 #define RCC_CICR_LSERDYC               RCC_CICR_LSERDYC_Msk
5963 #define RCC_CICR_MSIRDYC_Pos           (2U)
5964 #define RCC_CICR_MSIRDYC_Msk           (0x1UL << RCC_CICR_MSIRDYC_Pos)         /*!< 0x00000004 */
5965 #define RCC_CICR_MSIRDYC               RCC_CICR_MSIRDYC_Msk
5966 #define RCC_CICR_HSIRDYC_Pos           (3U)
5967 #define RCC_CICR_HSIRDYC_Msk           (0x1UL << RCC_CICR_HSIRDYC_Pos)         /*!< 0x00000008 */
5968 #define RCC_CICR_HSIRDYC               RCC_CICR_HSIRDYC_Msk
5969 #define RCC_CICR_HSERDYC_Pos           (4U)
5970 #define RCC_CICR_HSERDYC_Msk           (0x1UL << RCC_CICR_HSERDYC_Pos)         /*!< 0x00000010 */
5971 #define RCC_CICR_HSERDYC               RCC_CICR_HSERDYC_Msk
5972 #define RCC_CICR_PLLRDYC_Pos           (5U)
5973 #define RCC_CICR_PLLRDYC_Msk           (0x1UL << RCC_CICR_PLLRDYC_Pos)         /*!< 0x00000020 */
5974 #define RCC_CICR_PLLRDYC               RCC_CICR_PLLRDYC_Msk
5975 
5976 #define RCC_CICR_CSSC_Pos              (8U)
5977 #define RCC_CICR_CSSC_Msk              (0x1UL << RCC_CICR_CSSC_Pos)            /*!< 0x00000100 */
5978 #define RCC_CICR_CSSC                  RCC_CICR_CSSC_Msk
5979 #define RCC_CICR_LSECSSC_Pos           (9U)
5980 #define RCC_CICR_LSECSSC_Msk           (0x1UL << RCC_CICR_LSECSSC_Pos)         /*!< 0x00000200 */
5981 #define RCC_CICR_LSECSSC               RCC_CICR_LSECSSC_Msk
5982 #define RCC_CICR_HSI48RDYC_Pos         (10U)
5983 #define RCC_CICR_HSI48RDYC_Msk         (0x1UL << RCC_CICR_HSI48RDYC_Pos)       /*!< 0x00000400 */
5984 #define RCC_CICR_HSI48RDYC             RCC_CICR_HSI48RDYC_Msk
5985 /********************  Bit definition for RCC_AHB1RSTR register  ***************/
5986 #define RCC_AHBRSTR_DMA1RST_Pos       (0U)
5987 #define RCC_AHBRSTR_DMA1RST_Msk       (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)       /*!< 0x00000001 */
5988 #define RCC_AHBRSTR_DMA1RST           RCC_AHBRSTR_DMA1RST_Msk
5989 #define RCC_AHBRSTR_DMA2RST_Pos       (1U)
5990 #define RCC_AHBRSTR_DMA2RST_Msk       (0x1UL << RCC_AHBRSTR_DMA2RST_Pos)       /*!< 0x00000002 */
5991 #define RCC_AHBRSTR_DMA2RST           RCC_AHBRSTR_DMA2RST_Msk
5992 #define RCC_AHBRSTR_FLASHRST_Pos      (8U)
5993 #define RCC_AHBRSTR_FLASHRST_Msk      (0x1UL << RCC_AHBRSTR_FLASHRST_Pos)      /*!< 0x00000100 */
5994 #define RCC_AHBRSTR_FLASHRST          RCC_AHBRSTR_FLASHRST_Msk
5995 #define RCC_AHBRSTR_CRCRST_Pos        (12U)
5996 #define RCC_AHBRSTR_CRCRST_Msk        (0x1UL << RCC_AHBRSTR_CRCRST_Pos)        /*!< 0x00001000 */
5997 #define RCC_AHBRSTR_CRCRST            RCC_AHBRSTR_CRCRST_Msk
5998 #define RCC_AHBRSTR_AESRST_Pos        (16U)
5999 #define RCC_AHBRSTR_AESRST_Msk        (0x1UL << RCC_AHBRSTR_AESRST_Pos)        /*!< 0x00010000 */
6000 #define RCC_AHBRSTR_AESRST            RCC_AHBRSTR_AESRST_Msk
6001 #define RCC_AHBRSTR_RNGRST_Pos        (18U)
6002 #define RCC_AHBRSTR_RNGRST_Msk        (0x1UL << RCC_AHBRSTR_RNGRST_Pos)        /*!< 0x00040000 */
6003 #define RCC_AHBRSTR_RNGRST            RCC_AHBRSTR_RNGRST_Msk
6004 #define RCC_AHBRSTR_TSCRST_Pos        (24U)
6005 #define RCC_AHBRSTR_TSCRST_Msk        (0x1UL << RCC_AHBRSTR_TSCRST_Pos)        /*!< 0x01000000 */
6006 #define RCC_AHBRSTR_TSCRST            RCC_AHBRSTR_TSCRST_Msk
6007 
6008 /********************  Bit definition for RCC_IOPRSTR register  **************/
6009 #define RCC_IOPRSTR_GPIOARST_Pos       (0U)
6010 #define RCC_IOPRSTR_GPIOARST_Msk       (0x1UL << RCC_IOPRSTR_GPIOARST_Pos)     /*!< 0x00000001 */
6011 #define RCC_IOPRSTR_GPIOARST           RCC_IOPRSTR_GPIOARST_Msk
6012 #define RCC_IOPRSTR_GPIOBRST_Pos       (1U)
6013 #define RCC_IOPRSTR_GPIOBRST_Msk       (0x1UL << RCC_IOPRSTR_GPIOBRST_Pos)     /*!< 0x00000002 */
6014 #define RCC_IOPRSTR_GPIOBRST           RCC_IOPRSTR_GPIOBRST_Msk
6015 #define RCC_IOPRSTR_GPIOCRST_Pos       (2U)
6016 #define RCC_IOPRSTR_GPIOCRST_Msk       (0x1UL << RCC_IOPRSTR_GPIOCRST_Pos)     /*!< 0x00000004 */
6017 #define RCC_IOPRSTR_GPIOCRST           RCC_IOPRSTR_GPIOCRST_Msk
6018 #define RCC_IOPRSTR_GPIODRST_Pos       (3U)
6019 #define RCC_IOPRSTR_GPIODRST_Msk       (0x1UL << RCC_IOPRSTR_GPIODRST_Pos)     /*!< 0x00000008 */
6020 #define RCC_IOPRSTR_GPIODRST           RCC_IOPRSTR_GPIODRST_Msk
6021 #define RCC_IOPRSTR_GPIOERST_Pos       (4U)
6022 #define RCC_IOPRSTR_GPIOERST_Msk       (0x1UL << RCC_IOPRSTR_GPIOERST_Pos)     /*!< 0x00000010 */
6023 #define RCC_IOPRSTR_GPIOERST           RCC_IOPRSTR_GPIOERST_Msk
6024 #define RCC_IOPRSTR_GPIOFRST_Pos       (5U)
6025 #define RCC_IOPRSTR_GPIOFRST_Msk       (0x1UL << RCC_IOPRSTR_GPIOFRST_Pos)     /*!< 0x00000020 */
6026 #define RCC_IOPRSTR_GPIOFRST           RCC_IOPRSTR_GPIOFRST_Msk
6027 
6028 /********************  Bit definition for RCC_APBRSTR1 register  **************/
6029 #define RCC_APBRSTR1_TIM2RST_Pos       (0U)
6030 #define RCC_APBRSTR1_TIM2RST_Msk       (0x1UL << RCC_APBRSTR1_TIM2RST_Pos)     /*!< 0x00000001 */
6031 #define RCC_APBRSTR1_TIM2RST           RCC_APBRSTR1_TIM2RST_Msk
6032 #define RCC_APBRSTR1_TIM3RST_Pos       (1U)
6033 #define RCC_APBRSTR1_TIM3RST_Msk       (0x1UL << RCC_APBRSTR1_TIM3RST_Pos)     /*!< 0x00000002 */
6034 #define RCC_APBRSTR1_TIM3RST           RCC_APBRSTR1_TIM3RST_Msk
6035 #define RCC_APBRSTR1_TIM6RST_Pos       (4U)
6036 #define RCC_APBRSTR1_TIM6RST_Msk       (0x1UL << RCC_APBRSTR1_TIM6RST_Pos)     /*!< 0x00000010 */
6037 #define RCC_APBRSTR1_TIM6RST           RCC_APBRSTR1_TIM6RST_Msk
6038 #define RCC_APBRSTR1_TIM7RST_Pos       (5U)
6039 #define RCC_APBRSTR1_TIM7RST_Msk       (0x1UL << RCC_APBRSTR1_TIM7RST_Pos)     /*!< 0x00000020 */
6040 #define RCC_APBRSTR1_TIM7RST           RCC_APBRSTR1_TIM7RST_Msk
6041 #define RCC_APBRSTR1_LPUART2RST_Pos    (7U)
6042 #define RCC_APBRSTR1_LPUART2RST_Msk    (0x1UL << RCC_APBRSTR1_LPUART2RST_Pos)  /*!< 0x00000080 */
6043 #define RCC_APBRSTR1_LPUART2RST        RCC_APBRSTR1_LPUART2RST_Msk
6044 #define RCC_APBRSTR1_LCDRST_Pos        (9U)
6045 #define RCC_APBRSTR1_LCDRST_Msk        (0x1UL << RCC_APBRSTR1_LCDRST_Pos)      /*!< 0x00000200 */
6046 #define RCC_APBRSTR1_LCDRST            RCC_APBRSTR1_LCDRST_Msk
6047 #define RCC_APBRSTR1_LPUART3RST_Pos    (12U)
6048 #define RCC_APBRSTR1_LPUART3RST_Msk    (0x1UL << RCC_APBRSTR1_LPUART3RST_Pos)  /*!< 0x00000100 */
6049 #define RCC_APBRSTR1_LPUART3RST        RCC_APBRSTR1_LPUART3RST_Msk
6050 #define RCC_APBRSTR1_USBRST_Pos        (13U)
6051 #define RCC_APBRSTR1_USBRST_Msk        (0x1UL << RCC_APBRSTR1_USBRST_Pos)      /*!< 0x00000200 */
6052 #define RCC_APBRSTR1_USBRST            RCC_APBRSTR1_USBRST_Msk
6053 #define RCC_APBRSTR1_SPI2RST_Pos       (14U)
6054 #define RCC_APBRSTR1_SPI2RST_Msk       (0x1UL << RCC_APBRSTR1_SPI2RST_Pos)     /*!< 0x00004000 */
6055 #define RCC_APBRSTR1_SPI2RST           RCC_APBRSTR1_SPI2RST_Msk
6056 #define RCC_APBRSTR1_SPI3RST_Pos       (15U)
6057 #define RCC_APBRSTR1_SPI3RST_Msk       (0x1UL << RCC_APBRSTR1_SPI3RST_Pos)     /*!< 0x00008000 */
6058 #define RCC_APBRSTR1_SPI3RST           RCC_APBRSTR1_SPI3RST_Msk
6059 #define RCC_APBRSTR1_CRSRST_Pos        (16U)
6060 #define RCC_APBRSTR1_CRSRST_Msk        (0x1UL << RCC_APBRSTR1_CRSRST_Pos)      /*!< 0x00010000 */
6061 #define RCC_APBRSTR1_CRSRST            RCC_APBRSTR1_CRSRST_Msk
6062 #define RCC_APBRSTR1_USART2RST_Pos     (17U)
6063 #define RCC_APBRSTR1_USART2RST_Msk     (0x1UL << RCC_APBRSTR1_USART2RST_Pos)   /*!< 0x00020000 */
6064 #define RCC_APBRSTR1_USART2RST         RCC_APBRSTR1_USART2RST_Msk
6065 #define RCC_APBRSTR1_USART3RST_Pos     (18U)
6066 #define RCC_APBRSTR1_USART3RST_Msk     (0x1UL << RCC_APBRSTR1_USART3RST_Pos)   /*!< 0x00040000 */
6067 #define RCC_APBRSTR1_USART3RST         RCC_APBRSTR1_USART3RST_Msk
6068 #define RCC_APBRSTR1_USART4RST_Pos     (19U)
6069 #define RCC_APBRSTR1_USART4RST_Msk     (0x1UL << RCC_APBRSTR1_USART4RST_Pos)   /*!< 0x00080000 */
6070 #define RCC_APBRSTR1_USART4RST         RCC_APBRSTR1_USART4RST_Msk
6071 #define RCC_APBRSTR1_LPUART1RST_Pos    (20U)
6072 #define RCC_APBRSTR1_LPUART1RST_Msk    (0x1UL << RCC_APBRSTR1_LPUART1RST_Pos)  /*!< 0x00010000 */
6073 #define RCC_APBRSTR1_LPUART1RST        RCC_APBRSTR1_LPUART1RST_Msk
6074 #define RCC_APBRSTR1_I2C1RST_Pos       (21U)
6075 #define RCC_APBRSTR1_I2C1RST_Msk       (0x1UL << RCC_APBRSTR1_I2C1RST_Pos)     /*!< 0x00200000 */
6076 #define RCC_APBRSTR1_I2C1RST           RCC_APBRSTR1_I2C1RST_Msk
6077 #define RCC_APBRSTR1_I2C2RST_Pos       (22U)
6078 #define RCC_APBRSTR1_I2C2RST_Msk       (0x1UL << RCC_APBRSTR1_I2C2RST_Pos)     /*!< 0x00400000 */
6079 #define RCC_APBRSTR1_I2C2RST           RCC_APBRSTR1_I2C2RST_Msk
6080 #define RCC_APBRSTR1_I2C3RST_Pos       (23U)
6081 #define RCC_APBRSTR1_I2C3RST_Msk       (0x1UL << RCC_APBRSTR1_I2C3RST_Pos)     /*!< 0x00800000 */
6082 #define RCC_APBRSTR1_I2C3RST           RCC_APBRSTR1_I2C3RST_Msk
6083 #define RCC_APBRSTR1_OPAMPRST_Pos      (24U)
6084 #define RCC_APBRSTR1_OPAMPRST_Msk      (0x1UL << RCC_APBRSTR1_OPAMPRST_Pos)    /*!< 0x01000000 */
6085 #define RCC_APBRSTR1_OPAMPRST          RCC_APBRSTR1_OPAMPRST_Msk
6086 #define RCC_APBRSTR1_I2C4RST_Pos       (25U)
6087 #define RCC_APBRSTR1_I2C4RST_Msk       (0x1UL << RCC_APBRSTR1_I2C4RST_Pos)     /*!< 0x02000000 */
6088 #define RCC_APBRSTR1_I2C4RST           RCC_APBRSTR1_I2C4RST_Msk
6089 #define RCC_APBRSTR1_LPTIM3RST_Pos     (26U)
6090 #define RCC_APBRSTR1_LPTIM3RST_Msk     (0x1UL << RCC_APBRSTR1_LPTIM3RST_Pos)   /*!< 0x04000000 */
6091 #define RCC_APBRSTR1_LPTIM3RST         RCC_APBRSTR1_LPTIM3RST_Msk
6092 #define RCC_APBRSTR1_PWRRST_Pos        (28U)
6093 #define RCC_APBRSTR1_PWRRST_Msk        (0x1UL << RCC_APBRSTR1_PWRRST_Pos)      /*!< 0x10000000 */
6094 #define RCC_APBRSTR1_PWRRST            RCC_APBRSTR1_PWRRST_Msk
6095 #define RCC_APBRSTR1_DAC1RST_Pos       (29U)
6096 #define RCC_APBRSTR1_DAC1RST_Msk       (0x1UL << RCC_APBRSTR1_DAC1RST_Pos)     /*!< 0x20000000 */
6097 #define RCC_APBRSTR1_DAC1RST           RCC_APBRSTR1_DAC1RST_Msk
6098 #define RCC_APBRSTR1_LPTIM2RST_Pos     (30U)
6099 #define RCC_APBRSTR1_LPTIM2RST_Msk     (0x1UL << RCC_APBRSTR1_LPTIM2RST_Pos)   /*!< 0x40000000 */
6100 #define RCC_APBRSTR1_LPTIM2RST         RCC_APBRSTR1_LPTIM2RST_Msk
6101 #define RCC_APBRSTR1_LPTIM1RST_Pos     (31U)
6102 #define RCC_APBRSTR1_LPTIM1RST_Msk     (0x1UL << RCC_APBRSTR1_LPTIM1RST_Pos)   /*!< 0x80000000 */
6103 #define RCC_APBRSTR1_LPTIM1RST         RCC_APBRSTR1_LPTIM1RST_Msk
6104 
6105 /********************  Bit definition for RCC_APB2RSTR register  **************/
6106 #define RCC_APBRSTR2_SYSCFGRST_Pos     (0U)
6107 #define RCC_APBRSTR2_SYSCFGRST_Msk     (0x1UL << RCC_APBRSTR2_SYSCFGRST_Pos)   /*!< 0x00000001 */
6108 #define RCC_APBRSTR2_SYSCFGRST         RCC_APBRSTR2_SYSCFGRST_Msk
6109 #define RCC_APBRSTR2_TIM1RST_Pos       (11U)
6110 #define RCC_APBRSTR2_TIM1RST_Msk       (0x1UL << RCC_APBRSTR2_TIM1RST_Pos)     /*!< 0x00000800 */
6111 #define RCC_APBRSTR2_TIM1RST           RCC_APBRSTR2_TIM1RST_Msk
6112 #define RCC_APBRSTR2_SPI1RST_Pos       (12U)
6113 #define RCC_APBRSTR2_SPI1RST_Msk       (0x1UL << RCC_APBRSTR2_SPI1RST_Pos)     /*!< 0x00001000 */
6114 #define RCC_APBRSTR2_SPI1RST           RCC_APBRSTR2_SPI1RST_Msk
6115 #define RCC_APBRSTR2_USART1RST_Pos     (14U)
6116 #define RCC_APBRSTR2_USART1RST_Msk     (0x1UL << RCC_APBRSTR2_USART1RST_Pos)   /*!< 0x00004000 */
6117 #define RCC_APBRSTR2_USART1RST         RCC_APBRSTR2_USART1RST_Msk
6118 #define RCC_APBRSTR2_TIM15RST_Pos      (16U)
6119 #define RCC_APBRSTR2_TIM15RST_Msk      (0x1UL << RCC_APBRSTR2_TIM15RST_Pos)    /*!< 0x00010000 */
6120 #define RCC_APBRSTR2_TIM15RST          RCC_APBRSTR2_TIM15RST_Msk
6121 #define RCC_APBRSTR2_TIM16RST_Pos      (17U)
6122 #define RCC_APBRSTR2_TIM16RST_Msk      (0x1UL << RCC_APBRSTR2_TIM16RST_Pos)    /*!< 0x00020000 */
6123 #define RCC_APBRSTR2_TIM16RST          RCC_APBRSTR2_TIM16RST_Msk
6124 #define RCC_APBRSTR2_ADCRST_Pos        (20U)
6125 #define RCC_APBRSTR2_ADCRST_Msk        (0x1UL << RCC_APBRSTR2_ADCRST_Pos)      /*!< 0x00100000 */
6126 #define RCC_APBRSTR2_ADCRST            RCC_APBRSTR2_ADCRST_Msk
6127 
6128 /********************  Bit definition for RCC_AHBENR register  ****************/
6129 #define RCC_AHBENR_DMA1EN_Pos          (0U)
6130 #define RCC_AHBENR_DMA1EN_Msk          (0x1UL << RCC_AHBENR_DMA1EN_Pos)        /*!< 0x00000001 */
6131 #define RCC_AHBENR_DMA1EN              RCC_AHBENR_DMA1EN_Msk
6132 #define RCC_AHBENR_DMA2EN_Pos          (1U)
6133 #define RCC_AHBENR_DMA2EN_Msk          (0x1UL << RCC_AHBENR_DMA2EN_Pos)        /*!< 0x00000002 */
6134 #define RCC_AHBENR_DMA2EN              RCC_AHBENR_DMA2EN_Msk
6135 #define RCC_AHBENR_FLASHEN_Pos         (8U)
6136 #define RCC_AHBENR_FLASHEN_Msk         (0x1UL << RCC_AHBENR_FLASHEN_Pos)       /*!< 0x00000100 */
6137 #define RCC_AHBENR_FLASHEN             RCC_AHBENR_FLASHEN_Msk
6138 #define RCC_AHBENR_CRCEN_Pos           (12U)
6139 #define RCC_AHBENR_CRCEN_Msk           (0x1UL << RCC_AHBENR_CRCEN_Pos)         /*!< 0x00001000 */
6140 #define RCC_AHBENR_CRCEN               RCC_AHBENR_CRCEN_Msk
6141 #define RCC_AHBENR_AESEN_Pos           (16U)
6142 #define RCC_AHBENR_AESEN_Msk           (0x1UL << RCC_AHBENR_AESEN_Pos)         /*!< 0x00010000 */
6143 #define RCC_AHBENR_AESEN               RCC_AHBENR_AESEN_Msk
6144 #define RCC_AHBENR_RNGEN_Pos           (18U)
6145 #define RCC_AHBENR_RNGEN_Msk           (0x1UL << RCC_AHBENR_RNGEN_Pos)         /*!< 0x00040000 */
6146 #define RCC_AHBENR_RNGEN               RCC_AHBENR_RNGEN_Msk
6147 #define RCC_AHBENR_TSCEN_Pos           (24U)
6148 #define RCC_AHBENR_TSCEN_Msk           (0x1UL << RCC_AHBENR_TSCEN_Pos)         /*!< 0x01000000 */
6149 #define RCC_AHBENR_TSCEN               RCC_AHBENR_TSCEN_Msk
6150 
6151 /********************  Bit definition for RCC_IOPENR register  ****************/
6152 #define RCC_IOPENR_GPIOAEN_Pos         (0U)
6153 #define RCC_IOPENR_GPIOAEN_Msk         (0x1UL << RCC_IOPENR_GPIOAEN_Pos)       /*!< 0x00000001 */
6154 #define RCC_IOPENR_GPIOAEN             RCC_IOPENR_GPIOAEN_Msk
6155 #define RCC_IOPENR_GPIOBEN_Pos         (1U)
6156 #define RCC_IOPENR_GPIOBEN_Msk         (0x1UL << RCC_IOPENR_GPIOBEN_Pos)       /*!< 0x00000002 */
6157 #define RCC_IOPENR_GPIOBEN             RCC_IOPENR_GPIOBEN_Msk
6158 #define RCC_IOPENR_GPIOCEN_Pos         (2U)
6159 #define RCC_IOPENR_GPIOCEN_Msk         (0x1UL << RCC_IOPENR_GPIOCEN_Pos)       /*!< 0x00000004 */
6160 #define RCC_IOPENR_GPIOCEN             RCC_IOPENR_GPIOCEN_Msk
6161 #define RCC_IOPENR_GPIODEN_Pos         (3U)
6162 #define RCC_IOPENR_GPIODEN_Msk         (0x1UL << RCC_IOPENR_GPIODEN_Pos)       /*!< 0x00000008 */
6163 #define RCC_IOPENR_GPIODEN             RCC_IOPENR_GPIODEN_Msk
6164 #define RCC_IOPENR_GPIOEEN_Pos         (4U)
6165 #define RCC_IOPENR_GPIOEEN_Msk         (0x1UL << RCC_IOPENR_GPIOEEN_Pos)       /*!< 0x00000010 */
6166 #define RCC_IOPENR_GPIOEEN             RCC_IOPENR_GPIOEEN_Msk
6167 #define RCC_IOPENR_GPIOFEN_Pos         (5U)
6168 #define RCC_IOPENR_GPIOFEN_Msk         (0x1UL << RCC_IOPENR_GPIOFEN_Pos)       /*!< 0x00000020 */
6169 #define RCC_IOPENR_GPIOFEN             RCC_IOPENR_GPIOFEN_Msk
6170 
6171 /********************  Bit definition for RCC_DBGCFGR register  ****************/
6172 #define RCC_DBGCFGR_DBGEN_Pos          (0U)
6173 #define RCC_DBGCFGR_DBGEN_Msk          (0x1UL << RCC_DBGCFGR_DBGEN_Pos)        /*!< 0x00000001 */
6174 #define RCC_DBGCFGR_DBGEN              RCC_DBGCFGR_DBGEN_Msk
6175 #define RCC_DBGCFGR_DBGRST_Pos         (1U)
6176 #define RCC_DBGCFGR_DBGRST_Msk         (0x1UL << RCC_DBGCFGR_DBGRST_Pos)       /*!< 0x00000002 */
6177 #define RCC_DBGCFGR_DBGRST             RCC_DBGCFGR_DBGRST_Msk
6178 
6179 /********************  Bit definition for RCC_APB1ENR register  ***************/
6180 #define RCC_APBENR1_TIM2EN_Pos         (0U)
6181 #define RCC_APBENR1_TIM2EN_Msk         (0x1UL << RCC_APBENR1_TIM2EN_Pos)       /*!< 0x00000001 */
6182 #define RCC_APBENR1_TIM2EN             RCC_APBENR1_TIM2EN_Msk
6183 #define RCC_APBENR1_TIM3EN_Pos         (1U)
6184 #define RCC_APBENR1_TIM3EN_Msk         (0x1UL << RCC_APBENR1_TIM3EN_Pos)       /*!< 0x00000002 */
6185 #define RCC_APBENR1_TIM3EN             RCC_APBENR1_TIM3EN_Msk
6186 #define RCC_APBENR1_TIM6EN_Pos         (4U)
6187 #define RCC_APBENR1_TIM6EN_Msk         (0x1UL << RCC_APBENR1_TIM6EN_Pos)       /*!< 0x00000010 */
6188 #define RCC_APBENR1_TIM6EN             RCC_APBENR1_TIM6EN_Msk
6189 #define RCC_APBENR1_TIM7EN_Pos         (5U)
6190 #define RCC_APBENR1_TIM7EN_Msk         (0x1UL << RCC_APBENR1_TIM7EN_Pos)       /*!< 0x00000020 */
6191 #define RCC_APBENR1_TIM7EN             RCC_APBENR1_TIM7EN_Msk
6192 #define RCC_APBENR1_LPUART2EN_Pos      (7U)
6193 #define RCC_APBENR1_LPUART2EN_Msk      (0x1UL << RCC_APBENR1_LPUART2EN_Pos)    /*!< 0x00000080 */
6194 #define RCC_APBENR1_LPUART2EN          RCC_APBENR1_LPUART2EN_Msk
6195 #define RCC_APBENR1_LCDEN_Pos          (9U)
6196 #define RCC_APBENR1_LCDEN_Msk          (0x1UL << RCC_APBENR1_LCDEN_Pos)        /*!< 0x00000200 */
6197 #define RCC_APBENR1_LCDEN              RCC_APBENR1_LCDEN_Msk
6198 #define RCC_APBENR1_RTCAPBEN_Pos       (10U)
6199 #define RCC_APBENR1_RTCAPBEN_Msk       (0x1UL << RCC_APBENR1_RTCAPBEN_Pos)     /*!< 0x00000400 */
6200 #define RCC_APBENR1_RTCAPBEN           RCC_APBENR1_RTCAPBEN_Msk
6201 #define RCC_APBENR1_WWDGEN_Pos         (11U)
6202 #define RCC_APBENR1_WWDGEN_Msk         (0x1UL << RCC_APBENR1_WWDGEN_Pos)       /*!< 0x00000800 */
6203 #define RCC_APBENR1_WWDGEN             RCC_APBENR1_WWDGEN_Msk
6204 #define RCC_APBENR1_LPUART3EN_Pos      (12U)
6205 #define RCC_APBENR1_LPUART3EN_Msk      (0x1UL << RCC_APBENR1_LPUART3EN_Pos)    /*!< 0x00001000 */
6206 #define RCC_APBENR1_LPUART3EN          RCC_APBENR1_LPUART3EN_Msk
6207 #define RCC_APBENR1_USBEN_Pos          (13U)
6208 #define RCC_APBENR1_USBEN_Msk          (0x1UL << RCC_APBENR1_USBEN_Pos)        /*!< 0x00002000 */
6209 #define RCC_APBENR1_USBEN              RCC_APBENR1_USBEN_Msk
6210 #define RCC_APBENR1_SPI2EN_Pos         (14U)
6211 #define RCC_APBENR1_SPI2EN_Msk         (0x1UL << RCC_APBENR1_SPI2EN_Pos)       /*!< 0x00004000 */
6212 #define RCC_APBENR1_SPI2EN             RCC_APBENR1_SPI2EN_Msk
6213 #define RCC_APBENR1_SPI3EN_Pos         (15U)
6214 #define RCC_APBENR1_SPI3EN_Msk         (0x1UL << RCC_APBENR1_SPI3EN_Pos)       /*!< 0x00008000 */
6215 #define RCC_APBENR1_SPI3EN             RCC_APBENR1_SPI3EN_Msk
6216 #define RCC_APBENR1_CRSEN_Pos          (16U)
6217 #define RCC_APBENR1_CRSEN_Msk          (0x1UL << RCC_APBENR1_CRSEN_Pos)        /*!< 0x00010000 */
6218 #define RCC_APBENR1_CRSEN              RCC_APBENR1_CRSEN_Msk
6219 #define RCC_APBENR1_USART2EN_Pos       (17U)
6220 #define RCC_APBENR1_USART2EN_Msk       (0x1UL << RCC_APBENR1_USART2EN_Pos)     /*!< 0x00020000 */
6221 #define RCC_APBENR1_USART2EN           RCC_APBENR1_USART2EN_Msk
6222 #define RCC_APBENR1_USART3EN_Pos       (18U)
6223 #define RCC_APBENR1_USART3EN_Msk       (0x1UL << RCC_APBENR1_USART3EN_Pos)     /*!< 0x00040000 */
6224 #define RCC_APBENR1_USART3EN           RCC_APBENR1_USART3EN_Msk
6225 #define RCC_APBENR1_USART4EN_Pos       (19U)
6226 #define RCC_APBENR1_USART4EN_Msk       (0x1UL << RCC_APBENR1_USART4EN_Pos)     /*!< 0x00080000 */
6227 #define RCC_APBENR1_USART4EN           RCC_APBENR1_USART4EN_Msk
6228 #define RCC_APBENR1_LPUART1EN_Pos      (20U)
6229 #define RCC_APBENR1_LPUART1EN_Msk      (0x1UL << RCC_APBENR1_LPUART1EN_Pos)    /*!< 0x00010000 */
6230 #define RCC_APBENR1_LPUART1EN          RCC_APBENR1_LPUART1EN_Msk
6231 #define RCC_APBENR1_I2C1EN_Pos         (21U)
6232 #define RCC_APBENR1_I2C1EN_Msk         (0x1UL << RCC_APBENR1_I2C1EN_Pos)       /*!< 0x00200000 */
6233 #define RCC_APBENR1_I2C1EN             RCC_APBENR1_I2C1EN_Msk
6234 #define RCC_APBENR1_I2C2EN_Pos         (22U)
6235 #define RCC_APBENR1_I2C2EN_Msk         (0x1UL << RCC_APBENR1_I2C2EN_Pos)       /*!< 0x00400000 */
6236 #define RCC_APBENR1_I2C2EN             RCC_APBENR1_I2C2EN_Msk
6237 #define RCC_APBENR1_I2C3EN_Pos         (23U)
6238 #define RCC_APBENR1_I2C3EN_Msk         (0x1UL << RCC_APBENR1_I2C3EN_Pos)       /*!< 0x00800000 */
6239 #define RCC_APBENR1_I2C3EN             RCC_APBENR1_I2C3EN_Msk
6240 #define RCC_APBENR1_OPAMPEN_Pos        (24U)
6241 #define RCC_APBENR1_OPAMPEN_Msk        (0x1UL << RCC_APBENR1_OPAMPEN_Pos)      /*!< 0x01000000 */
6242 #define RCC_APBENR1_OPAMPEN            RCC_APBENR1_OPAMPEN_Msk
6243 #define RCC_APBENR1_I2C4EN_Pos         (25U)
6244 #define RCC_APBENR1_I2C4EN_Msk         (0x1UL << RCC_APBENR1_I2C4EN_Pos)       /*!< 0x02000000 */
6245 #define RCC_APBENR1_I2C4EN             RCC_APBENR1_I2C4EN_Msk
6246 #define RCC_APBENR1_LPTIM3EN_Pos       (26U)
6247 #define RCC_APBENR1_LPTIM3EN_Msk       (0x1UL << RCC_APBENR1_LPTIM3EN_Pos)     /*!< 0x04000000 */
6248 #define RCC_APBENR1_LPTIM3EN           RCC_APBENR1_LPTIM3EN_Msk
6249 #define RCC_APBENR1_PWREN_Pos          (28U)
6250 #define RCC_APBENR1_PWREN_Msk          (0x1UL << RCC_APBENR1_PWREN_Pos)        /*!< 0x10000000 */
6251 #define RCC_APBENR1_PWREN              RCC_APBENR1_PWREN_Msk
6252 #define RCC_APBENR1_DAC1EN_Pos         (29U)
6253 #define RCC_APBENR1_DAC1EN_Msk         (0x1UL << RCC_APBENR1_DAC1EN_Pos)       /*!< 0x20000000 */
6254 #define RCC_APBENR1_DAC1EN             RCC_APBENR1_DAC1EN_Msk
6255 #define RCC_APBENR1_LPTIM2EN_Pos       (30U)
6256 #define RCC_APBENR1_LPTIM2EN_Msk       (0x1UL << RCC_APBENR1_LPTIM2EN_Pos)     /*!< 0x40000000 */
6257 #define RCC_APBENR1_LPTIM2EN           RCC_APBENR1_LPTIM2EN_Msk
6258 #define RCC_APBENR1_LPTIM1EN_Pos       (31U)
6259 #define RCC_APBENR1_LPTIM1EN_Msk       (0x1UL << RCC_APBENR1_LPTIM1EN_Pos)     /*!< 0x80000000 */
6260 #define RCC_APBENR1_LPTIM1EN           RCC_APBENR1_LPTIM1EN_Msk
6261 
6262 /********************  Bit definition for RCC_APB2ENR register  **************/
6263 #define RCC_APBENR2_SYSCFGEN_Pos       (0U)
6264 #define RCC_APBENR2_SYSCFGEN_Msk       (0x1UL << RCC_APBENR2_SYSCFGEN_Pos)     /*!< 0x00000001 */
6265 #define RCC_APBENR2_SYSCFGEN           RCC_APBENR2_SYSCFGEN_Msk
6266 #define RCC_APBENR2_TIM1EN_Pos         (11U)
6267 #define RCC_APBENR2_TIM1EN_Msk         (0x1UL << RCC_APBENR2_TIM1EN_Pos)       /*!< 0x00000800 */
6268 #define RCC_APBENR2_TIM1EN             RCC_APBENR2_TIM1EN_Msk
6269 #define RCC_APBENR2_SPI1EN_Pos         (12U)
6270 #define RCC_APBENR2_SPI1EN_Msk         (0x1UL << RCC_APBENR2_SPI1EN_Pos)       /*!< 0x00001000 */
6271 #define RCC_APBENR2_SPI1EN             RCC_APBENR2_SPI1EN_Msk
6272 #define RCC_APBENR2_USART1EN_Pos       (14U)
6273 #define RCC_APBENR2_USART1EN_Msk       (0x1UL << RCC_APBENR2_USART1EN_Pos)     /*!< 0x00004000 */
6274 #define RCC_APBENR2_USART1EN           RCC_APBENR2_USART1EN_Msk
6275 #define RCC_APBENR2_TIM15EN_Pos        (16U)
6276 #define RCC_APBENR2_TIM15EN_Msk        (0x1UL << RCC_APBENR2_TIM15EN_Pos)      /*!< 0x00008000 */
6277 #define RCC_APBENR2_TIM15EN            RCC_APBENR2_TIM15EN_Msk
6278 #define RCC_APBENR2_TIM16EN_Pos        (17U)
6279 #define RCC_APBENR2_TIM16EN_Msk        (0x1UL << RCC_APBENR2_TIM16EN_Pos)      /*!< 0x00020000 */
6280 #define RCC_APBENR2_TIM16EN            RCC_APBENR2_TIM16EN_Msk
6281 #define RCC_APBENR2_ADCEN_Pos          (20U)
6282 #define RCC_APBENR2_ADCEN_Msk          (0x1UL << RCC_APBENR2_ADCEN_Pos)        /*!< 0x00100000 */
6283 #define RCC_APBENR2_ADCEN              RCC_APBENR2_ADCEN_Msk
6284 
6285 /********************  Bit definition for RCC_AHBSMENR register  *************/
6286 #define RCC_AHBSMENR_DMA1SMEN_Pos      (0U)
6287 #define RCC_AHBSMENR_DMA1SMEN_Msk      (0x1UL << RCC_AHBSMENR_DMA1SMEN_Pos)    /*!< 0x00000001 */
6288 #define RCC_AHBSMENR_DMA1SMEN          RCC_AHBSMENR_DMA1SMEN_Msk
6289 #define RCC_AHBSMENR_DMA2SMEN_Pos      (1U)
6290 #define RCC_AHBSMENR_DMA2SMEN_Msk      (0x1UL << RCC_AHBSMENR_DMA2SMEN_Pos)    /*!< 0x00000002 */
6291 #define RCC_AHBSMENR_DMA2SMEN          RCC_AHBSMENR_DMA2SMEN_Msk
6292 #define RCC_AHBSMENR_FLASHSMEN_Pos     (8U)
6293 #define RCC_AHBSMENR_FLASHSMEN_Msk     (0x1UL << RCC_AHBSMENR_FLASHSMEN_Pos)   /*!< 0x00000100 */
6294 #define RCC_AHBSMENR_FLASHSMEN         RCC_AHBSMENR_FLASHSMEN_Msk
6295 #define RCC_AHBSMENR_SRAM1SMEN_Pos     (9U)
6296 #define RCC_AHBSMENR_SRAM1SMEN_Msk     (0x1UL << RCC_AHBSMENR_SRAM1SMEN_Pos)   /*!< 0x00000200 */
6297 #define RCC_AHBSMENR_SRAM1SMEN         RCC_AHBSMENR_SRAM1SMEN_Msk
6298 #define RCC_AHBSMENR_CRCSMEN_Pos       (12U)
6299 #define RCC_AHBSMENR_CRCSMEN_Msk       (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)     /*!< 0x00001000 */
6300 #define RCC_AHBSMENR_CRCSMEN           RCC_AHBSMENR_CRCSMEN_Msk
6301 #define RCC_AHBSMENR_AESSMEN_Pos       (16U)
6302 #define RCC_AHBSMENR_AESSMEN_Msk       (0x1UL << RCC_AHBSMENR_AESSMEN_Pos)     /*!< 0x00010000 */
6303 #define RCC_AHBSMENR_AESSMEN           RCC_AHBSMENR_AESSMEN_Msk
6304 #define RCC_AHBSMENR_RNGSMEN_Pos       (18U)
6305 #define RCC_AHBSMENR_RNGSMEN_Msk       (0x1UL << RCC_AHBSMENR_RNGSMEN_Pos)     /*!< 0x00040000 */
6306 #define RCC_AHBSMENR_RNGSMEN           RCC_AHBSMENR_RNGSMEN_Msk
6307 #define RCC_AHBSMENR_TSCSMEN_Pos       (24U)
6308 #define RCC_AHBSMENR_TSCSMEN_Msk       (0x1UL << RCC_AHBSMENR_TSCSMEN_Pos)     /*!< 0x01000000 */
6309 #define RCC_AHBSMENR_TSCSMEN           RCC_AHBSMENR_TSCSMEN_Msk
6310 
6311 /********************  Bit definition for RCC_IOPSMENR register  *************/
6312 #define RCC_IOPSMENR_GPIOASMEN_Pos     (0U)
6313 #define RCC_IOPSMENR_GPIOASMEN_Msk     (0x1UL << RCC_IOPSMENR_GPIOASMEN_Pos)   /*!< 0x00000001 */
6314 #define RCC_IOPSMENR_GPIOASMEN         RCC_IOPSMENR_GPIOASMEN_Msk
6315 #define RCC_IOPSMENR_GPIOBSMEN_Pos     (1U)
6316 #define RCC_IOPSMENR_GPIOBSMEN_Msk     (0x1UL << RCC_IOPSMENR_GPIOBSMEN_Pos)   /*!< 0x00000002 */
6317 #define RCC_IOPSMENR_GPIOBSMEN         RCC_IOPSMENR_GPIOBSMEN_Msk
6318 #define RCC_IOPSMENR_GPIOCSMEN_Pos     (2U)
6319 #define RCC_IOPSMENR_GPIOCSMEN_Msk     (0x1UL << RCC_IOPSMENR_GPIOCSMEN_Pos)   /*!< 0x00000004 */
6320 #define RCC_IOPSMENR_GPIOCSMEN         RCC_IOPSMENR_GPIOCSMEN_Msk
6321 #define RCC_IOPSMENR_GPIODSMEN_Pos     (3U)
6322 #define RCC_IOPSMENR_GPIODSMEN_Msk     (0x1UL << RCC_IOPSMENR_GPIODSMEN_Pos)   /*!< 0x00000008 */
6323 #define RCC_IOPSMENR_GPIODSMEN         RCC_IOPSMENR_GPIODSMEN_Msk
6324 #define RCC_IOPSMENR_GPIOESMEN_Pos     (4U)
6325 #define RCC_IOPSMENR_GPIOESMEN_Msk     (0x1UL << RCC_IOPSMENR_GPIOESMEN_Pos)   /*!< 0x00000010 */
6326 #define RCC_IOPSMENR_GPIOESMEN         RCC_IOPSMENR_GPIOESMEN_Msk
6327 #define RCC_IOPSMENR_GPIOFSMEN_Pos     (5U)
6328 #define RCC_IOPSMENR_GPIOFSMEN_Msk     (0x1UL << RCC_IOPSMENR_GPIOFSMEN_Pos)   /*!< 0x00000020 */
6329 #define RCC_IOPSMENR_GPIOFSMEN         RCC_IOPSMENR_GPIOFSMEN_Msk
6330 
6331 /********************  Bit definition for RCC_APB1SMENR register  *************/
6332 #define RCC_APBSMENR1_TIM2SMEN_Pos     (0U)
6333 #define RCC_APBSMENR1_TIM2SMEN_Msk     (0x1UL << RCC_APBSMENR1_TIM2SMEN_Pos)   /*!< 0x00000001 */
6334 #define RCC_APBSMENR1_TIM2SMEN         RCC_APBSMENR1_TIM2SMEN_Msk
6335 #define RCC_APBSMENR1_TIM3SMEN_Pos     (1U)
6336 #define RCC_APBSMENR1_TIM3SMEN_Msk     (0x1UL << RCC_APBSMENR1_TIM3SMEN_Pos)   /*!< 0x00000002 */
6337 #define RCC_APBSMENR1_TIM3SMEN         RCC_APBSMENR1_TIM3SMEN_Msk
6338 #define RCC_APBSMENR1_TIM6SMEN_Pos     (4U)
6339 #define RCC_APBSMENR1_TIM6SMEN_Msk     (0x1UL << RCC_APBSMENR1_TIM6SMEN_Pos)   /*!< 0x00000010 */
6340 #define RCC_APBSMENR1_TIM6SMEN         RCC_APBSMENR1_TIM6SMEN_Msk
6341 #define RCC_APBSMENR1_TIM7SMEN_Pos     (5U)
6342 #define RCC_APBSMENR1_TIM7SMEN_Msk     (0x1UL << RCC_APBSMENR1_TIM7SMEN_Pos)   /*!< 0x00000020 */
6343 #define RCC_APBSMENR1_TIM7SMEN         RCC_APBSMENR1_TIM7SMEN_Msk
6344 #define RCC_APBSMENR1_LPUART2SMEN_Pos  (7U)
6345 #define RCC_APBSMENR1_LPUART2SMEN_Msk  (0x1UL << RCC_APBSMENR1_LPUART2SMEN_Pos)/*!< 0x00000080 */
6346 #define RCC_APBSMENR1_LPUART2SMEN      RCC_APBSMENR1_LPUART2SMEN_Msk
6347 #define RCC_APBSMENR1_LCDSMEN_Pos      (9U)
6348 #define RCC_APBSMENR1_LCDSMEN_Msk      (0x1UL << RCC_APBSMENR1_LCDSMEN_Pos)    /*!< 0x00000200 */
6349 #define RCC_APBSMENR1_LCDSMEN          RCC_APBSMENR1_LCDSMEN_Msk
6350 #define RCC_APBSMENR1_RTCAPBSMEN_Pos   (10U)
6351 #define RCC_APBSMENR1_RTCAPBSMEN_Msk   (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
6352 #define RCC_APBSMENR1_RTCAPBSMEN       RCC_APBSMENR1_RTCAPBSMEN_Msk
6353 #define RCC_APBSMENR1_WWDGSMEN_Pos     (11U)
6354 #define RCC_APBSMENR1_WWDGSMEN_Msk     (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos)   /*!< 0x00000800 */
6355 #define RCC_APBSMENR1_WWDGSMEN         RCC_APBSMENR1_WWDGSMEN_Msk
6356 #define RCC_APBSMENR1_LPUART3SMEN_Pos  (12U)
6357 #define RCC_APBSMENR1_LPUART3SMEN_Msk  (0x1UL << RCC_APBSMENR1_LPUART3SMEN_Pos)/*!< 0x00000100 */
6358 #define RCC_APBSMENR1_LPUART3SMEN      RCC_APBSMENR1_LPUART3SMEN_Msk
6359 #define RCC_APBSMENR1_USBSMEN_Pos      (13U)
6360 #define RCC_APBSMENR1_USBSMEN_Msk      (0x1UL << RCC_APBSMENR1_USBSMEN_Pos)    /*!< 0x00000200 */
6361 #define RCC_APBSMENR1_USBSMEN          RCC_APBSMENR1_USBSMEN_Msk
6362 #define RCC_APBSMENR1_SPI2SMEN_Pos     (14U)
6363 #define RCC_APBSMENR1_SPI2SMEN_Msk     (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos)   /*!< 0x00004000 */
6364 #define RCC_APBSMENR1_SPI2SMEN         RCC_APBSMENR1_SPI2SMEN_Msk
6365 #define RCC_APBSMENR1_SPI3SMEN_Pos     (15U)
6366 #define RCC_APBSMENR1_SPI3SMEN_Msk     (0x1UL << RCC_APBSMENR1_SPI3SMEN_Pos)   /*!< 0x00008000 */
6367 #define RCC_APBSMENR1_SPI3SMEN         RCC_APBSMENR1_SPI3SMEN_Msk
6368 #define RCC_APBSMENR1_CRSSMEN_Pos      (16U)
6369 #define RCC_APBSMENR1_CRSSMEN_Msk      (0x1UL << RCC_APBSMENR1_CRSSMEN_Pos)    /*!< 0x00010000 */
6370 #define RCC_APBSMENR1_CRSSMEN          RCC_APBSMENR1_CRSSMEN_Msk
6371 #define RCC_APBSMENR1_USART2SMEN_Pos   (17U)
6372 #define RCC_APBSMENR1_USART2SMEN_Msk   (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
6373 #define RCC_APBSMENR1_USART2SMEN       RCC_APBSMENR1_USART2SMEN_Msk
6374 #define RCC_APBSMENR1_USART3SMEN_Pos   (18U)
6375 #define RCC_APBSMENR1_USART3SMEN_Msk   (0x1UL << RCC_APBSMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
6376 #define RCC_APBSMENR1_USART3SMEN       RCC_APBSMENR1_USART3SMEN_Msk
6377 #define RCC_APBSMENR1_USART4SMEN_Pos   (19U)
6378 #define RCC_APBSMENR1_USART4SMEN_Msk   (0x1UL << RCC_APBSMENR1_USART4SMEN_Pos) /*!< 0x00080000 */
6379 #define RCC_APBSMENR1_USART4SMEN       RCC_APBSMENR1_USART4SMEN_Msk
6380 #define RCC_APBSMENR1_LPUART1SMEN_Pos  (20U)
6381 #define RCC_APBSMENR1_LPUART1SMEN_Msk  (0x1UL << RCC_APBSMENR1_LPUART1SMEN_Pos)/*!< 0x00100000 */
6382 #define RCC_APBSMENR1_LPUART1SMEN      RCC_APBSMENR1_LPUART1SMEN_Msk
6383 #define RCC_APBSMENR1_I2C1SMEN_Pos     (21U)
6384 #define RCC_APBSMENR1_I2C1SMEN_Msk     (0x1UL << RCC_APBSMENR1_I2C1SMEN_Pos)   /*!< 0x00200000 */
6385 #define RCC_APBSMENR1_I2C1SMEN         RCC_APBSMENR1_I2C1SMEN_Msk
6386 #define RCC_APBSMENR1_I2C2SMEN_Pos     (22U)
6387 #define RCC_APBSMENR1_I2C2SMEN_Msk     (0x1UL << RCC_APBSMENR1_I2C2SMEN_Pos)   /*!< 0x00400000 */
6388 #define RCC_APBSMENR1_I2C2SMEN         RCC_APBSMENR1_I2C2SMEN_Msk
6389 #define RCC_APBSMENR1_I2C3SMEN_Pos     (23U)
6390 #define RCC_APBSMENR1_I2C3SMEN_Msk     (0x1UL << RCC_APBSMENR1_I2C3SMEN_Pos)   /*!< 0x00800000 */
6391 #define RCC_APBSMENR1_I2C3SMEN         RCC_APBSMENR1_I2C3SMEN_Msk
6392 #define RCC_APBSMENR1_OPAMPSMEN_Pos    (24U)
6393 #define RCC_APBSMENR1_OPAMPSMEN_Msk    (0x1UL << RCC_APBSMENR1_OPAMPSMEN_Pos)  /*!< 0x01000000 */
6394 #define RCC_APBSMENR1_OPAMPSMEN        RCC_APBSMENR1_OPAMPSMEN_Msk
6395 #define RCC_APBSMENR1_I2C4SMEN_Pos     (25U)
6396 #define RCC_APBSMENR1_I2C4SMEN_Msk     (0x1UL << RCC_APBSMENR1_I2C4SMEN_Pos)   /*!< 0x02000000 */
6397 #define RCC_APBSMENR1_I2C4SMEN         RCC_APBSMENR1_I2C4SMEN_Msk
6398 #define RCC_APBSMENR1_LPTIM3SMEN_Pos   (26U)
6399 #define RCC_APBSMENR1_LPTIM3SMEN_Msk   (0x1UL << RCC_APBSMENR1_LPTIM3SMEN_Pos) /*!< 0x04000000 */
6400 #define RCC_APBSMENR1_LPTIM3SMEN       RCC_APBSMENR1_LPTIM3SMEN_Msk
6401 #define RCC_APBSMENR1_PWRSMEN_Pos      (28U)
6402 #define RCC_APBSMENR1_PWRSMEN_Msk      (0x1UL << RCC_APBSMENR1_PWRSMEN_Pos)    /*!< 0x10000000 */
6403 #define RCC_APBSMENR1_PWRSMEN          RCC_APBSMENR1_PWRSMEN_Msk
6404 #define RCC_APBSMENR1_DAC1SMEN_Pos     (29U)
6405 #define RCC_APBSMENR1_DAC1SMEN_Msk     (0x1UL << RCC_APBSMENR1_DAC1SMEN_Pos)   /*!< 0x20000000 */
6406 #define RCC_APBSMENR1_DAC1SMEN         RCC_APBSMENR1_DAC1SMEN_Msk
6407 #define RCC_APBSMENR1_LPTIM2SMEN_Pos   (30U)
6408 #define RCC_APBSMENR1_LPTIM2SMEN_Msk   (0x1UL << RCC_APBSMENR1_LPTIM2SMEN_Pos) /*!< 0x40000000 */
6409 #define RCC_APBSMENR1_LPTIM2SMEN       RCC_APBSMENR1_LPTIM2SMEN_Msk
6410 #define RCC_APBSMENR1_LPTIM1SMEN_Pos   (31U)
6411 #define RCC_APBSMENR1_LPTIM1SMEN_Msk   (0x1UL << RCC_APBSMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
6412 #define RCC_APBSMENR1_LPTIM1SMEN       RCC_APBSMENR1_LPTIM1SMEN_Msk
6413 
6414 /********************  Bit definition for RCC_APBSMENR2 register  *************/
6415 #define RCC_APBSMENR2_SYSCFGSMEN_Pos   (0U)
6416 #define RCC_APBSMENR2_SYSCFGSMEN_Msk   (0x1UL << RCC_APBSMENR2_SYSCFGSMEN_Pos) /*!< 0x00000001 */
6417 #define RCC_APBSMENR2_SYSCFGSMEN       RCC_APBSMENR2_SYSCFGSMEN_Msk
6418 #define RCC_APBSMENR2_TIM1SMEN_Pos     (11U)
6419 #define RCC_APBSMENR2_TIM1SMEN_Msk     (0x1UL << RCC_APBSMENR2_TIM1SMEN_Pos)   /*!< 0x00000800 */
6420 #define RCC_APBSMENR2_TIM1SMEN         RCC_APBSMENR2_TIM1SMEN_Msk
6421 #define RCC_APBSMENR2_SPI1SMEN_Pos     (12U)
6422 #define RCC_APBSMENR2_SPI1SMEN_Msk     (0x1UL << RCC_APBSMENR2_SPI1SMEN_Pos)   /*!< 0x00001000 */
6423 #define RCC_APBSMENR2_SPI1SMEN         RCC_APBSMENR2_SPI1SMEN_Msk
6424 #define RCC_APBSMENR2_USART1SMEN_Pos   (14U)
6425 #define RCC_APBSMENR2_USART1SMEN_Msk   (0x1UL << RCC_APBSMENR2_USART1SMEN_Pos) /*!< 0x00004000 */
6426 #define RCC_APBSMENR2_USART1SMEN       RCC_APBSMENR2_USART1SMEN_Msk
6427 #define RCC_APBSMENR2_TIM15SMEN_Pos    (16U)
6428 #define RCC_APBSMENR2_TIM15SMEN_Msk    (0x1UL << RCC_APBSMENR2_TIM15SMEN_Pos)  /*!< 0x00010000 */
6429 #define RCC_APBSMENR2_TIM15SMEN        RCC_APBSMENR2_TIM15SMEN_Msk
6430 #define RCC_APBSMENR2_TIM16SMEN_Pos    (17U)
6431 #define RCC_APBSMENR2_TIM16SMEN_Msk    (0x1UL << RCC_APBSMENR2_TIM16SMEN_Pos)  /*!< 0x00020000 */
6432 #define RCC_APBSMENR2_TIM16SMEN        RCC_APBSMENR2_TIM16SMEN_Msk
6433 #define RCC_APBSMENR2_ADCSMEN_Pos      (20U)
6434 #define RCC_APBSMENR2_ADCSMEN_Msk      (0x1UL << RCC_APBSMENR2_ADCSMEN_Pos)    /*!< 0x00100000 */
6435 #define RCC_APBSMENR2_ADCSMEN          RCC_APBSMENR2_ADCSMEN_Msk
6436 
6437 /********************  Bit definition for RCC_CCIPR register  ******************/
6438 #define RCC_CCIPR_USART1SEL_Pos        (0U)
6439 #define RCC_CCIPR_USART1SEL_Msk        (0x3UL << RCC_CCIPR_USART1SEL_Pos)      /*!< 0x00000003 */
6440 #define RCC_CCIPR_USART1SEL            RCC_CCIPR_USART1SEL_Msk
6441 #define RCC_CCIPR_USART1SEL_0          (0x1UL << RCC_CCIPR_USART1SEL_Pos)      /*!< 0x00000001 */
6442 #define RCC_CCIPR_USART1SEL_1          (0x2UL << RCC_CCIPR_USART1SEL_Pos)      /*!< 0x00000002 */
6443 #define RCC_CCIPR_USART2SEL_Pos        (2U)
6444 #define RCC_CCIPR_USART2SEL_Msk        (0x3UL << RCC_CCIPR_USART2SEL_Pos)      /*!< 0x0000000C */
6445 #define RCC_CCIPR_USART2SEL            RCC_CCIPR_USART2SEL_Msk
6446 #define RCC_CCIPR_USART2SEL_0          (0x1UL << RCC_CCIPR_USART2SEL_Pos)      /*!< 0x00000004 */
6447 #define RCC_CCIPR_USART2SEL_1          (0x2UL << RCC_CCIPR_USART2SEL_Pos)      /*!< 0x00000008 */
6448 #define RCC_CCIPR_LPUART3SEL_Pos       (6U)
6449 #define RCC_CCIPR_LPUART3SEL_Msk       (0x3UL << RCC_CCIPR_LPUART3SEL_Pos)     /*!< 0x000000C0 */
6450 #define RCC_CCIPR_LPUART3SEL           RCC_CCIPR_LPUART3SEL_Msk
6451 #define RCC_CCIPR_LPUART3SEL_0         (0x1UL << RCC_CCIPR_LPUART3SEL_Pos)     /*!< 0x00000040 */
6452 #define RCC_CCIPR_LPUART3SEL_1         (0x2UL << RCC_CCIPR_LPUART3SEL_Pos)     /*!< 0x00000080 */
6453 #define RCC_CCIPR_LPUART2SEL_Pos       (8U)
6454 #define RCC_CCIPR_LPUART2SEL_Msk       (0x3UL << RCC_CCIPR_LPUART2SEL_Pos)     /*!< 0x00000300 */
6455 #define RCC_CCIPR_LPUART2SEL           RCC_CCIPR_LPUART2SEL_Msk
6456 #define RCC_CCIPR_LPUART2SEL_0         (0x1UL << RCC_CCIPR_LPUART2SEL_Pos)     /*!< 0x00000100 */
6457 #define RCC_CCIPR_LPUART2SEL_1         (0x2UL << RCC_CCIPR_LPUART2SEL_Pos)     /*!< 0x00000200 */
6458 #define RCC_CCIPR_LPUART1SEL_Pos       (10U)
6459 #define RCC_CCIPR_LPUART1SEL_Msk       (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)     /*!< 0x00000C00 */
6460 #define RCC_CCIPR_LPUART1SEL           RCC_CCIPR_LPUART1SEL_Msk
6461 #define RCC_CCIPR_LPUART1SEL_0         (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)     /*!< 0x00000400 */
6462 #define RCC_CCIPR_LPUART1SEL_1         (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)     /*!< 0x00000800 */
6463 #define RCC_CCIPR_I2C1SEL_Pos          (12U)
6464 #define RCC_CCIPR_I2C1SEL_Msk          (0x3UL << RCC_CCIPR_I2C1SEL_Pos)        /*!< 0x00003000 */
6465 #define RCC_CCIPR_I2C1SEL              RCC_CCIPR_I2C1SEL_Msk
6466 #define RCC_CCIPR_I2C1SEL_0            (0x1UL << RCC_CCIPR_I2C1SEL_Pos)        /*!< 0x00001000 */
6467 #define RCC_CCIPR_I2C1SEL_1            (0x2UL << RCC_CCIPR_I2C1SEL_Pos)        /*!< 0x00002000 */
6468 #define RCC_CCIPR_I2C3SEL_Pos          (16U)
6469 #define RCC_CCIPR_I2C3SEL_Msk          (0x3UL << RCC_CCIPR_I2C3SEL_Pos)        /*!< 0x00030000 */
6470 #define RCC_CCIPR_I2C3SEL              RCC_CCIPR_I2C3SEL_Msk
6471 #define RCC_CCIPR_I2C3SEL_0            (0x1UL << RCC_CCIPR_I2C3SEL_Pos)        /*!< 0x00010000 */
6472 #define RCC_CCIPR_I2C3SEL_1            (0x2UL << RCC_CCIPR_I2C3SEL_Pos)        /*!< 0x00020000 */
6473 #define RCC_CCIPR_LPTIM1SEL_Pos        (18U)
6474 #define RCC_CCIPR_LPTIM1SEL_Msk        (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)      /*!< 0x000C0000 */
6475 #define RCC_CCIPR_LPTIM1SEL            RCC_CCIPR_LPTIM1SEL_Msk
6476 #define RCC_CCIPR_LPTIM1SEL_0          (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)      /*!< 0x00040000 */
6477 #define RCC_CCIPR_LPTIM1SEL_1          (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)      /*!< 0x00080000 */
6478 #define RCC_CCIPR_LPTIM2SEL_Pos        (20U)
6479 #define RCC_CCIPR_LPTIM2SEL_Msk        (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos)      /*!< 0x00300000 */
6480 #define RCC_CCIPR_LPTIM2SEL            RCC_CCIPR_LPTIM2SEL_Msk
6481 #define RCC_CCIPR_LPTIM2SEL_0          (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos)      /*!< 0x00100000 */
6482 #define RCC_CCIPR_LPTIM2SEL_1          (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos)      /*!< 0x00200000 */
6483 #define RCC_CCIPR_LPTIM3SEL_Pos        (22U)
6484 #define RCC_CCIPR_LPTIM3SEL_Msk        (0x3UL << RCC_CCIPR_LPTIM3SEL_Pos)      /*!< 0x00C0000 */
6485 #define RCC_CCIPR_LPTIM3SEL            RCC_CCIPR_LPTIM3SEL_Msk
6486 #define RCC_CCIPR_LPTIM3SEL_0          (0x1UL << RCC_CCIPR_LPTIM3SEL_Pos)      /*!< 0x00400000 */
6487 #define RCC_CCIPR_LPTIM3SEL_1          (0x2UL << RCC_CCIPR_LPTIM3SEL_Pos)      /*!< 0x00800000 */
6488 #define RCC_CCIPR_TIM1SEL_Pos          (24U)
6489 #define RCC_CCIPR_TIM1SEL_Msk          (0x1UL << RCC_CCIPR_TIM1SEL_Pos)        /*!< 0x01000000 */
6490 #define RCC_CCIPR_TIM1SEL              RCC_CCIPR_TIM1SEL_Msk
6491 #define RCC_CCIPR_TIM15SEL_Pos         (25U)
6492 #define RCC_CCIPR_TIM15SEL_Msk         (0x1UL << RCC_CCIPR_TIM15SEL_Pos)       /*!< 0x02000000 */
6493 #define RCC_CCIPR_TIM15SEL             RCC_CCIPR_TIM15SEL_Msk
6494 #define RCC_CCIPR_CLK48SEL_Pos         (26U)
6495 #define RCC_CCIPR_CLK48SEL_Msk         (0x3UL << RCC_CCIPR_CLK48SEL_Pos)         /*!< 0x0C000000 */
6496 #define RCC_CCIPR_CLK48SEL             RCC_CCIPR_CLK48SEL_Msk
6497 #define RCC_CCIPR_CLK48SEL_0           (0x1UL << RCC_CCIPR_CLK48SEL_Pos)       /*!< 0x04000000 */
6498 #define RCC_CCIPR_CLK48SEL_1           (0x2UL << RCC_CCIPR_CLK48SEL_Pos)       /*!< 0x08000000 */
6499 #define RCC_CCIPR_ADCSEL_Pos           (28U)
6500 #define RCC_CCIPR_ADCSEL_Msk           (0x3UL << RCC_CCIPR_ADCSEL_Pos)         /*!< 0x30000000 */
6501 #define RCC_CCIPR_ADCSEL               RCC_CCIPR_ADCSEL_Msk
6502 #define RCC_CCIPR_ADCSEL_0             (0x1UL << RCC_CCIPR_ADCSEL_Pos)         /*!< 0x10000000 */
6503 #define RCC_CCIPR_ADCSEL_1             (0x2UL << RCC_CCIPR_ADCSEL_Pos)         /*!< 0x20000000 */
6504 
6505 /********************  Bit definition for RCC_BDCR register  ******************/
6506 #define RCC_BDCR_LSEON_Pos             (0U)
6507 #define RCC_BDCR_LSEON_Msk             (0x1UL << RCC_BDCR_LSEON_Pos)           /*!< 0x00000001 */
6508 #define RCC_BDCR_LSEON                 RCC_BDCR_LSEON_Msk
6509 #define RCC_BDCR_LSERDY_Pos            (1U)
6510 #define RCC_BDCR_LSERDY_Msk            (0x1UL << RCC_BDCR_LSERDY_Pos)          /*!< 0x00000002 */
6511 #define RCC_BDCR_LSERDY                RCC_BDCR_LSERDY_Msk
6512 #define RCC_BDCR_LSEBYP_Pos            (2U)
6513 #define RCC_BDCR_LSEBYP_Msk            (0x1UL << RCC_BDCR_LSEBYP_Pos)          /*!< 0x00000004 */
6514 #define RCC_BDCR_LSEBYP                RCC_BDCR_LSEBYP_Msk
6515 #define RCC_BDCR_LSEDRV_Pos            (3U)
6516 #define RCC_BDCR_LSEDRV_Msk            (0x3UL << RCC_BDCR_LSEDRV_Pos)          /*!< 0x00000018 */
6517 #define RCC_BDCR_LSEDRV                RCC_BDCR_LSEDRV_Msk
6518 #define RCC_BDCR_LSEDRV_0              (0x1UL << RCC_BDCR_LSEDRV_Pos)          /*!< 0x00000008 */
6519 #define RCC_BDCR_LSEDRV_1              (0x2UL << RCC_BDCR_LSEDRV_Pos)          /*!< 0x00000010 */
6520 #define RCC_BDCR_LSECSSON_Pos          (5U)
6521 #define RCC_BDCR_LSECSSON_Msk          (0x1UL << RCC_BDCR_LSECSSON_Pos)        /*!< 0x00000020 */
6522 #define RCC_BDCR_LSECSSON              RCC_BDCR_LSECSSON_Msk
6523 #define RCC_BDCR_LSECSSD_Pos           (6U)
6524 #define RCC_BDCR_LSECSSD_Msk           (0x1UL << RCC_BDCR_LSECSSD_Pos)         /*!< 0x00000040 */
6525 #define RCC_BDCR_LSECSSD               RCC_BDCR_LSECSSD_Msk
6526 #define RCC_BDCR_LSESYSEN_Pos          (7U)
6527 #define RCC_BDCR_LSESYSEN_Msk          (0x1UL << RCC_BDCR_LSESYSEN_Pos)        /*!< 0x00000080 */
6528 #define RCC_BDCR_LSESYSEN              RCC_BDCR_LSESYSEN_Msk
6529 #define RCC_BDCR_RTCSEL_Pos            (8U)
6530 #define RCC_BDCR_RTCSEL_Msk            (0x3UL << RCC_BDCR_RTCSEL_Pos)          /*!< 0x00000300 */
6531 #define RCC_BDCR_RTCSEL                RCC_BDCR_RTCSEL_Msk
6532 #define RCC_BDCR_RTCSEL_0              (0x1UL << RCC_BDCR_RTCSEL_Pos)          /*!< 0x00000100 */
6533 #define RCC_BDCR_RTCSEL_1              (0x2UL << RCC_BDCR_RTCSEL_Pos)          /*!< 0x00000200 */
6534 #define RCC_BDCR_LSESYSRDY_Pos         (11U)
6535 #define RCC_BDCR_LSESYSRDY_Msk         (0x1UL << RCC_BDCR_LSESYSRDY_Pos)       /*!< 0x00000800 */
6536 #define RCC_BDCR_LSESYSRDY             RCC_BDCR_LSESYSRDY_Msk
6537 #define RCC_BDCR_RTCEN_Pos             (15U)
6538 #define RCC_BDCR_RTCEN_Msk             (0x1UL << RCC_BDCR_RTCEN_Pos)           /*!< 0x00008000 */
6539 #define RCC_BDCR_RTCEN                 RCC_BDCR_RTCEN_Msk
6540 #define RCC_BDCR_BDRST_Pos             (16U)
6541 #define RCC_BDCR_BDRST_Msk             (0x1UL << RCC_BDCR_BDRST_Pos)           /*!< 0x00010000 */
6542 #define RCC_BDCR_BDRST                 RCC_BDCR_BDRST_Msk
6543 #define RCC_BDCR_LSCOEN_Pos            (24U)
6544 #define RCC_BDCR_LSCOEN_Msk            (0x1UL << RCC_BDCR_LSCOEN_Pos)          /*!< 0x01000000 */
6545 #define RCC_BDCR_LSCOEN                RCC_BDCR_LSCOEN_Msk
6546 #define RCC_BDCR_LSCOSEL_Pos           (25U)
6547 #define RCC_BDCR_LSCOSEL_Msk           (0x1UL << RCC_BDCR_LSCOSEL_Pos)         /*!< 0x02000000 */
6548 #define RCC_BDCR_LSCOSEL               RCC_BDCR_LSCOSEL_Msk
6549 
6550 /********************  Bit definition for RCC_CSR register  *******************/
6551 #define RCC_CSR_LSION_Pos              (0U)
6552 #define RCC_CSR_LSION_Msk              (0x1UL << RCC_CSR_LSION_Pos)            /*!< 0x00000001 */
6553 #define RCC_CSR_LSION                  RCC_CSR_LSION_Msk
6554 #define RCC_CSR_LSIRDY_Pos             (1U)
6555 #define RCC_CSR_LSIRDY_Msk             (0x1UL << RCC_CSR_LSIRDY_Pos)           /*!< 0x00000002 */
6556 #define RCC_CSR_LSIRDY                 RCC_CSR_LSIRDY_Msk
6557 #define RCC_CSR_LSIPREDIV_Pos          (2U)
6558 #define RCC_CSR_LSIPREDIV_Msk          (0x1UL << RCC_CSR_LSIPREDIV_Pos)        /*!< 0x00000004 */
6559 #define RCC_CSR_LSIPREDIV              RCC_CSR_LSIPREDIV_Msk
6560 #define RCC_CSR_MSISTBYRG_Pos          (8U)
6561 #define RCC_CSR_MSISTBYRG_Msk          (0xFUL << RCC_CSR_MSISTBYRG_Pos)        /*!< 0x00000F00 */
6562 #define RCC_CSR_MSISTBYRG              RCC_CSR_MSISTBYRG_Msk
6563 #define RCC_CSR_MSISTBYRG_1            (0x4UL << RCC_CSR_MSISTBYRG_Pos)        /*!< 0x00000400 */
6564 #define RCC_CSR_MSISTBYRG_2            (0x5UL << RCC_CSR_MSISTBYRG_Pos)        /*!< 0x00000500 */
6565 #define RCC_CSR_MSISTBYRG_4            (0x6UL << RCC_CSR_MSISTBYRG_Pos)        /*!< 0x00000600 */
6566 #define RCC_CSR_MSISTBYRG_8            (0x7UL << RCC_CSR_MSISTBYRG_Pos)        /*!< 0x00000700 */
6567 #define RCC_CSR_RMVF_Pos               (23U)
6568 #define RCC_CSR_RMVF_Msk               (0x1UL << RCC_CSR_RMVF_Pos)             /*!< 0x00800000 */
6569 #define RCC_CSR_RMVF                   RCC_CSR_RMVF_Msk
6570 #define RCC_CSR_OBLRSTF_Pos            (25U)
6571 #define RCC_CSR_OBLRSTF_Msk            (0x1UL << RCC_CSR_OBLRSTF_Pos)          /*!< 0x02000000 */
6572 #define RCC_CSR_OBLRSTF                RCC_CSR_OBLRSTF_Msk
6573 #define RCC_CSR_PINRSTF_Pos            (26U)
6574 #define RCC_CSR_PINRSTF_Msk            (0x1UL << RCC_CSR_PINRSTF_Pos)          /*!< 0x04000000 */
6575 #define RCC_CSR_PINRSTF                RCC_CSR_PINRSTF_Msk
6576 #define RCC_CSR_PWRRSTF_Pos            (27U)
6577 #define RCC_CSR_PWRRSTF_Msk            (0x1UL << RCC_CSR_PWRRSTF_Pos)          /*!< 0x08000000 */
6578 #define RCC_CSR_PWRRSTF                RCC_CSR_PWRRSTF_Msk
6579 #define RCC_CSR_SFTRSTF_Pos            (28U)
6580 #define RCC_CSR_SFTRSTF_Msk            (0x1UL << RCC_CSR_SFTRSTF_Pos)          /*!< 0x10000000 */
6581 #define RCC_CSR_SFTRSTF                RCC_CSR_SFTRSTF_Msk
6582 #define RCC_CSR_IWDGRSTF_Pos           (29U)
6583 #define RCC_CSR_IWDGRSTF_Msk           (0x1UL << RCC_CSR_IWDGRSTF_Pos)         /*!< 0x20000000 */
6584 #define RCC_CSR_IWDGRSTF               RCC_CSR_IWDGRSTF_Msk
6585 #define RCC_CSR_WWDGRSTF_Pos           (30U)
6586 #define RCC_CSR_WWDGRSTF_Msk           (0x1UL << RCC_CSR_WWDGRSTF_Pos)         /*!< 0x40000000 */
6587 #define RCC_CSR_WWDGRSTF               RCC_CSR_WWDGRSTF_Msk
6588 #define RCC_CSR_LPWRRSTF_Pos           (31U)
6589 #define RCC_CSR_LPWRRSTF_Msk           (0x1UL << RCC_CSR_LPWRRSTF_Pos)         /*!< 0x80000000 */
6590 #define RCC_CSR_LPWRRSTF               RCC_CSR_LPWRRSTF_Msk
6591 /********************  Bit definition for RCC_CRRCR register  *****************/
6592 #define RCC_CRRCR_HSI48ON_Pos          (0U)
6593 #define RCC_CRRCR_HSI48ON_Msk          (0x1UL << RCC_CRRCR_HSI48ON_Pos)        /*!< 0x00000000 */
6594 #define RCC_CRRCR_HSI48ON              RCC_CRRCR_HSI48ON_Msk                   /*!< System HSI48 clock enable */
6595 #define RCC_CRRCR_HSI48RDY_Pos         (1U)
6596 #define RCC_CRRCR_HSI48RDY_Msk         (0x1UL << RCC_CRRCR_HSI48RDY_Pos)       /*!< 0x00000001 */
6597 #define RCC_CRRCR_HSI48RDY             RCC_CRRCR_HSI48RDY_Msk                  /*!< System HSI48 clock ready */
6598 
6599 /*!< HSI48CAL configuration */
6600 #define RCC_CRRCR_HSI48CAL_Pos         (7U)
6601 #define RCC_CRRCR_HSI48CAL_Msk         (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x0000FF80 */
6602 #define RCC_CRRCR_HSI48CAL             RCC_CRRCR_HSI48CAL_Msk                  /*!< RC48CAL[8:0] bits */
6603 #define RCC_CRRCR_HSI48CAL_0           (0x001UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000080 */
6604 #define RCC_CRRCR_HSI48CAL_1           (0x002UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000100 */
6605 #define RCC_CRRCR_HSI48CAL_2           (0x004UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000200 */
6606 #define RCC_CRRCR_HSI48CAL_3           (0x008UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000400 */
6607 #define RCC_CRRCR_HSI48CAL_4           (0x010UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000800 */
6608 #define RCC_CRRCR_HSI48CAL_5           (0x020UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00001000 */
6609 #define RCC_CRRCR_HSI48CAL_6           (0x040UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00002000 */
6610 #define RCC_CRRCR_HSI48CAL_7           (0x080UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00004000 */
6611 #define RCC_CRRCR_HSI48CAL_8           (0x100UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00008000 */
6612 /******************************************************************************/
6613 /*                                                                            */
6614 /*                                    RNG                                     */
6615 /*                                                                            */
6616 /******************************************************************************/
6617 /********************  Bits definition for RNG_CR register  *******************/
6618 #define RNG_CR_RNGEN_Pos                    (2U)
6619 #define RNG_CR_RNGEN_Msk                    (0x1UL << RNG_CR_RNGEN_Pos)             /*!< 0x00000004 */
6620 #define RNG_CR_RNGEN                        RNG_CR_RNGEN_Msk
6621 #define RNG_CR_IE_Pos                       (3U)
6622 #define RNG_CR_IE_Msk                       (0x1UL << RNG_CR_IE_Pos)                /*!< 0x00000008 */
6623 #define RNG_CR_IE                           RNG_CR_IE_Msk
6624 #define RNG_CR_CED_Pos                      (5U)
6625 #define RNG_CR_CED_Msk                      (0x1UL << RNG_CR_CED_Pos)               /*!< 0x00000020 */
6626 #define RNG_CR_CED                          RNG_CR_CED_Msk
6627 #define RNG_CR_ARDIS_Pos                    (7U)
6628 #define RNG_CR_ARDIS_Msk                    (0x1UL << RNG_CR_ARDIS_Pos)
6629 #define RNG_CR_ARDIS                        RNG_CR_ARDIS_Msk
6630 #define RNG_CR_RNG_CONFIG3_Pos              (8U)
6631 #define RNG_CR_RNG_CONFIG3_Msk              (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
6632 #define RNG_CR_RNG_CONFIG3                  RNG_CR_RNG_CONFIG3_Msk
6633 #define RNG_CR_NISTC_Pos                    (12U)
6634 #define RNG_CR_NISTC_Msk                    (0x1UL << RNG_CR_NISTC_Pos)
6635 #define RNG_CR_NISTC                        RNG_CR_NISTC_Msk
6636 #define RNG_CR_RNG_CONFIG2_Pos              (13U)
6637 #define RNG_CR_RNG_CONFIG2_Msk              (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
6638 #define RNG_CR_RNG_CONFIG2                  RNG_CR_RNG_CONFIG2_Msk
6639 #define RNG_CR_CLKDIV_Pos                   (16U)
6640 #define RNG_CR_CLKDIV_Msk                   (0xFUL << RNG_CR_CLKDIV_Pos)
6641 #define RNG_CR_CLKDIV                       RNG_CR_CLKDIV_Msk
6642 #define RNG_CR_CLKDIV_0                     (0x1UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00010000 */
6643 #define RNG_CR_CLKDIV_1                     (0x2UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00020000 */
6644 #define RNG_CR_CLKDIV_2                     (0x4UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00040000 */
6645 #define RNG_CR_CLKDIV_3                     (0x8UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00080000 */
6646 #define RNG_CR_RNG_CONFIG1_Pos              (20U)
6647 #define RNG_CR_RNG_CONFIG1_Msk              (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
6648 #define RNG_CR_RNG_CONFIG1                  RNG_CR_RNG_CONFIG1_Msk
6649 #define RNG_CR_CONDRST_Pos                  (30U)
6650 #define RNG_CR_CONDRST_Msk                  (0x1UL << RNG_CR_CONDRST_Pos)
6651 #define RNG_CR_CONDRST                      RNG_CR_CONDRST_Msk
6652 #define RNG_CR_CONFIGLOCK_Pos               (31U)
6653 #define RNG_CR_CONFIGLOCK_Msk               (0x1UL << RNG_CR_CONFIGLOCK_Pos)
6654 #define RNG_CR_CONFIGLOCK                   RNG_CR_CONFIGLOCK_Msk
6655 
6656 /********************  Bits definition for RNG_SR register  *******************/
6657 #define RNG_SR_DRDY_Pos     (0U)
6658 #define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */
6659 #define RNG_SR_DRDY         RNG_SR_DRDY_Msk
6660 #define RNG_SR_CECS_Pos     (1U)
6661 #define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */
6662 #define RNG_SR_CECS         RNG_SR_CECS_Msk
6663 #define RNG_SR_SECS_Pos     (2U)
6664 #define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */
6665 #define RNG_SR_SECS         RNG_SR_SECS_Msk
6666 #define RNG_SR_CEIS_Pos     (5U)
6667 #define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */
6668 #define RNG_SR_CEIS         RNG_SR_CEIS_Msk
6669 #define RNG_SR_SEIS_Pos     (6U)
6670 #define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */
6671 #define RNG_SR_SEIS         RNG_SR_SEIS_Msk
6672 
6673 /********************  Bits definition for RNG_HTCR register  *******************/
6674 #define RNG_HTCR_HTCFG_Pos                  (0U)
6675 #define RNG_HTCR_HTCFG_Msk                  (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos)    /*!< 0xFFFFFFFF */
6676 #define RNG_HTCR_HTCFG                      RNG_HTCR_HTCFG_Msk
6677 
6678 /******************************************************************************/
6679 /*                                                                            */
6680 /*                           Real-Time Clock (RTC)                            */
6681 /*                                                                            */
6682 /******************************************************************************/
6683 /********************  Bits definition for RTC_TR register  *******************/
6684 #define RTC_TR_SU_Pos                       (0U)
6685 #define RTC_TR_SU_Msk                       (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */
6686 #define RTC_TR_SU                           RTC_TR_SU_Msk
6687 #define RTC_TR_SU_0                         (0x1UL << RTC_TR_SU_Pos)                /*!< 0x00000001 */
6688 #define RTC_TR_SU_1                         (0x2UL << RTC_TR_SU_Pos)                /*!< 0x00000002 */
6689 #define RTC_TR_SU_2                         (0x4UL << RTC_TR_SU_Pos)                /*!< 0x00000004 */
6690 #define RTC_TR_SU_3                         (0x8UL << RTC_TR_SU_Pos)                /*!< 0x00000008 */
6691 #define RTC_TR_ST_Pos                       (4U)
6692 #define RTC_TR_ST_Msk                       (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */
6693 #define RTC_TR_ST                           RTC_TR_ST_Msk
6694 #define RTC_TR_ST_0                         (0x1UL << RTC_TR_ST_Pos)                /*!< 0x00000010 */
6695 #define RTC_TR_ST_1                         (0x2UL << RTC_TR_ST_Pos)                /*!< 0x00000020 */
6696 #define RTC_TR_ST_2                         (0x4UL << RTC_TR_ST_Pos)                /*!< 0x00000040 */
6697 #define RTC_TR_MNU_Pos                      (8U)
6698 #define RTC_TR_MNU_Msk                      (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */
6699 #define RTC_TR_MNU                          RTC_TR_MNU_Msk
6700 #define RTC_TR_MNU_0                        (0x1UL << RTC_TR_MNU_Pos)               /*!< 0x00000100 */
6701 #define RTC_TR_MNU_1                        (0x2UL << RTC_TR_MNU_Pos)               /*!< 0x00000200 */
6702 #define RTC_TR_MNU_2                        (0x4UL << RTC_TR_MNU_Pos)               /*!< 0x00000400 */
6703 #define RTC_TR_MNU_3                        (0x8UL << RTC_TR_MNU_Pos)               /*!< 0x00000800 */
6704 #define RTC_TR_MNT_Pos                      (12U)
6705 #define RTC_TR_MNT_Msk                      (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */
6706 #define RTC_TR_MNT                          RTC_TR_MNT_Msk
6707 #define RTC_TR_MNT_0                        (0x1UL << RTC_TR_MNT_Pos)               /*!< 0x00001000 */
6708 #define RTC_TR_MNT_1                        (0x2UL << RTC_TR_MNT_Pos)               /*!< 0x00002000 */
6709 #define RTC_TR_MNT_2                        (0x4UL << RTC_TR_MNT_Pos)               /*!< 0x00004000 */
6710 #define RTC_TR_HU_Pos                       (16U)
6711 #define RTC_TR_HU_Msk                       (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */
6712 #define RTC_TR_HU                           RTC_TR_HU_Msk
6713 #define RTC_TR_HU_0                         (0x1UL << RTC_TR_HU_Pos)                /*!< 0x00010000 */
6714 #define RTC_TR_HU_1                         (0x2UL << RTC_TR_HU_Pos)                /*!< 0x00020000 */
6715 #define RTC_TR_HU_2                         (0x4UL << RTC_TR_HU_Pos)                /*!< 0x00040000 */
6716 #define RTC_TR_HU_3                         (0x8UL << RTC_TR_HU_Pos)                /*!< 0x00080000 */
6717 #define RTC_TR_HT_Pos                       (20U)
6718 #define RTC_TR_HT_Msk                       (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */
6719 #define RTC_TR_HT                           RTC_TR_HT_Msk
6720 #define RTC_TR_HT_0                         (0x1UL << RTC_TR_HT_Pos)                /*!< 0x00100000 */
6721 #define RTC_TR_HT_1                         (0x2UL << RTC_TR_HT_Pos)                /*!< 0x00200000 */
6722 #define RTC_TR_PM_Pos                       (22U)
6723 #define RTC_TR_PM_Msk                       (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */
6724 #define RTC_TR_PM                           RTC_TR_PM_Msk
6725 
6726 /********************  Bits definition for RTC_DR register  *******************/
6727 #define RTC_DR_DU_Pos                       (0U)
6728 #define RTC_DR_DU_Msk                       (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */
6729 #define RTC_DR_DU                           RTC_DR_DU_Msk
6730 #define RTC_DR_DU_0                         (0x1UL << RTC_DR_DU_Pos)                /*!< 0x00000001 */
6731 #define RTC_DR_DU_1                         (0x2UL << RTC_DR_DU_Pos)                /*!< 0x00000002 */
6732 #define RTC_DR_DU_2                         (0x4UL << RTC_DR_DU_Pos)                /*!< 0x00000004 */
6733 #define RTC_DR_DU_3                         (0x8UL << RTC_DR_DU_Pos)                /*!< 0x00000008 */
6734 #define RTC_DR_DT_Pos                       (4U)
6735 #define RTC_DR_DT_Msk                       (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */
6736 #define RTC_DR_DT                           RTC_DR_DT_Msk
6737 #define RTC_DR_DT_0                         (0x1UL << RTC_DR_DT_Pos)                /*!< 0x00000010 */
6738 #define RTC_DR_DT_1                         (0x2UL << RTC_DR_DT_Pos)                /*!< 0x00000020 */
6739 #define RTC_DR_MU_Pos                       (8U)
6740 #define RTC_DR_MU_Msk                       (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */
6741 #define RTC_DR_MU                           RTC_DR_MU_Msk
6742 #define RTC_DR_MU_0                         (0x1UL << RTC_DR_MU_Pos)                /*!< 0x00000100 */
6743 #define RTC_DR_MU_1                         (0x2UL << RTC_DR_MU_Pos)                /*!< 0x00000200 */
6744 #define RTC_DR_MU_2                         (0x4UL << RTC_DR_MU_Pos)                /*!< 0x00000400 */
6745 #define RTC_DR_MU_3                         (0x8UL << RTC_DR_MU_Pos)                /*!< 0x00000800 */
6746 #define RTC_DR_MT_Pos                       (12U)
6747 #define RTC_DR_MT_Msk                       (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */
6748 #define RTC_DR_MT                           RTC_DR_MT_Msk
6749 #define RTC_DR_WDU_Pos                      (13U)
6750 #define RTC_DR_WDU_Msk                      (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */
6751 #define RTC_DR_WDU                          RTC_DR_WDU_Msk
6752 #define RTC_DR_WDU_0                        (0x1UL << RTC_DR_WDU_Pos)               /*!< 0x00002000 */
6753 #define RTC_DR_WDU_1                        (0x2UL << RTC_DR_WDU_Pos)               /*!< 0x00004000 */
6754 #define RTC_DR_WDU_2                        (0x4UL << RTC_DR_WDU_Pos)               /*!< 0x00008000 */
6755 #define RTC_DR_YU_Pos                       (16U)
6756 #define RTC_DR_YU_Msk                       (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */
6757 #define RTC_DR_YU                           RTC_DR_YU_Msk
6758 #define RTC_DR_YU_0                         (0x1UL << RTC_DR_YU_Pos)                /*!< 0x00010000 */
6759 #define RTC_DR_YU_1                         (0x2UL << RTC_DR_YU_Pos)                /*!< 0x00020000 */
6760 #define RTC_DR_YU_2                         (0x4UL << RTC_DR_YU_Pos)                /*!< 0x00040000 */
6761 #define RTC_DR_YU_3                         (0x8UL << RTC_DR_YU_Pos)                /*!< 0x00080000 */
6762 #define RTC_DR_YT_Pos                       (20U)
6763 #define RTC_DR_YT_Msk                       (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */
6764 #define RTC_DR_YT                           RTC_DR_YT_Msk
6765 #define RTC_DR_YT_0                         (0x1UL << RTC_DR_YT_Pos)                /*!< 0x00100000 */
6766 #define RTC_DR_YT_1                         (0x2UL << RTC_DR_YT_Pos)                /*!< 0x00200000 */
6767 #define RTC_DR_YT_2                         (0x4UL << RTC_DR_YT_Pos)                /*!< 0x00400000 */
6768 #define RTC_DR_YT_3                         (0x8UL << RTC_DR_YT_Pos)                /*!< 0x00800000 */
6769 
6770 /********************  Bits definition for RTC_SSR register  ******************/
6771 #define RTC_SSR_SS_Pos                      (0U)
6772 #define RTC_SSR_SS_Msk                      (0xFFFFFFFFUL << RTC_SSR_SS_Pos)        /*!< 0xFFFFFFFF */
6773 #define RTC_SSR_SS                          RTC_SSR_SS_Msk
6774 
6775 /********************  Bits definition for RTC_ICSR register  ******************/
6776 #define RTC_ICSR_WUTWF_Pos                  (2U)
6777 #define RTC_ICSR_WUTWF_Msk                  (0x1UL << RTC_ICSR_WUTWF_Pos)           /*!< 0x00000004 */
6778 #define RTC_ICSR_WUTWF                      RTC_ICSR_WUTWF_Msk
6779 #define RTC_ICSR_SHPF_Pos                   (3U)
6780 #define RTC_ICSR_SHPF_Msk                   (0x1UL << RTC_ICSR_SHPF_Pos)            /*!< 0x00000008 */
6781 #define RTC_ICSR_SHPF                       RTC_ICSR_SHPF_Msk
6782 #define RTC_ICSR_INITS_Pos                  (4U)
6783 #define RTC_ICSR_INITS_Msk                  (0x1UL << RTC_ICSR_INITS_Pos)           /*!< 0x00000010 */
6784 #define RTC_ICSR_INITS                      RTC_ICSR_INITS_Msk
6785 #define RTC_ICSR_RSF_Pos                    (5U)
6786 #define RTC_ICSR_RSF_Msk                    (0x1UL << RTC_ICSR_RSF_Pos)             /*!< 0x00000020 */
6787 #define RTC_ICSR_RSF                        RTC_ICSR_RSF_Msk
6788 #define RTC_ICSR_INITF_Pos                  (6U)
6789 #define RTC_ICSR_INITF_Msk                  (0x1UL << RTC_ICSR_INITF_Pos)           /*!< 0x00000040 */
6790 #define RTC_ICSR_INITF                      RTC_ICSR_INITF_Msk
6791 #define RTC_ICSR_INIT_Pos                   (7U)
6792 #define RTC_ICSR_INIT_Msk                   (0x1UL << RTC_ICSR_INIT_Pos)            /*!< 0x00000080 */
6793 #define RTC_ICSR_INIT                       RTC_ICSR_INIT_Msk
6794 #define RTC_ICSR_BIN_Pos                    (8U)
6795 #define RTC_ICSR_BIN_Msk                    (0x3UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000300 */
6796 #define RTC_ICSR_BIN                        RTC_ICSR_BIN_Msk
6797 #define RTC_ICSR_BIN_0                      (0x1UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000100 */
6798 #define RTC_ICSR_BIN_1                      (0x2UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000200 */
6799 #define RTC_ICSR_BCDU_Pos                   (10U)
6800 #define RTC_ICSR_BCDU_Msk                   (0x7UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001C00 */
6801 #define RTC_ICSR_BCDU                       RTC_ICSR_BCDU_Msk
6802 #define RTC_ICSR_BCDU_0                     (0x1UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000400 */
6803 #define RTC_ICSR_BCDU_1                     (0x2UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000800 */
6804 #define RTC_ICSR_BCDU_2                     (0x4UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001000 */
6805 #define RTC_ICSR_RECALPF_Pos                (16U)
6806 #define RTC_ICSR_RECALPF_Msk                (0x1UL << RTC_ICSR_RECALPF_Pos)         /*!< 0x00010000 */
6807 #define RTC_ICSR_RECALPF                    RTC_ICSR_RECALPF_Msk
6808 
6809 /********************  Bits definition for RTC_PRER register  *****************/
6810 #define RTC_PRER_PREDIV_S_Pos               (0U)
6811 #define RTC_PRER_PREDIV_S_Msk               (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */
6812 #define RTC_PRER_PREDIV_S                   RTC_PRER_PREDIV_S_Msk
6813 #define RTC_PRER_PREDIV_A_Pos               (16U)
6814 #define RTC_PRER_PREDIV_A_Msk               (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */
6815 #define RTC_PRER_PREDIV_A                   RTC_PRER_PREDIV_A_Msk
6816 
6817 /********************  Bits definition for RTC_WUTR register  *****************/
6818 #define RTC_WUTR_WUT_Pos                    (0U)
6819 #define RTC_WUTR_WUT_Msk                    (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */
6820 #define RTC_WUTR_WUT                        RTC_WUTR_WUT_Msk
6821 #define RTC_WUTR_WUTOCLR_Pos                (16U)
6822 #define RTC_WUTR_WUTOCLR_Msk                (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos)      /*!< 0x0000FFFF */
6823 #define RTC_WUTR_WUTOCLR                    RTC_WUTR_WUTOCLR_Msk
6824 
6825 /********************  Bits definition for RTC_CR register  *******************/
6826 #define RTC_CR_WUCKSEL_Pos                  (0U)
6827 #define RTC_CR_WUCKSEL_Msk                  (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */
6828 #define RTC_CR_WUCKSEL                      RTC_CR_WUCKSEL_Msk
6829 #define RTC_CR_WUCKSEL_0                    (0x1UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000001 */
6830 #define RTC_CR_WUCKSEL_1                    (0x2UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000002 */
6831 #define RTC_CR_WUCKSEL_2                    (0x4UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000004 */
6832 #define RTC_CR_TSEDGE_Pos                   (3U)
6833 #define RTC_CR_TSEDGE_Msk                   (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */
6834 #define RTC_CR_TSEDGE                       RTC_CR_TSEDGE_Msk
6835 #define RTC_CR_REFCKON_Pos                  (4U)
6836 #define RTC_CR_REFCKON_Msk                  (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */
6837 #define RTC_CR_REFCKON                      RTC_CR_REFCKON_Msk
6838 #define RTC_CR_BYPSHAD_Pos                  (5U)
6839 #define RTC_CR_BYPSHAD_Msk                  (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */
6840 #define RTC_CR_BYPSHAD                      RTC_CR_BYPSHAD_Msk
6841 #define RTC_CR_FMT_Pos                      (6U)
6842 #define RTC_CR_FMT_Msk                      (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */
6843 #define RTC_CR_FMT                          RTC_CR_FMT_Msk
6844 #define RTC_CR_SSRUIE_Pos                   (7U)
6845 #define RTC_CR_SSRUIE_Msk                   (0x1UL << RTC_CR_SSRUIE_Pos)            /*!< 0x00000080 */
6846 #define RTC_CR_SSRUIE                       RTC_CR_SSRUIE_Msk
6847 #define RTC_CR_ALRAE_Pos                    (8U)
6848 #define RTC_CR_ALRAE_Msk                    (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */
6849 #define RTC_CR_ALRAE                        RTC_CR_ALRAE_Msk
6850 #define RTC_CR_ALRBE_Pos                    (9U)
6851 #define RTC_CR_ALRBE_Msk                    (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */
6852 #define RTC_CR_ALRBE                        RTC_CR_ALRBE_Msk
6853 #define RTC_CR_WUTE_Pos                     (10U)
6854 #define RTC_CR_WUTE_Msk                     (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */
6855 #define RTC_CR_WUTE                         RTC_CR_WUTE_Msk
6856 #define RTC_CR_TSE_Pos                      (11U)
6857 #define RTC_CR_TSE_Msk                      (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */
6858 #define RTC_CR_TSE                          RTC_CR_TSE_Msk
6859 #define RTC_CR_ALRAIE_Pos                   (12U)
6860 #define RTC_CR_ALRAIE_Msk                   (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */
6861 #define RTC_CR_ALRAIE                       RTC_CR_ALRAIE_Msk
6862 #define RTC_CR_ALRBIE_Pos                   (13U)
6863 #define RTC_CR_ALRBIE_Msk                   (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */
6864 #define RTC_CR_ALRBIE                       RTC_CR_ALRBIE_Msk
6865 #define RTC_CR_WUTIE_Pos                    (14U)
6866 #define RTC_CR_WUTIE_Msk                    (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */
6867 #define RTC_CR_WUTIE                        RTC_CR_WUTIE_Msk
6868 #define RTC_CR_TSIE_Pos                     (15U)
6869 #define RTC_CR_TSIE_Msk                     (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */
6870 #define RTC_CR_TSIE                         RTC_CR_TSIE_Msk
6871 #define RTC_CR_ADD1H_Pos                    (16U)
6872 #define RTC_CR_ADD1H_Msk                    (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */
6873 #define RTC_CR_ADD1H                        RTC_CR_ADD1H_Msk
6874 #define RTC_CR_SUB1H_Pos                    (17U)
6875 #define RTC_CR_SUB1H_Msk                    (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */
6876 #define RTC_CR_SUB1H                        RTC_CR_SUB1H_Msk
6877 #define RTC_CR_BKP_Pos                      (18U)
6878 #define RTC_CR_BKP_Msk                      (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */
6879 #define RTC_CR_BKP                          RTC_CR_BKP_Msk
6880 #define RTC_CR_COSEL_Pos                    (19U)
6881 #define RTC_CR_COSEL_Msk                    (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */
6882 #define RTC_CR_COSEL                        RTC_CR_COSEL_Msk
6883 #define RTC_CR_POL_Pos                      (20U)
6884 #define RTC_CR_POL_Msk                      (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */
6885 #define RTC_CR_POL                          RTC_CR_POL_Msk
6886 #define RTC_CR_OSEL_Pos                     (21U)
6887 #define RTC_CR_OSEL_Msk                     (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */
6888 #define RTC_CR_OSEL                         RTC_CR_OSEL_Msk
6889 #define RTC_CR_OSEL_0                       (0x1UL << RTC_CR_OSEL_Pos)              /*!< 0x00200000 */
6890 #define RTC_CR_OSEL_1                       (0x2UL << RTC_CR_OSEL_Pos)              /*!< 0x00400000 */
6891 #define RTC_CR_COE_Pos                      (23U)
6892 #define RTC_CR_COE_Msk                      (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */
6893 #define RTC_CR_COE                          RTC_CR_COE_Msk
6894 #define RTC_CR_ITSE_Pos                     (24U)
6895 #define RTC_CR_ITSE_Msk                     (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */
6896 #define RTC_CR_ITSE                         RTC_CR_ITSE_Msk                         /*!<Timestamp on internal event enable  */
6897 #define RTC_CR_TAMPTS_Pos                   (25U)
6898 #define RTC_CR_TAMPTS_Msk                   (0x1UL << RTC_CR_TAMPTS_Pos)            /*!< 0x02000000 */
6899 #define RTC_CR_TAMPTS                       RTC_CR_TAMPTS_Msk                       /*!<Activate timestamp on tamper detection event  */
6900 #define RTC_CR_TAMPOE_Pos                   (26U)
6901 #define RTC_CR_TAMPOE_Msk                   (0x1UL << RTC_CR_TAMPOE_Pos)            /*!< 0x04000000 */
6902 #define RTC_CR_TAMPOE                       RTC_CR_TAMPOE_Msk                       /*!<Tamper detection output enable on TAMPALARM  */
6903 #define RTC_CR_ALRAFCLR_Pos                 (27U)
6904 #define RTC_CR_ALRAFCLR_Msk                 (0x1UL << RTC_CR_ALRAFCLR_Pos)          /*!< 0x8000000 */
6905 #define RTC_CR_ALRAFCLR                     RTC_CR_ALRAFCLR_Msk                     /*!<Alarm A mask */
6906 #define RTC_CR_ALRBFCLR_Pos                 (28U)
6907 #define RTC_CR_ALRBFCLR_Msk                 (0x1UL << RTC_CR_ALRBFCLR_Pos)          /*!< 0x10000000 */
6908 #define RTC_CR_ALRBFCLR                     RTC_CR_ALRBFCLR_Msk                     /*!<Alarm B mask */
6909 #define RTC_CR_TAMPALRM_PU_Pos              (29U)
6910 #define RTC_CR_TAMPALRM_PU_Msk              (0x1UL << RTC_CR_TAMPALRM_PU_Pos)       /*!< 0x20000000 */
6911 #define RTC_CR_TAMPALRM_PU                  RTC_CR_TAMPALRM_PU_Msk                  /*!<TAMPALARM output pull-up config */
6912 #define RTC_CR_TAMPALRM_TYPE_Pos            (30U)
6913 #define RTC_CR_TAMPALRM_TYPE_Msk            (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)     /*!< 0x40000000 */
6914 #define RTC_CR_TAMPALRM_TYPE                RTC_CR_TAMPALRM_TYPE_Msk                /*!<TAMPALARM output type  */
6915 #define RTC_CR_OUT2EN_Pos                   (31U)
6916 #define RTC_CR_OUT2EN_Msk                   (0x1UL << RTC_CR_OUT2EN_Pos)            /*!< 0x80000000 */
6917 #define RTC_CR_OUT2EN                       RTC_CR_OUT2EN_Msk                       /*!<RTC_OUT2 output enable */
6918 
6919 /********************  Bits definition for RTC_WPR register  ******************/
6920 #define RTC_WPR_KEY_Pos                     (0U)
6921 #define RTC_WPR_KEY_Msk                     (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */
6922 #define RTC_WPR_KEY                         RTC_WPR_KEY_Msk
6923 
6924 /********************  Bits definition for RTC_CALR register  *****************/
6925 #define RTC_CALR_CALM_Pos                   (0U)
6926 #define RTC_CALR_CALM_Msk                   (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */
6927 #define RTC_CALR_CALM                       RTC_CALR_CALM_Msk
6928 #define RTC_CALR_CALM_0                     (0x001UL << RTC_CALR_CALM_Pos)          /*!< 0x00000001 */
6929 #define RTC_CALR_CALM_1                     (0x002UL << RTC_CALR_CALM_Pos)          /*!< 0x00000002 */
6930 #define RTC_CALR_CALM_2                     (0x004UL << RTC_CALR_CALM_Pos)          /*!< 0x00000004 */
6931 #define RTC_CALR_CALM_3                     (0x008UL << RTC_CALR_CALM_Pos)          /*!< 0x00000008 */
6932 #define RTC_CALR_CALM_4                     (0x010UL << RTC_CALR_CALM_Pos)          /*!< 0x00000010 */
6933 #define RTC_CALR_CALM_5                     (0x020UL << RTC_CALR_CALM_Pos)          /*!< 0x00000020 */
6934 #define RTC_CALR_CALM_6                     (0x040UL << RTC_CALR_CALM_Pos)          /*!< 0x00000040 */
6935 #define RTC_CALR_CALM_7                     (0x080UL << RTC_CALR_CALM_Pos)          /*!< 0x00000080 */
6936 #define RTC_CALR_CALM_8                     (0x100UL << RTC_CALR_CALM_Pos)          /*!< 0x00000100 */
6937 #define RTC_CALR_LPCAL_Pos                  (12U)
6938 #define RTC_CALR_LPCAL_Msk                  (0x1UL << RTC_CALR_LPCAL_Pos)           /*!< 0x00001000 */
6939 #define RTC_CALR_LPCAL                      RTC_CALR_LPCAL_Msk
6940 #define RTC_CALR_CALW16_Pos                 (13U)
6941 #define RTC_CALR_CALW16_Msk                 (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */
6942 #define RTC_CALR_CALW16                     RTC_CALR_CALW16_Msk
6943 #define RTC_CALR_CALW8_Pos                  (14U)
6944 #define RTC_CALR_CALW8_Msk                  (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */
6945 #define RTC_CALR_CALW8                      RTC_CALR_CALW8_Msk
6946 #define RTC_CALR_CALP_Pos                   (15U)
6947 #define RTC_CALR_CALP_Msk                   (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */
6948 #define RTC_CALR_CALP                       RTC_CALR_CALP_Msk
6949 
6950 /********************  Bits definition for RTC_SHIFTR register  ***************/
6951 #define RTC_SHIFTR_SUBFS_Pos                (0U)
6952 #define RTC_SHIFTR_SUBFS_Msk                (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */
6953 #define RTC_SHIFTR_SUBFS                    RTC_SHIFTR_SUBFS_Msk
6954 #define RTC_SHIFTR_ADD1S_Pos                (31U)
6955 #define RTC_SHIFTR_ADD1S_Msk                (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */
6956 #define RTC_SHIFTR_ADD1S                    RTC_SHIFTR_ADD1S_Msk
6957 
6958 /********************  Bits definition for RTC_TSTR register  *****************/
6959 #define RTC_TSTR_SU_Pos                     (0U)
6960 #define RTC_TSTR_SU_Msk                     (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */
6961 #define RTC_TSTR_SU                         RTC_TSTR_SU_Msk
6962 #define RTC_TSTR_SU_0                       (0x1UL << RTC_TSTR_SU_Pos)              /*!< 0x00000001 */
6963 #define RTC_TSTR_SU_1                       (0x2UL << RTC_TSTR_SU_Pos)              /*!< 0x00000002 */
6964 #define RTC_TSTR_SU_2                       (0x4UL << RTC_TSTR_SU_Pos)              /*!< 0x00000004 */
6965 #define RTC_TSTR_SU_3                       (0x8UL << RTC_TSTR_SU_Pos)              /*!< 0x00000008 */
6966 #define RTC_TSTR_ST_Pos                     (4U)
6967 #define RTC_TSTR_ST_Msk                     (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */
6968 #define RTC_TSTR_ST                         RTC_TSTR_ST_Msk
6969 #define RTC_TSTR_ST_0                       (0x1UL << RTC_TSTR_ST_Pos)              /*!< 0x00000010 */
6970 #define RTC_TSTR_ST_1                       (0x2UL << RTC_TSTR_ST_Pos)              /*!< 0x00000020 */
6971 #define RTC_TSTR_ST_2                       (0x4UL << RTC_TSTR_ST_Pos)              /*!< 0x00000040 */
6972 #define RTC_TSTR_MNU_Pos                    (8U)
6973 #define RTC_TSTR_MNU_Msk                    (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */
6974 #define RTC_TSTR_MNU                        RTC_TSTR_MNU_Msk
6975 #define RTC_TSTR_MNU_0                      (0x1UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000100 */
6976 #define RTC_TSTR_MNU_1                      (0x2UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000200 */
6977 #define RTC_TSTR_MNU_2                      (0x4UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000400 */
6978 #define RTC_TSTR_MNU_3                      (0x8UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000800 */
6979 #define RTC_TSTR_MNT_Pos                    (12U)
6980 #define RTC_TSTR_MNT_Msk                    (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */
6981 #define RTC_TSTR_MNT                        RTC_TSTR_MNT_Msk
6982 #define RTC_TSTR_MNT_0                      (0x1UL << RTC_TSTR_MNT_Pos)             /*!< 0x00001000 */
6983 #define RTC_TSTR_MNT_1                      (0x2UL << RTC_TSTR_MNT_Pos)             /*!< 0x00002000 */
6984 #define RTC_TSTR_MNT_2                      (0x4UL << RTC_TSTR_MNT_Pos)             /*!< 0x00004000 */
6985 #define RTC_TSTR_HU_Pos                     (16U)
6986 #define RTC_TSTR_HU_Msk                     (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */
6987 #define RTC_TSTR_HU                         RTC_TSTR_HU_Msk
6988 #define RTC_TSTR_HU_0                       (0x1UL << RTC_TSTR_HU_Pos)              /*!< 0x00010000 */
6989 #define RTC_TSTR_HU_1                       (0x2UL << RTC_TSTR_HU_Pos)              /*!< 0x00020000 */
6990 #define RTC_TSTR_HU_2                       (0x4UL << RTC_TSTR_HU_Pos)              /*!< 0x00040000 */
6991 #define RTC_TSTR_HU_3                       (0x8UL << RTC_TSTR_HU_Pos)              /*!< 0x00080000 */
6992 #define RTC_TSTR_HT_Pos                     (20U)
6993 #define RTC_TSTR_HT_Msk                     (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */
6994 #define RTC_TSTR_HT                         RTC_TSTR_HT_Msk
6995 #define RTC_TSTR_HT_0                       (0x1UL << RTC_TSTR_HT_Pos)              /*!< 0x00100000 */
6996 #define RTC_TSTR_HT_1                       (0x2UL << RTC_TSTR_HT_Pos)              /*!< 0x00200000 */
6997 #define RTC_TSTR_PM_Pos                     (22U)
6998 #define RTC_TSTR_PM_Msk                     (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */
6999 #define RTC_TSTR_PM                         RTC_TSTR_PM_Msk
7000 
7001 /********************  Bits definition for RTC_TSDR register  *****************/
7002 #define RTC_TSDR_DU_Pos                     (0U)
7003 #define RTC_TSDR_DU_Msk                     (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */
7004 #define RTC_TSDR_DU                         RTC_TSDR_DU_Msk
7005 #define RTC_TSDR_DU_0                       (0x1UL << RTC_TSDR_DU_Pos)              /*!< 0x00000001 */
7006 #define RTC_TSDR_DU_1                       (0x2UL << RTC_TSDR_DU_Pos)              /*!< 0x00000002 */
7007 #define RTC_TSDR_DU_2                       (0x4UL << RTC_TSDR_DU_Pos)              /*!< 0x00000004 */
7008 #define RTC_TSDR_DU_3                       (0x8UL << RTC_TSDR_DU_Pos)              /*!< 0x00000008 */
7009 #define RTC_TSDR_DT_Pos                     (4U)
7010 #define RTC_TSDR_DT_Msk                     (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */
7011 #define RTC_TSDR_DT                         RTC_TSDR_DT_Msk
7012 #define RTC_TSDR_DT_0                       (0x1UL << RTC_TSDR_DT_Pos)              /*!< 0x00000010 */
7013 #define RTC_TSDR_DT_1                       (0x2UL << RTC_TSDR_DT_Pos)              /*!< 0x00000020 */
7014 #define RTC_TSDR_MU_Pos                     (8U)
7015 #define RTC_TSDR_MU_Msk                     (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */
7016 #define RTC_TSDR_MU                         RTC_TSDR_MU_Msk
7017 #define RTC_TSDR_MU_0                       (0x1UL << RTC_TSDR_MU_Pos)              /*!< 0x00000100 */
7018 #define RTC_TSDR_MU_1                       (0x2UL << RTC_TSDR_MU_Pos)              /*!< 0x00000200 */
7019 #define RTC_TSDR_MU_2                       (0x4UL << RTC_TSDR_MU_Pos)              /*!< 0x00000400 */
7020 #define RTC_TSDR_MU_3                       (0x8UL << RTC_TSDR_MU_Pos)              /*!< 0x00000800 */
7021 #define RTC_TSDR_MT_Pos                     (12U)
7022 #define RTC_TSDR_MT_Msk                     (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */
7023 #define RTC_TSDR_MT                         RTC_TSDR_MT_Msk
7024 #define RTC_TSDR_WDU_Pos                    (13U)
7025 #define RTC_TSDR_WDU_Msk                    (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */
7026 #define RTC_TSDR_WDU                        RTC_TSDR_WDU_Msk
7027 #define RTC_TSDR_WDU_0                      (0x1UL << RTC_TSDR_WDU_Pos)             /*!< 0x00002000 */
7028 #define RTC_TSDR_WDU_1                      (0x2UL << RTC_TSDR_WDU_Pos)             /*!< 0x00004000 */
7029 #define RTC_TSDR_WDU_2                      (0x4UL << RTC_TSDR_WDU_Pos)             /*!< 0x00008000 */
7030 
7031 /********************  Bits definition for RTC_TSSSR register  ****************/
7032 #define RTC_TSSSR_SS_Pos                    (0U)
7033 #define RTC_TSSSR_SS_Msk                    (0xFFFFFFFFUL << RTC_TSSSR_SS_Pos)      /*!< 0xFFFFFFFF */
7034 #define RTC_TSSSR_SS                        RTC_TSSSR_SS_Msk                        /*!< rtc timestamp sub second > */
7035 
7036 /********************  Bits definition for RTC_ALRMAR register  ***************/
7037 #define RTC_ALRMAR_SU_Pos                   (0U)
7038 #define RTC_ALRMAR_SU_Msk                   (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */
7039 #define RTC_ALRMAR_SU                       RTC_ALRMAR_SU_Msk
7040 #define RTC_ALRMAR_SU_0                     (0x1UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000001 */
7041 #define RTC_ALRMAR_SU_1                     (0x2UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000002 */
7042 #define RTC_ALRMAR_SU_2                     (0x4UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000004 */
7043 #define RTC_ALRMAR_SU_3                     (0x8UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000008 */
7044 #define RTC_ALRMAR_ST_Pos                   (4U)
7045 #define RTC_ALRMAR_ST_Msk                   (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */
7046 #define RTC_ALRMAR_ST                       RTC_ALRMAR_ST_Msk
7047 #define RTC_ALRMAR_ST_0                     (0x1UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000010 */
7048 #define RTC_ALRMAR_ST_1                     (0x2UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000020 */
7049 #define RTC_ALRMAR_ST_2                     (0x4UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000040 */
7050 #define RTC_ALRMAR_MSK1_Pos                 (7U)
7051 #define RTC_ALRMAR_MSK1_Msk                 (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */
7052 #define RTC_ALRMAR_MSK1                     RTC_ALRMAR_MSK1_Msk
7053 #define RTC_ALRMAR_MNU_Pos                  (8U)
7054 #define RTC_ALRMAR_MNU_Msk                  (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */
7055 #define RTC_ALRMAR_MNU                      RTC_ALRMAR_MNU_Msk
7056 #define RTC_ALRMAR_MNU_0                    (0x1UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000100 */
7057 #define RTC_ALRMAR_MNU_1                    (0x2UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000200 */
7058 #define RTC_ALRMAR_MNU_2                    (0x4UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000400 */
7059 #define RTC_ALRMAR_MNU_3                    (0x8UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000800 */
7060 #define RTC_ALRMAR_MNT_Pos                  (12U)
7061 #define RTC_ALRMAR_MNT_Msk                  (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */
7062 #define RTC_ALRMAR_MNT                      RTC_ALRMAR_MNT_Msk
7063 #define RTC_ALRMAR_MNT_0                    (0x1UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00001000 */
7064 #define RTC_ALRMAR_MNT_1                    (0x2UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00002000 */
7065 #define RTC_ALRMAR_MNT_2                    (0x4UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00004000 */
7066 #define RTC_ALRMAR_MSK2_Pos                 (15U)
7067 #define RTC_ALRMAR_MSK2_Msk                 (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */
7068 #define RTC_ALRMAR_MSK2                     RTC_ALRMAR_MSK2_Msk
7069 #define RTC_ALRMAR_HU_Pos                   (16U)
7070 #define RTC_ALRMAR_HU_Msk                   (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */
7071 #define RTC_ALRMAR_HU                       RTC_ALRMAR_HU_Msk
7072 #define RTC_ALRMAR_HU_0                     (0x1UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00010000 */
7073 #define RTC_ALRMAR_HU_1                     (0x2UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00020000 */
7074 #define RTC_ALRMAR_HU_2                     (0x4UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00040000 */
7075 #define RTC_ALRMAR_HU_3                     (0x8UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00080000 */
7076 #define RTC_ALRMAR_HT_Pos                   (20U)
7077 #define RTC_ALRMAR_HT_Msk                   (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */
7078 #define RTC_ALRMAR_HT                       RTC_ALRMAR_HT_Msk
7079 #define RTC_ALRMAR_HT_0                     (0x1UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00100000 */
7080 #define RTC_ALRMAR_HT_1                     (0x2UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00200000 */
7081 #define RTC_ALRMAR_PM_Pos                   (22U)
7082 #define RTC_ALRMAR_PM_Msk                   (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */
7083 #define RTC_ALRMAR_PM                       RTC_ALRMAR_PM_Msk
7084 #define RTC_ALRMAR_MSK3_Pos                 (23U)
7085 #define RTC_ALRMAR_MSK3_Msk                 (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */
7086 #define RTC_ALRMAR_MSK3                     RTC_ALRMAR_MSK3_Msk
7087 #define RTC_ALRMAR_DU_Pos                   (24U)
7088 #define RTC_ALRMAR_DU_Msk                   (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */
7089 #define RTC_ALRMAR_DU                       RTC_ALRMAR_DU_Msk
7090 #define RTC_ALRMAR_DU_0                     (0x1UL << RTC_ALRMAR_DU_Pos)            /*!< 0x01000000 */
7091 #define RTC_ALRMAR_DU_1                     (0x2UL << RTC_ALRMAR_DU_Pos)            /*!< 0x02000000 */
7092 #define RTC_ALRMAR_DU_2                     (0x4UL << RTC_ALRMAR_DU_Pos)            /*!< 0x04000000 */
7093 #define RTC_ALRMAR_DU_3                     (0x8UL << RTC_ALRMAR_DU_Pos)            /*!< 0x08000000 */
7094 #define RTC_ALRMAR_DT_Pos                   (28U)
7095 #define RTC_ALRMAR_DT_Msk                   (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */
7096 #define RTC_ALRMAR_DT                       RTC_ALRMAR_DT_Msk
7097 #define RTC_ALRMAR_DT_0                     (0x1UL << RTC_ALRMAR_DT_Pos)            /*!< 0x10000000 */
7098 #define RTC_ALRMAR_DT_1                     (0x2UL << RTC_ALRMAR_DT_Pos)            /*!< 0x20000000 */
7099 #define RTC_ALRMAR_WDSEL_Pos                (30U)
7100 #define RTC_ALRMAR_WDSEL_Msk                (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */
7101 #define RTC_ALRMAR_WDSEL                    RTC_ALRMAR_WDSEL_Msk
7102 #define RTC_ALRMAR_MSK4_Pos                 (31U)
7103 #define RTC_ALRMAR_MSK4_Msk                 (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */
7104 #define RTC_ALRMAR_MSK4                     RTC_ALRMAR_MSK4_Msk
7105 
7106 /********************  Bits definition for RTC_ALRMASSR register  *************/
7107 #define RTC_ALRMASSR_SS_Pos                 (0U)
7108 #define RTC_ALRMASSR_SS_Msk                 (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */
7109 #define RTC_ALRMASSR_SS                     RTC_ALRMASSR_SS_Msk
7110 #define RTC_ALRMASSR_MASKSS_Pos             (24U)
7111 #define RTC_ALRMASSR_MASKSS_Msk             (0x3FUL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x3F000000 */
7112 #define RTC_ALRMASSR_MASKSS                 RTC_ALRMASSR_MASKSS_Msk
7113 #define RTC_ALRMASSR_MASKSS_0               (0x1UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x01000000 */
7114 #define RTC_ALRMASSR_MASKSS_1               (0x2UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x02000000 */
7115 #define RTC_ALRMASSR_MASKSS_2               (0x4UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x04000000 */
7116 #define RTC_ALRMASSR_MASKSS_3               (0x8UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x08000000 */
7117 #define RTC_ALRMASSR_MASKSS_4               (0x10UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x10000000 */
7118 #define RTC_ALRMASSR_MASKSS_5               (0x20UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x20000000 */
7119 #define RTC_ALRMASSR_SSCLR_Pos              (31U)
7120 #define RTC_ALRMASSR_SSCLR_Msk              (0x1UL << RTC_ALRMASSR_SSCLR_Pos)       /*!< 0x80000000 */
7121 #define RTC_ALRMASSR_SSCLR                  RTC_ALRMASSR_SSCLR_Msk
7122 
7123 /********************  Bits definition for RTC_ALRMBR register  ***************/
7124 #define RTC_ALRMBR_SU_Pos                   (0U)
7125 #define RTC_ALRMBR_SU_Msk                   (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */
7126 #define RTC_ALRMBR_SU                       RTC_ALRMBR_SU_Msk
7127 #define RTC_ALRMBR_SU_0                     (0x1UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000001 */
7128 #define RTC_ALRMBR_SU_1                     (0x2UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000002 */
7129 #define RTC_ALRMBR_SU_2                     (0x4UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000004 */
7130 #define RTC_ALRMBR_SU_3                     (0x8UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000008 */
7131 #define RTC_ALRMBR_ST_Pos                   (4U)
7132 #define RTC_ALRMBR_ST_Msk                   (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */
7133 #define RTC_ALRMBR_ST                       RTC_ALRMBR_ST_Msk
7134 #define RTC_ALRMBR_ST_0                     (0x1UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000010 */
7135 #define RTC_ALRMBR_ST_1                     (0x2UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000020 */
7136 #define RTC_ALRMBR_ST_2                     (0x4UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000040 */
7137 #define RTC_ALRMBR_MSK1_Pos                 (7U)
7138 #define RTC_ALRMBR_MSK1_Msk                 (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */
7139 #define RTC_ALRMBR_MSK1                     RTC_ALRMBR_MSK1_Msk
7140 #define RTC_ALRMBR_MNU_Pos                  (8U)
7141 #define RTC_ALRMBR_MNU_Msk                  (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */
7142 #define RTC_ALRMBR_MNU                      RTC_ALRMBR_MNU_Msk
7143 #define RTC_ALRMBR_MNU_0                    (0x1UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000100 */
7144 #define RTC_ALRMBR_MNU_1                    (0x2UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000200 */
7145 #define RTC_ALRMBR_MNU_2                    (0x4UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000400 */
7146 #define RTC_ALRMBR_MNU_3                    (0x8UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000800 */
7147 #define RTC_ALRMBR_MNT_Pos                  (12U)
7148 #define RTC_ALRMBR_MNT_Msk                  (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */
7149 #define RTC_ALRMBR_MNT                      RTC_ALRMBR_MNT_Msk
7150 #define RTC_ALRMBR_MNT_0                    (0x1UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00001000 */
7151 #define RTC_ALRMBR_MNT_1                    (0x2UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00002000 */
7152 #define RTC_ALRMBR_MNT_2                    (0x4UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00004000 */
7153 #define RTC_ALRMBR_MSK2_Pos                 (15U)
7154 #define RTC_ALRMBR_MSK2_Msk                 (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */
7155 #define RTC_ALRMBR_MSK2                     RTC_ALRMBR_MSK2_Msk
7156 #define RTC_ALRMBR_HU_Pos                   (16U)
7157 #define RTC_ALRMBR_HU_Msk                   (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */
7158 #define RTC_ALRMBR_HU                       RTC_ALRMBR_HU_Msk
7159 #define RTC_ALRMBR_HU_0                     (0x1UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00010000 */
7160 #define RTC_ALRMBR_HU_1                     (0x2UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00020000 */
7161 #define RTC_ALRMBR_HU_2                     (0x4UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00040000 */
7162 #define RTC_ALRMBR_HU_3                     (0x8UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00080000 */
7163 #define RTC_ALRMBR_HT_Pos                   (20U)
7164 #define RTC_ALRMBR_HT_Msk                   (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */
7165 #define RTC_ALRMBR_HT                       RTC_ALRMBR_HT_Msk
7166 #define RTC_ALRMBR_HT_0                     (0x1UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00100000 */
7167 #define RTC_ALRMBR_HT_1                     (0x2UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00200000 */
7168 #define RTC_ALRMBR_PM_Pos                   (22U)
7169 #define RTC_ALRMBR_PM_Msk                   (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */
7170 #define RTC_ALRMBR_PM                       RTC_ALRMBR_PM_Msk
7171 #define RTC_ALRMBR_MSK3_Pos                 (23U)
7172 #define RTC_ALRMBR_MSK3_Msk                 (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */
7173 #define RTC_ALRMBR_MSK3                     RTC_ALRMBR_MSK3_Msk
7174 #define RTC_ALRMBR_DU_Pos                   (24U)
7175 #define RTC_ALRMBR_DU_Msk                   (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */
7176 #define RTC_ALRMBR_DU                       RTC_ALRMBR_DU_Msk
7177 #define RTC_ALRMBR_DU_0                     (0x1UL << RTC_ALRMBR_DU_Pos)            /*!< 0x01000000 */
7178 #define RTC_ALRMBR_DU_1                     (0x2UL << RTC_ALRMBR_DU_Pos)            /*!< 0x02000000 */
7179 #define RTC_ALRMBR_DU_2                     (0x4UL << RTC_ALRMBR_DU_Pos)            /*!< 0x04000000 */
7180 #define RTC_ALRMBR_DU_3                     (0x8UL << RTC_ALRMBR_DU_Pos)            /*!< 0x08000000 */
7181 #define RTC_ALRMBR_DT_Pos                   (28U)
7182 #define RTC_ALRMBR_DT_Msk                   (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */
7183 #define RTC_ALRMBR_DT                       RTC_ALRMBR_DT_Msk
7184 #define RTC_ALRMBR_DT_0                     (0x1UL << RTC_ALRMBR_DT_Pos)            /*!< 0x10000000 */
7185 #define RTC_ALRMBR_DT_1                     (0x2UL << RTC_ALRMBR_DT_Pos)            /*!< 0x20000000 */
7186 #define RTC_ALRMBR_WDSEL_Pos                (30U)
7187 #define RTC_ALRMBR_WDSEL_Msk                (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */
7188 #define RTC_ALRMBR_WDSEL                    RTC_ALRMBR_WDSEL_Msk
7189 #define RTC_ALRMBR_MSK4_Pos                 (31U)
7190 #define RTC_ALRMBR_MSK4_Msk                 (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */
7191 #define RTC_ALRMBR_MSK4                     RTC_ALRMBR_MSK4_Msk
7192 
7193 /********************  Bits definition for RTC_ALRMBSSR register  *************/
7194 #define RTC_ALRMBSSR_SS_Pos                 (0U)
7195 #define RTC_ALRMBSSR_SS_Msk                 (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */
7196 #define RTC_ALRMBSSR_SS                     RTC_ALRMBSSR_SS_Msk
7197 #define RTC_ALRMBSSR_MASKSS_Pos             (24U)
7198 #define RTC_ALRMBSSR_MASKSS_Msk             (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x3F000000 */
7199 #define RTC_ALRMBSSR_MASKSS                 RTC_ALRMBSSR_MASKSS_Msk
7200 #define RTC_ALRMBSSR_MASKSS_0               (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x01000000 */
7201 #define RTC_ALRMBSSR_MASKSS_1               (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x02000000 */
7202 #define RTC_ALRMBSSR_MASKSS_2               (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x04000000 */
7203 #define RTC_ALRMBSSR_MASKSS_3               (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x08000000 */
7204 #define RTC_ALRMBSSR_MASKSS_4               (0x10UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x10000000 */
7205 #define RTC_ALRMBSSR_MASKSS_5               (0x20UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x20000000 */
7206 #define RTC_ALRMBSSR_SSCLR_Pos              (31U)
7207 #define RTC_ALRMBSSR_SSCLR_Msk              (0x1UL << RTC_ALRMBSSR_SSCLR_Pos)       /*!< 0x80000000 */
7208 #define RTC_ALRMBSSR_SSCLR                  RTC_ALRMBSSR_SSCLR_Msk
7209 
7210 /********************  Bits definition for RTC_SR register  *******************/
7211 #define RTC_SR_ALRAF_Pos                    (0U)
7212 #define RTC_SR_ALRAF_Msk                    (0x1UL << RTC_SR_ALRAF_Pos)             /*!< 0x00000001 */
7213 #define RTC_SR_ALRAF                        RTC_SR_ALRAF_Msk
7214 #define RTC_SR_ALRBF_Pos                    (1U)
7215 #define RTC_SR_ALRBF_Msk                    (0x1UL << RTC_SR_ALRBF_Pos)             /*!< 0x00000002 */
7216 #define RTC_SR_ALRBF                        RTC_SR_ALRBF_Msk
7217 #define RTC_SR_WUTF_Pos                     (2U)
7218 #define RTC_SR_WUTF_Msk                     (0x1UL << RTC_SR_WUTF_Pos)              /*!< 0x00000004 */
7219 #define RTC_SR_WUTF                         RTC_SR_WUTF_Msk
7220 #define RTC_SR_TSF_Pos                      (3U)
7221 #define RTC_SR_TSF_Msk                      (0x1UL << RTC_SR_TSF_Pos)               /*!< 0x00000008 */
7222 #define RTC_SR_TSF                          RTC_SR_TSF_Msk
7223 #define RTC_SR_TSOVF_Pos                    (4U)
7224 #define RTC_SR_TSOVF_Msk                    (0x1UL << RTC_SR_TSOVF_Pos)             /*!< 0x00000010 */
7225 #define RTC_SR_TSOVF                        RTC_SR_TSOVF_Msk
7226 #define RTC_SR_ITSF_Pos                     (5U)
7227 #define RTC_SR_ITSF_Msk                     (0x1UL << RTC_SR_ITSF_Pos)              /*!< 0x00000020 */
7228 #define RTC_SR_ITSF                         RTC_SR_ITSF_Msk
7229 #define RTC_SR_SSRUF_Pos                    (6U)
7230 #define RTC_SR_SSRUF_Msk                    (0x1UL << RTC_SR_SSRUF_Pos)             /*!< 0x00000040 */
7231 #define RTC_SR_SSRUF                        RTC_SR_SSRUF_Msk
7232 
7233 /********************  Bits definition for RTC_MISR register  *****************/
7234 #define RTC_MISR_ALRAMF_Pos                 (0U)
7235 #define RTC_MISR_ALRAMF_Msk                 (0x1UL << RTC_MISR_ALRAMF_Pos)          /*!< 0x00000001 */
7236 #define RTC_MISR_ALRAMF                     RTC_MISR_ALRAMF_Msk
7237 #define RTC_MISR_ALRBMF_Pos                 (1U)
7238 #define RTC_MISR_ALRBMF_Msk                 (0x1UL << RTC_MISR_ALRBMF_Pos)          /*!< 0x00000002 */
7239 #define RTC_MISR_ALRBMF                     RTC_MISR_ALRBMF_Msk
7240 #define RTC_MISR_WUTMF_Pos                  (2U)
7241 #define RTC_MISR_WUTMF_Msk                  (0x1UL << RTC_MISR_WUTMF_Pos)           /*!< 0x00000004 */
7242 #define RTC_MISR_WUTMF                      RTC_MISR_WUTMF_Msk
7243 #define RTC_MISR_TSMF_Pos                   (3U)
7244 #define RTC_MISR_TSMF_Msk                   (0x1UL << RTC_MISR_TSMF_Pos)            /*!< 0x00000008 */
7245 #define RTC_MISR_TSMF                       RTC_MISR_TSMF_Msk
7246 #define RTC_MISR_TSOVMF_Pos                 (4U)
7247 #define RTC_MISR_TSOVMF_Msk                 (0x1UL << RTC_MISR_TSOVMF_Pos)          /*!< 0x00000010 */
7248 #define RTC_MISR_TSOVMF                     RTC_MISR_TSOVMF_Msk
7249 #define RTC_MISR_ITSMF_Pos                  (5U)
7250 #define RTC_MISR_ITSMF_Msk                  (0x1UL << RTC_MISR_ITSMF_Pos)           /*!< 0x00000020 */
7251 #define RTC_MISR_ITSMF                      RTC_MISR_ITSMF_Msk
7252 #define RTC_MISR_SSRUMF_Pos                 (6U)
7253 #define RTC_MISR_SSRUMF_Msk                 (0x1UL << RTC_MISR_SSRUMF_Pos)          /*!< 0x00000040 */
7254 #define RTC_MISR_SSRUMF                     RTC_MISR_SSRUMF_Msk
7255 
7256 /********************  Bits definition for RTC_SCR register  ******************/
7257 #define RTC_SCR_CALRAF_Pos                  (0U)
7258 #define RTC_SCR_CALRAF_Msk                  (0x1UL << RTC_SCR_CALRAF_Pos)           /*!< 0x00000001 */
7259 #define RTC_SCR_CALRAF                      RTC_SCR_CALRAF_Msk
7260 #define RTC_SCR_CALRBF_Pos                  (1U)
7261 #define RTC_SCR_CALRBF_Msk                  (0x1UL << RTC_SCR_CALRBF_Pos)           /*!< 0x00000002 */
7262 #define RTC_SCR_CALRBF                      RTC_SCR_CALRBF_Msk
7263 #define RTC_SCR_CWUTF_Pos                   (2U)
7264 #define RTC_SCR_CWUTF_Msk                   (0x1UL << RTC_SCR_CWUTF_Pos)            /*!< 0x00000004 */
7265 #define RTC_SCR_CWUTF                       RTC_SCR_CWUTF_Msk
7266 #define RTC_SCR_CTSF_Pos                    (3U)
7267 #define RTC_SCR_CTSF_Msk                    (0x1UL << RTC_SCR_CTSF_Pos)             /*!< 0x00000008 */
7268 #define RTC_SCR_CTSF                        RTC_SCR_CTSF_Msk
7269 #define RTC_SCR_CTSOVF_Pos                  (4U)
7270 #define RTC_SCR_CTSOVF_Msk                  (0x1UL << RTC_SCR_CTSOVF_Pos)           /*!< 0x00000010 */
7271 #define RTC_SCR_CTSOVF                      RTC_SCR_CTSOVF_Msk
7272 #define RTC_SCR_CITSF_Pos                   (5U)
7273 #define RTC_SCR_CITSF_Msk                   (0x1UL << RTC_SCR_CITSF_Pos)            /*!< 0x00000020 */
7274 #define RTC_SCR_CITSF                       RTC_SCR_CITSF_Msk
7275 #define RTC_SCR_CSSRUF_Pos                  (6U)
7276 #define RTC_SCR_CSSRUF_Msk                  (0x1UL << RTC_SCR_CSSRUF_Pos)           /*!< 0x00000040 */
7277 #define RTC_SCR_CSSRUF                      RTC_SCR_CSSRUF_Msk
7278 
7279 /********************  Bits definition for RTC_ALRABINR register  ******************/
7280 #define RTC_ALRABINR_SS_Pos                 (0U)
7281 #define RTC_ALRABINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos)   /*!< 0xFFFFFFFF */
7282 #define RTC_ALRABINR_SS                     RTC_ALRABINR_SS_Msk
7283 
7284 /********************  Bits definition for RTC_ALRBBINR register  ******************/
7285 #define RTC_ALRBBINR_SS_Pos                 (0U)
7286 #define RTC_ALRBBINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos)   /*!< 0xFFFFFFFF */
7287 #define RTC_ALRBBINR_SS                     RTC_ALRBBINR_SS_Msk
7288 
7289 /******************************************************************************/
7290 /*                                                                            */
7291 /*                     Tamper and backup register (TAMP)                      */
7292 /*                                                                            */
7293 /******************************************************************************/
7294 /********************  Bits definition for TAMP_CR1 register  *****************/
7295 #define TAMP_CR1_TAMP1E_Pos          (0U)
7296 #define TAMP_CR1_TAMP1E_Msk          (0x1UL << TAMP_CR1_TAMP1E_Pos)            /*!< 0x00000001 */
7297 #define TAMP_CR1_TAMP1E              TAMP_CR1_TAMP1E_Msk
7298 #define TAMP_CR1_TAMP2E_Pos          (1U)
7299 #define TAMP_CR1_TAMP2E_Msk          (0x1UL << TAMP_CR1_TAMP2E_Pos)            /*!< 0x00000002 */
7300 #define TAMP_CR1_TAMP2E              TAMP_CR1_TAMP2E_Msk
7301 #define TAMP_CR1_TAMP3E_Pos          (2U)
7302 #define TAMP_CR1_TAMP3E_Msk          (0x1UL << TAMP_CR1_TAMP3E_Pos)            /*!< 0x00000004 */
7303 #define TAMP_CR1_TAMP3E              TAMP_CR1_TAMP3E_Msk
7304 #define TAMP_CR1_TAMP4E_Pos          (3U)
7305 #define TAMP_CR1_TAMP4E_Msk          (0x1UL << TAMP_CR1_TAMP4E_Pos)            /*!< 0x00000008 */
7306 #define TAMP_CR1_TAMP4E              TAMP_CR1_TAMP4E_Msk
7307 #define TAMP_CR1_TAMP5E_Pos          (4U)
7308 #define TAMP_CR1_TAMP5E_Msk          (0x1UL << TAMP_CR1_TAMP5E_Pos)            /*!< 0x00000010 */
7309 #define TAMP_CR1_TAMP5E              TAMP_CR1_TAMP5E_Msk
7310 #define TAMP_CR1_ITAMP3E_Pos         (18U)
7311 #define TAMP_CR1_ITAMP3E_Msk         (0x1UL << TAMP_CR1_ITAMP3E_Pos)           /*!< 0x00040000 */
7312 #define TAMP_CR1_ITAMP3E             TAMP_CR1_ITAMP3E_Msk
7313 #define TAMP_CR1_ITAMP4E_Pos         (19U)
7314 #define TAMP_CR1_ITAMP4E_Msk         (0x1UL << TAMP_CR1_ITAMP4E_Pos)           /*!< 0x00080000 */
7315 #define TAMP_CR1_ITAMP4E             TAMP_CR1_ITAMP4E_Msk
7316 #define TAMP_CR1_ITAMP5E_Pos         (20U)
7317 #define TAMP_CR1_ITAMP5E_Msk         (0x1UL << TAMP_CR1_ITAMP5E_Pos)           /*!< 0x00100000 */
7318 #define TAMP_CR1_ITAMP5E             TAMP_CR1_ITAMP5E_Msk
7319 #define TAMP_CR1_ITAMP6E_Pos         (21U)
7320 #define TAMP_CR1_ITAMP6E_Msk         (0x1UL << TAMP_CR1_ITAMP6E_Pos)           /*!< 0x00200000 */
7321 #define TAMP_CR1_ITAMP6E             TAMP_CR1_ITAMP6E_Msk
7322 
7323 /********************  Bits definition for TAMP_CR2 register  *****************/
7324 #define TAMP_CR2_TAMP1POM_Pos        (0U)
7325 #define TAMP_CR2_TAMP1POM_Msk        (0x1UL << TAMP_CR2_TAMP1POM_Pos)      /*!< 0x00000001 */
7326 #define TAMP_CR2_TAMP1POM            TAMP_CR2_TAMP1POM_Msk
7327 #define TAMP_CR2_TAMP2POM_Pos        (1U)
7328 #define TAMP_CR2_TAMP2POM_Msk        (0x1UL << TAMP_CR2_TAMP2POM_Pos)      /*!< 0x00000002 */
7329 #define TAMP_CR2_TAMP2POM            TAMP_CR2_TAMP2POM_Msk
7330 #define TAMP_CR2_TAMP3POM_Pos        (2U)
7331 #define TAMP_CR2_TAMP3POM_Msk        (0x1UL << TAMP_CR2_TAMP3POM_Pos)      /*!< 0x00000004 */
7332 #define TAMP_CR2_TAMP3POM            TAMP_CR2_TAMP3POM_Msk
7333 #define TAMP_CR2_TAMP4POM_Pos        (3U)
7334 #define TAMP_CR2_TAMP4POM_Msk        (0x1UL << TAMP_CR2_TAMP4POM_Pos)      /*!< 0x00000004 */
7335 #define TAMP_CR2_TAMP4POM            TAMP_CR2_TAMP4POM_Msk
7336 #define TAMP_CR2_TAMP5POM_Pos        (4U)
7337 #define TAMP_CR2_TAMP5POM_Msk        (0x1UL << TAMP_CR2_TAMP5POM_Pos)      /*!< 0x00000004 */
7338 #define TAMP_CR2_TAMP5POM            TAMP_CR2_TAMP5POM_Msk
7339 #define TAMP_CR2_TAMP1MSK_Pos        (16U)
7340 #define TAMP_CR2_TAMP1MSK_Msk        (0x1UL << TAMP_CR2_TAMP1MSK_Pos)          /*!< 0x00010000 */
7341 #define TAMP_CR2_TAMP1MSK            TAMP_CR2_TAMP1MSK_Msk
7342 #define TAMP_CR2_TAMP2MSK_Pos        (17U)
7343 #define TAMP_CR2_TAMP2MSK_Msk        (0x1UL << TAMP_CR2_TAMP2MSK_Pos)          /*!< 0x00020000 */
7344 #define TAMP_CR2_TAMP2MSK            TAMP_CR2_TAMP2MSK_Msk
7345 #define TAMP_CR2_TAMP3MSK_Pos        (18U)
7346 #define TAMP_CR2_TAMP3MSK_Msk        (0x1UL << TAMP_CR2_TAMP3MSK_Pos)          /*!< 0x00040000 */
7347 #define TAMP_CR2_TAMP3MSK            TAMP_CR2_TAMP3MSK_Msk
7348 #define TAMP_CR2_BKBLOCK_Pos         (22U)
7349 #define TAMP_CR2_BKBLOCK_Msk         (0x1UL << TAMP_CR2_BKBLOCK_Pos)           /*!< 0x00400000 */
7350 #define TAMP_CR2_BKBLOCK             TAMP_CR2_BKBLOCK_Msk
7351 #define TAMP_CR2_BKERASE_Pos         (23U)
7352 #define TAMP_CR2_BKERASE_Msk         (0x1UL << TAMP_CR2_BKERASE_Pos)           /*!< 0x00800000 */
7353 #define TAMP_CR2_BKERASE             TAMP_CR2_BKERASE_Msk
7354 #define TAMP_CR2_TAMP1TRG_Pos        (24U)
7355 #define TAMP_CR2_TAMP1TRG_Msk        (0x1UL << TAMP_CR2_TAMP1TRG_Pos)          /*!< 0x01000000 */
7356 #define TAMP_CR2_TAMP1TRG            TAMP_CR2_TAMP1TRG_Msk
7357 #define TAMP_CR2_TAMP2TRG_Pos        (25U)
7358 #define TAMP_CR2_TAMP2TRG_Msk        (0x1UL << TAMP_CR2_TAMP2TRG_Pos)          /*!< 0x02000000 */
7359 #define TAMP_CR2_TAMP2TRG            TAMP_CR2_TAMP2TRG_Msk
7360 #define TAMP_CR2_TAMP3TRG_Pos        (26U)
7361 #define TAMP_CR2_TAMP3TRG_Msk        (0x1UL << TAMP_CR2_TAMP3TRG_Pos)          /*!< 0x04000000 */
7362 #define TAMP_CR2_TAMP3TRG            TAMP_CR2_TAMP3TRG_Msk
7363 #define TAMP_CR2_TAMP4TRG_Pos        (27U)
7364 #define TAMP_CR2_TAMP4TRG_Msk        (0x1UL << TAMP_CR2_TAMP4TRG_Pos)          /*!< 0x04000000 */
7365 #define TAMP_CR2_TAMP4TRG            TAMP_CR2_TAMP4TRG_Msk
7366 #define TAMP_CR2_TAMP5TRG_Pos        (28U)
7367 #define TAMP_CR2_TAMP5TRG_Msk        (0x1UL << TAMP_CR2_TAMP5TRG_Pos)          /*!< 0x04000000 */
7368 #define TAMP_CR2_TAMP5TRG            TAMP_CR2_TAMP5TRG_Msk
7369 
7370 /********************  Bits definition for TAMP_CR3 register  *****************/
7371 #define TAMP_CR3_ITAMP3POM_Pos             (2U)
7372 #define TAMP_CR3_ITAMP3POM_Msk             (0x1UL << TAMP_CR3_ITAMP3POM_Pos)      /*!< 0x00000004 */
7373 #define TAMP_CR3_ITAMP3POM                 TAMP_CR3_ITAMP3POM_Msk
7374 #define TAMP_CR3_ITAMP4POM_Pos             (3U)
7375 #define TAMP_CR3_ITAMP4POM_Msk             (0x1UL << TAMP_CR3_ITAMP4POM_Pos)      /*!< 0x00000008 */
7376 #define TAMP_CR3_ITAMP4POM                 TAMP_CR3_ITAMP4POM_Msk
7377 #define TAMP_CR3_ITAMP5POM_Pos             (4U)
7378 #define TAMP_CR3_ITAMP5POM_Msk             (0x1UL << TAMP_CR3_ITAMP5POM_Pos)      /*!< 0x00000010 */
7379 #define TAMP_CR3_ITAMP5POM                 TAMP_CR3_ITAMP5NOER_Msk
7380 #define TAMP_CR3_ITAMP6POM_Pos             (5U)
7381 #define TAMP_CR3_ITAMP6POM_Msk             (0x1UL << TAMP_CR3_ITAMP6tPOM_Pos)      /*!< 0x00000020 */
7382 #define TAMP_CR3_ITAMP6POM                 TAMP_CR3_ITAMP6POM_Msk
7383 
7384 /********************  Bits definition for TAMP_FLTCR register  ***************/
7385 #define TAMP_FLTCR_TAMPFREQ_Pos      (0U)
7386 #define TAMP_FLTCR_TAMPFREQ_Msk      (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000007 */
7387 #define TAMP_FLTCR_TAMPFREQ          TAMP_FLTCR_TAMPFREQ_Msk
7388 #define TAMP_FLTCR_TAMPFREQ_0        (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000001 */
7389 #define TAMP_FLTCR_TAMPFREQ_1        (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000002 */
7390 #define TAMP_FLTCR_TAMPFREQ_2        (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000004 */
7391 #define TAMP_FLTCR_TAMPFLT_Pos       (3U)
7392 #define TAMP_FLTCR_TAMPFLT_Msk       (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000018 */
7393 #define TAMP_FLTCR_TAMPFLT           TAMP_FLTCR_TAMPFLT_Msk
7394 #define TAMP_FLTCR_TAMPFLT_0         (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000008 */
7395 #define TAMP_FLTCR_TAMPFLT_1         (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000010 */
7396 #define TAMP_FLTCR_TAMPPRCH_Pos      (5U)
7397 #define TAMP_FLTCR_TAMPPRCH_Msk      (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000060 */
7398 #define TAMP_FLTCR_TAMPPRCH          TAMP_FLTCR_TAMPPRCH_Msk
7399 #define TAMP_FLTCR_TAMPPRCH_0        (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000020 */
7400 #define TAMP_FLTCR_TAMPPRCH_1        (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000040 */
7401 #define TAMP_FLTCR_TAMPPUDIS_Pos     (7U)
7402 #define TAMP_FLTCR_TAMPPUDIS_Msk     (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)        /*!< 0x00000080 */
7403 #define TAMP_FLTCR_TAMPPUDIS         TAMP_FLTCR_TAMPPUDIS_Msk
7404 
7405 /********************  Bits definition for TAMP_IER register  *****************/
7406 #define TAMP_IER_TAMP1IE_Pos         (0U)
7407 #define TAMP_IER_TAMP1IE_Msk         (0x1UL << TAMP_IER_TAMP1IE_Pos)           /*!< 0x00000001 */
7408 #define TAMP_IER_TAMP1IE             TAMP_IER_TAMP1IE_Msk
7409 #define TAMP_IER_TAMP2IE_Pos         (1U)
7410 #define TAMP_IER_TAMP2IE_Msk         (0x1UL << TAMP_IER_TAMP2IE_Pos)           /*!< 0x00000002 */
7411 #define TAMP_IER_TAMP2IE             TAMP_IER_TAMP2IE_Msk
7412 #define TAMP_IER_TAMP3IE_Pos         (2U)
7413 #define TAMP_IER_TAMP3IE_Msk         (0x1UL << TAMP_IER_TAMP3IE_Pos)           /*!< 0x00000004 */
7414 #define TAMP_IER_TAMP3IE             TAMP_IER_TAMP3IE_Msk
7415 #define TAMP_IER_TAMP4IE_Pos         (3U)
7416 #define TAMP_IER_TAMP4IE_Msk         (0x1UL << TAMP_IER_TAMP4IE_Pos)           /*!< 0x00000004 */
7417 #define TAMP_IER_TAMP4IE             TAMP_IER_TAMP4IE_Msk
7418 #define TAMP_IER_TAMP5IE_Pos         (4U)
7419 #define TAMP_IER_TAMP5IE_Msk         (0x1UL << TAMP_IER_TAMP5IE_Pos)           /*!< 0x00000004 */
7420 #define TAMP_IER_TAMP5IE             TAMP_IER_TAMP5IE_Msk
7421 #define TAMP_IER_ITAMP3IE_Pos        (18U)
7422 #define TAMP_IER_ITAMP3IE_Msk        (0x1UL << TAMP_IER_ITAMP3IE_Pos)          /*!< 0x00040000 */
7423 #define TAMP_IER_ITAMP3IE            TAMP_IER_ITAMP3IE_Msk
7424 #define TAMP_IER_ITAMP4IE_Pos        (19U)
7425 #define TAMP_IER_ITAMP4IE_Msk        (0x1UL << TAMP_IER_ITAMP4IE_Pos)          /*!< 0x00080000 */
7426 #define TAMP_IER_ITAMP4IE            TAMP_IER_ITAMP4IE_Msk
7427 #define TAMP_IER_ITAMP5IE_Pos        (20U)
7428 #define TAMP_IER_ITAMP5IE_Msk        (0x1UL << TAMP_IER_ITAMP5IE_Pos)          /*!< 0x00100000 */
7429 #define TAMP_IER_ITAMP5IE            TAMP_IER_ITAMP5IE_Msk
7430 #define TAMP_IER_ITAMP6IE_Pos        (21U)
7431 #define TAMP_IER_ITAMP6IE_Msk        (0x1UL << TAMP_IER_ITAMP6IE_Pos)          /*!< 0x00200000 */
7432 #define TAMP_IER_ITAMP6IE            TAMP_IER_ITAMP6IE_Msk
7433 
7434 /********************  Bits definition for TAMP_SR register  *****************/
7435 #define TAMP_SR_TAMP1F_Pos           (0U)
7436 #define TAMP_SR_TAMP1F_Msk           (0x1UL << TAMP_SR_TAMP1F_Pos)             /*!< 0x00000001 */
7437 #define TAMP_SR_TAMP1F               TAMP_SR_TAMP1F_Msk
7438 #define TAMP_SR_TAMP2F_Pos           (1U)
7439 #define TAMP_SR_TAMP2F_Msk           (0x1UL << TAMP_SR_TAMP2F_Pos)             /*!< 0x00000002 */
7440 #define TAMP_SR_TAMP2F               TAMP_SR_TAMP2F_Msk
7441 #define TAMP_SR_TAMP3F_Pos           (2U)
7442 #define TAMP_SR_TAMP3F_Msk           (0x1UL << TAMP_SR_TAMP3F_Pos)             /*!< 0x00000004 */
7443 #define TAMP_SR_TAMP3F               TAMP_SR_TAMP3F_Msk
7444 #define TAMP_SR_TAMP4F_Pos           (3U)
7445 #define TAMP_SR_TAMP4F_Msk           (0x1UL << TAMP_SR_TAMP4F_Pos)             /*!< 0x00000004 */
7446 #define TAMP_SR_TAMP4F               TAMP_SR_TAMP4F_Msk
7447 #define TAMP_SR_TAMP5F_Pos           (4U)
7448 #define TAMP_SR_TAMP5F_Msk           (0x1UL << TAMP_SR_TAMP5F_Pos)             /*!< 0x00000004 */
7449 #define TAMP_SR_TAMP5F               TAMP_SR_TAMP5F_Msk
7450 #define TAMP_SR_ITAMP3F_Pos          (18U)
7451 #define TAMP_SR_ITAMP3F_Msk          (0x1UL << TAMP_SR_ITAMP3F_Pos)            /*!< 0x00040000 */
7452 #define TAMP_SR_ITAMP3F              TAMP_SR_ITAMP3F_Msk
7453 #define TAMP_SR_ITAMP4F_Pos          (19U)
7454 #define TAMP_SR_ITAMP4F_Msk          (0x1UL << TAMP_SR_ITAMP4F_Pos)            /*!< 0x00080000 */
7455 #define TAMP_SR_ITAMP4F              TAMP_SR_ITAMP4F_Msk
7456 #define TAMP_SR_ITAMP5F_Pos          (20U)
7457 #define TAMP_SR_ITAMP5F_Msk          (0x1UL << TAMP_SR_ITAMP5F_Pos)            /*!< 0x00100000 */
7458 #define TAMP_SR_ITAMP5F              TAMP_SR_ITAMP5F_Msk
7459 #define TAMP_SR_ITAMP6F_Pos          (21U)
7460 #define TAMP_SR_ITAMP6F_Msk          (0x1UL << TAMP_SR_ITAMP6F_Pos)            /*!< 0x00200000 */
7461 #define TAMP_SR_ITAMP6F              TAMP_SR_ITAMP6F_Msk
7462 
7463 /********************  Bits definition for TAMP_MISR register  ************ *****/
7464 #define TAMP_MISR_TAMP1MF_Pos        (0U)
7465 #define TAMP_MISR_TAMP1MF_Msk        (0x1UL << TAMP_MISR_TAMP1MF_Pos)           /*!< 0x00000001 */
7466 #define TAMP_MISR_TAMP1MF            TAMP_MISR_TAMP1MF_Msk
7467 #define TAMP_MISR_TAMP2MF_Pos        (1U)
7468 #define TAMP_MISR_TAMP2MF_Msk        (0x1UL << TAMP_MISR_TAMP2MF_Pos)           /*!< 0x00000002 */
7469 #define TAMP_MISR_TAMP2MF            TAMP_MISR_TAMP2MF_Msk
7470 #define TAMP_MISR_TAMP3MF_Pos        (2U)
7471 #define TAMP_MISR_TAMP3MF_Msk        (0x1UL << TAMP_MISR_TAMP3MF_Pos)          /*!< 0x00000004 */
7472 #define TAMP_MISR_TAMP3MF            TAMP_MISR_TAMP3MF_Msk
7473 #define TAMP_MISR_TAMP4MF_Pos        (3U)
7474 #define TAMP_MISR_TAMP4MF_Msk        (0x1UL << TAMP_MISR_TAMP4MF_Pos)          /*!< 0x00000004 */
7475 #define TAMP_MISR_TAMP4MF            TAMP_MISR_TAMP4MF_Msk
7476 #define TAMP_MISR_TAMP5MF_Pos        (4U)
7477 #define TAMP_MISR_TAMP5MF_Msk        (0x1UL << TAMP_MISR_TAMP5MF_Pos)          /*!< 0x00000004 */
7478 #define TAMP_MISR_TAMP5MF            TAMP_MISR_TAMP5MF_Msk
7479 #define TAMP_MISR_ITAMP3MF_Pos       (18U)
7480 #define TAMP_MISR_ITAMP3MF_Msk       (0x1UL << TAMP_MISR_ITAMP3MF_Pos)         /*!< 0x00040000 */
7481 #define TAMP_MISR_ITAMP3MF           TAMP_MISR_ITAMP3MF_Msk
7482 #define TAMP_MISR_ITAMP4MF_Pos       (19U)
7483 #define TAMP_MISR_ITAMP4MF_Msk       (0x1UL << TAMP_MISR_ITAMP4MF_Pos)         /*!< 0x00080000 */
7484 #define TAMP_MISR_ITAMP4MF           TAMP_MISR_ITAMP4MF_Msk
7485 #define TAMP_MISR_ITAMP5MF_Pos       (20U)
7486 #define TAMP_MISR_ITAMP5MF_Msk       (0x1UL << TAMP_MISR_ITAMP5MF_Pos)         /*!< 0x00100000 */
7487 #define TAMP_MISR_ITAMP5MF           TAMP_MISR_ITAMP5MF_Msk
7488 #define TAMP_MISR_ITAMP6MF_Pos       (21U)
7489 #define TAMP_MISR_ITAMP6MF_Msk       (0x1UL << TAMP_MISR_ITAMP6MF_Pos)         /*!< 0x00200000 */
7490 #define TAMP_MISR_ITAMP6MF           TAMP_MISR_ITAMP6MF_Msk
7491 
7492 /********************  Bits definition for TAMP_SCR register  *****************/
7493 #define TAMP_SCR_CTAMP1F_Pos         (0U)
7494 #define TAMP_SCR_CTAMP1F_Msk         (0x1UL << TAMP_SCR_CTAMP1F_Pos)            /*!< 0x00000001 */
7495 #define TAMP_SCR_CTAMP1F             TAMP_SCR_CTAMP1F_Msk
7496 #define TAMP_SCR_CTAMP2F_Pos         (1U)
7497 #define TAMP_SCR_CTAMP2F_Msk         (0x1UL << TAMP_SCR_CTAMP2F_Pos)            /*!< 0x00000002 */
7498 #define TAMP_SCR_CTAMP2F             TAMP_SCR_CTAMP2F_Msk
7499 #define TAMP_SCR_CTAMP3F_Pos         (2U)
7500 #define TAMP_SCR_CTAMP3F_Msk         (0x1UL << TAMP_SCR_CTAMP3F_Pos)           /*!< 0x00000004 */
7501 #define TAMP_SCR_CTAMP3F             TAMP_SCR_CTAMP3F_Msk
7502 #define TAMP_SCR_CTAMP4F_Pos         (3U)
7503 #define TAMP_SCR_CTAMP4F_Msk         (0x1UL << TAMP_SCR_CTAMP4F_Pos)           /*!< 0x00000004 */
7504 #define TAMP_SCR_CTAMP4F             TAMP_SCR_CTAMP4F_Msk
7505 #define TAMP_SCR_CTAMP5F_Pos         (4U)
7506 #define TAMP_SCR_CTAMP5F_Msk         (0x1UL << TAMP_SCR_CTAMP5F_Pos)           /*!< 0x00000004 */
7507 #define TAMP_SCR_CTAMP5F             TAMP_SCR_CTAMP5F_Msk
7508 #define TAMP_SCR_CITAMP3F_Pos        (18U)
7509 #define TAMP_SCR_CITAMP3F_Msk        (0x1UL << TAMP_SCR_CITAMP3F_Pos)          /*!< 0x00040000 */
7510 #define TAMP_SCR_CITAMP3F            TAMP_SCR_CITAMP3F_Msk
7511 #define TAMP_SCR_CITAMP4F_Pos        (19U)
7512 #define TAMP_SCR_CITAMP4F_Msk        (0x1UL << TAMP_SCR_CITAMP4F_Pos)          /*!< 0x00080000 */
7513 #define TAMP_SCR_CITAMP4F            TAMP_SCR_CITAMP4F_Msk
7514 #define TAMP_SCR_CITAMP5F_Pos        (20U)
7515 #define TAMP_SCR_CITAMP5F_Msk        (0x1UL << TAMP_SCR_CITAMP5F_Pos)          /*!< 0x00100000 */
7516 #define TAMP_SCR_CITAMP5F            TAMP_SCR_CITAMP5F_Msk
7517 #define TAMP_SCR_CITAMP6F_Pos        (21U)
7518 #define TAMP_SCR_CITAMP6F_Msk        (0x1UL << TAMP_SCR_CITAMP6F_Pos)          /*!< 0x00200000 */
7519 #define TAMP_SCR_CITAMP6F            TAMP_SCR_CITAMP6F_Msk
7520 
7521 /********************  Bits definition for TAMP_BKP0R register  ***************/
7522 #define TAMP_BKP0R_Pos               (0U)
7523 #define TAMP_BKP0R_Msk               (0xFFFFFFFFUL << TAMP_BKP0R_Pos)           /*!< 0xFFFFFFFF */
7524 #define TAMP_BKP0R                   TAMP_BKP0R_Msk
7525 
7526 /********************  Bits definition for TAMP_BKP1R register  ****************/
7527 #define TAMP_BKP1R_Pos               (0U)
7528 #define TAMP_BKP1R_Msk               (0xFFFFFFFFUL << TAMP_BKP1R_Pos)           /*!< 0xFFFFFFFF */
7529 #define TAMP_BKP1R                   TAMP_BKP1R_Msk
7530 
7531 /********************  Bits definition for TAMP_BKP2R register  ****************/
7532 #define TAMP_BKP2R_Pos               (0U)
7533 #define TAMP_BKP2R_Msk               (0xFFFFFFFFUL << TAMP_BKP2R_Pos)           /*!< 0xFFFFFFFF */
7534 #define TAMP_BKP2R                   TAMP_BKP2R_Msk
7535 
7536 /********************  Bits definition for TAMP_BKP3R register  ****************/
7537 #define TAMP_BKP3R_Pos               (0U)
7538 #define TAMP_BKP3R_Msk               (0xFFFFFFFFUL << TAMP_BKP3R_Pos)           /*!< 0xFFFFFFFF */
7539 #define TAMP_BKP3R                   TAMP_BKP3R_Msk
7540 
7541 /********************  Bits definition for TAMP_BKP4R register  ****************/
7542 #define TAMP_BKP4R_Pos               (0U)
7543 #define TAMP_BKP4R_Msk               (0xFFFFFFFFUL << TAMP_BKP4R_Pos)           /*!< 0xFFFFFFFF */
7544 #define TAMP_BKP4R                   TAMP_BKP4R_Msk
7545 
7546 /********************  Bits definition for TAMP_BKP5R register  ****************/
7547 #define TAMP_BKP5R_Pos               (0U)
7548 #define TAMP_BKP5R_Msk               (0xFFFFFFFFUL << TAMP_BKP5R_Pos)          /*!< 0xFFFFFFFF */
7549 #define TAMP_BKP5R                   TAMP_BKP5R_Msk
7550 
7551 /********************  Bits definition for TAMP_BKP6R register  ****************/
7552 #define TAMP_BKP6R_Pos               (0U)
7553 #define TAMP_BKP6R_Msk               (0xFFFFFFFFUL << TAMP_BKP6R_Pos)          /*!< 0xFFFFFFFF */
7554 #define TAMP_BKP6R                   TAMP_BKP6R_Msk
7555 
7556 /********************  Bits definition for TAMP_BKP7R register  ****************/
7557 #define TAMP_BKP7R_Pos               (0U)
7558 #define TAMP_BKP7R_Msk               (0xFFFFFFFFUL << TAMP_BKP7R_Pos)          /*!< 0xFFFFFFFF */
7559 #define TAMP_BKP7R                   TAMP_BKP7R_Msk
7560 
7561 /********************  Bits definition for TAMP_BKP8R register  ****************/
7562 #define TAMP_BKP8R_Pos               (0U)
7563 #define TAMP_BKP8R_Msk               (0xFFFFFFFFUL << TAMP_BKP8R_Pos)          /*!< 0xFFFFFFFF */
7564 #define TAMP_BKP8R                   TAMP_BKP8R_Msk
7565 
7566 /******************** Number of backup registers ******************************/
7567 #define TAMP_BKP_NUMBER_Pos             (4U)
7568 #define TAMP_BKP_NUMBER_Msk             (0x1UL << TAMP_BKP_NUMBER_Pos)         /*!< 0x00000080 */
7569 #define TAMP_BKP_NUMBER                 TAMP_BKP_NUMBER_Msk                    /*!< 9 BKPREG  */
7570 
7571 /******************************************************************************/
7572 /*                                                                            */
7573 /*                   Serial Peripheral Interface (SPI)                        */
7574 /*                                                                            */
7575 /******************************************************************************/
7576 /*
7577  * @brief Specific device feature definitions
7578  */
7579 
7580 /*******************  Bit definition for SPI_CR1 register  ********************/
7581 #define SPI_CR1_CPHA_Pos            (0U)
7582 #define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                /*!< 0x00000001 */
7583 #define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
7584 #define SPI_CR1_CPOL_Pos            (1U)
7585 #define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                /*!< 0x00000002 */
7586 #define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
7587 #define SPI_CR1_MSTR_Pos            (2U)
7588 #define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                /*!< 0x00000004 */
7589 #define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
7590 
7591 #define SPI_CR1_BR_Pos              (3U)
7592 #define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                  /*!< 0x00000038 */
7593 #define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
7594 #define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                  /*!< 0x00000008 */
7595 #define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                  /*!< 0x00000010 */
7596 #define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                  /*!< 0x00000020 */
7597 
7598 #define SPI_CR1_SPE_Pos             (6U)
7599 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000040 */
7600 #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
7601 #define SPI_CR1_LSBFIRST_Pos        (7U)
7602 #define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)            /*!< 0x00000080 */
7603 #define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
7604 #define SPI_CR1_SSI_Pos             (8U)
7605 #define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00000100 */
7606 #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
7607 #define SPI_CR1_SSM_Pos             (9U)
7608 #define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                 /*!< 0x00000200 */
7609 #define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
7610 #define SPI_CR1_RXONLY_Pos          (10U)
7611 #define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)              /*!< 0x00000400 */
7612 #define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
7613 #define SPI_CR1_CRCL_Pos            (11U)
7614 #define SPI_CR1_CRCL_Msk            (0x1UL << SPI_CR1_CRCL_Pos)                /*!< 0x00000800 */
7615 #define SPI_CR1_CRCL                SPI_CR1_CRCL_Msk                           /*!< CRC Length */
7616 #define SPI_CR1_CRCNEXT_Pos         (12U)
7617 #define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)             /*!< 0x00001000 */
7618 #define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
7619 #define SPI_CR1_CRCEN_Pos           (13U)
7620 #define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)               /*!< 0x00002000 */
7621 #define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
7622 #define SPI_CR1_BIDIOE_Pos          (14U)
7623 #define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)              /*!< 0x00004000 */
7624 #define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
7625 #define SPI_CR1_BIDIMODE_Pos        (15U)
7626 #define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)            /*!< 0x00008000 */
7627 #define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
7628 
7629 /*******************  Bit definition for SPI_CR2 register  ********************/
7630 #define SPI_CR2_RXDMAEN_Pos         (0U)
7631 #define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)             /*!< 0x00000001 */
7632 #define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
7633 #define SPI_CR2_TXDMAEN_Pos         (1U)
7634 #define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)             /*!< 0x00000002 */
7635 #define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
7636 #define SPI_CR2_SSOE_Pos            (2U)
7637 #define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                /*!< 0x00000004 */
7638 #define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
7639 #define SPI_CR2_NSSP_Pos            (3U)
7640 #define SPI_CR2_NSSP_Msk            (0x1UL << SPI_CR2_NSSP_Pos)                /*!< 0x00000008 */
7641 #define SPI_CR2_NSSP                SPI_CR2_NSSP_Msk                           /*!< NSS pulse management Enable */
7642 #define SPI_CR2_FRF_Pos             (4U)
7643 #define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                 /*!< 0x00000010 */
7644 #define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
7645 #define SPI_CR2_ERRIE_Pos           (5U)
7646 #define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)               /*!< 0x00000020 */
7647 #define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
7648 #define SPI_CR2_RXNEIE_Pos          (6U)
7649 #define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)              /*!< 0x00000040 */
7650 #define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
7651 #define SPI_CR2_TXEIE_Pos           (7U)
7652 #define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)               /*!< 0x00000080 */
7653 #define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
7654 #define SPI_CR2_DS_Pos              (8U)
7655 #define SPI_CR2_DS_Msk              (0xFUL << SPI_CR2_DS_Pos)                  /*!< 0x00000F00 */
7656 #define SPI_CR2_DS                  SPI_CR2_DS_Msk                             /*!< DS[3:0] Data Size */
7657 #define SPI_CR2_DS_0                (0x1UL << SPI_CR2_DS_Pos)                  /*!< 0x00000100 */
7658 #define SPI_CR2_DS_1                (0x2UL << SPI_CR2_DS_Pos)                  /*!< 0x00000200 */
7659 #define SPI_CR2_DS_2                (0x4UL << SPI_CR2_DS_Pos)                  /*!< 0x00000400 */
7660 #define SPI_CR2_DS_3                (0x8UL << SPI_CR2_DS_Pos)                  /*!< 0x00000800 */
7661 #define SPI_CR2_FRXTH_Pos           (12U)
7662 #define SPI_CR2_FRXTH_Msk           (0x1UL << SPI_CR2_FRXTH_Pos)               /*!< 0x00001000 */
7663 #define SPI_CR2_FRXTH               SPI_CR2_FRXTH_Msk                          /*!< FIFO reception Threshold */
7664 #define SPI_CR2_LDMARX_Pos          (13U)
7665 #define SPI_CR2_LDMARX_Msk          (0x1UL << SPI_CR2_LDMARX_Pos)              /*!< 0x00002000 */
7666 #define SPI_CR2_LDMARX              SPI_CR2_LDMARX_Msk                         /*!< Last DMA transfer for reception */
7667 #define SPI_CR2_LDMATX_Pos          (14U)
7668 #define SPI_CR2_LDMATX_Msk          (0x1UL << SPI_CR2_LDMATX_Pos)              /*!< 0x00004000 */
7669 #define SPI_CR2_LDMATX              SPI_CR2_LDMATX_Msk                         /*!< Last DMA transfer for transmission */
7670 
7671 /********************  Bit definition for SPI_SR register  ********************/
7672 #define SPI_SR_RXNE_Pos             (0U)
7673 #define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                 /*!< 0x00000001 */
7674 #define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
7675 #define SPI_SR_TXE_Pos              (1U)
7676 #define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                  /*!< 0x00000002 */
7677 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
7678 #define SPI_SR_CHSIDE_Pos           (2U)
7679 #define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)               /*!< 0x00000004 */
7680 #define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
7681 #define SPI_SR_UDR_Pos              (3U)
7682 #define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000008 */
7683 #define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
7684 #define SPI_SR_CRCERR_Pos           (4U)
7685 #define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)               /*!< 0x00000010 */
7686 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
7687 #define SPI_SR_MODF_Pos             (5U)
7688 #define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000020 */
7689 #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
7690 #define SPI_SR_OVR_Pos              (6U)
7691 #define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */
7692 #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
7693 #define SPI_SR_BSY_Pos              (7U)
7694 #define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                  /*!< 0x00000080 */
7695 #define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
7696 #define SPI_SR_FRE_Pos              (8U)
7697 #define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                  /*!< 0x00000100 */
7698 #define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */
7699 #define SPI_SR_FRLVL_Pos            (9U)
7700 #define SPI_SR_FRLVL_Msk            (0x3UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000600 */
7701 #define SPI_SR_FRLVL                SPI_SR_FRLVL_Msk                           /*!< FIFO Reception Level */
7702 #define SPI_SR_FRLVL_0              (0x1UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000200 */
7703 #define SPI_SR_FRLVL_1              (0x2UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000400 */
7704 #define SPI_SR_FTLVL_Pos            (11U)
7705 #define SPI_SR_FTLVL_Msk            (0x3UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001800 */
7706 #define SPI_SR_FTLVL                SPI_SR_FTLVL_Msk                           /*!< FIFO Transmission Level */
7707 #define SPI_SR_FTLVL_0              (0x1UL << SPI_SR_FTLVL_Pos)                /*!< 0x00000800 */
7708 #define SPI_SR_FTLVL_1              (0x2UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001000 */
7709 
7710 /********************  Bit definition for SPI_DR register  ********************/
7711 #define SPI_DR_DR_Pos               (0U)
7712 #define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                /*!< 0x0000FFFF */
7713 #define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
7714 
7715 /*******************  Bit definition for SPI_CRCPR register  ******************/
7716 #define SPI_CRCPR_CRCPOLY_Pos       (0U)
7717 #define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)        /*!< 0x0000FFFF */
7718 #define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
7719 
7720 /******************  Bit definition for SPI_RXCRCR register  ******************/
7721 #define SPI_RXCRCR_RXCRC_Pos        (0U)
7722 #define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)         /*!< 0x0000FFFF */
7723 #define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
7724 
7725 /******************  Bit definition for SPI_TXCRCR register  ******************/
7726 #define SPI_TXCRCR_TXCRC_Pos        (0U)
7727 #define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)         /*!< 0x0000FFFF */
7728 #define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
7729 
7730 /******************************************************************************/
7731 /*                                                                            */
7732 /*                                 SYSCFG                                     */
7733 /*                                                                            */
7734 /******************************************************************************/
7735 
7736 /******************  Bit definition for SYSCFG_CFGR1 register  ******************/
7737 #define SYSCFG_CFGR1_MEM_MODE_Pos       (0U)
7738 #define SYSCFG_CFGR1_MEM_MODE_Msk       (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos)     /*!< 0x00000003 */
7739 #define SYSCFG_CFGR1_MEM_MODE           SYSCFG_CFGR1_MEM_MODE_Msk                /*!< SYSCFG_Memory Remap Config */
7740 #define SYSCFG_CFGR1_MEM_MODE_0         (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos)     /*!< 0x00000001 */
7741 #define SYSCFG_CFGR1_MEM_MODE_1         (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos)     /*!< 0x00000002 */
7742 #define SYSCFG_CFGR1_PA11_RMP_Pos       (3U)
7743 #define SYSCFG_CFGR1_PA11_RMP_Msk       (0x1UL << SYSCFG_CFGR1_PA11_RMP_Pos)     /*!< 0x00000008 */
7744 #define SYSCFG_CFGR1_PA11_RMP           SYSCFG_CFGR1_PA11_RMP_Msk                /*!< PA11 Remap */
7745 #define SYSCFG_CFGR1_PA12_RMP_Pos       (4U)
7746 #define SYSCFG_CFGR1_PA12_RMP_Msk       (0x1UL << SYSCFG_CFGR1_PA12_RMP_Pos)     /*!< 0x00000010 */
7747 #define SYSCFG_CFGR1_PA12_RMP           SYSCFG_CFGR1_PA12_RMP_Msk                /*!< PA12 Remap */
7748 #define SYSCFG_CFGR1_IR_POL_Pos         (5U)
7749 #define SYSCFG_CFGR1_IR_POL_Msk         (0x1UL << SYSCFG_CFGR1_IR_POL_Pos)       /*!< 0x00000020 */
7750 #define SYSCFG_CFGR1_IR_POL             SYSCFG_CFGR1_IR_POL_Msk                  /*!< IROut Polarity Selection */
7751 #define SYSCFG_CFGR1_IR_MOD_Pos         (6U)
7752 #define SYSCFG_CFGR1_IR_MOD_Msk         (0x3UL << SYSCFG_CFGR1_IR_MOD_Pos)       /*!< 0x000000C0 */
7753 #define SYSCFG_CFGR1_IR_MOD             SYSCFG_CFGR1_IR_MOD_Msk                  /*!< IRDA Modulation Envelope signal source selection */
7754 #define SYSCFG_CFGR1_IR_MOD_0           (0x1UL << SYSCFG_CFGR1_IR_MOD_Pos)       /*!< 0x00000040 */
7755 #define SYSCFG_CFGR1_IR_MOD_1           (0x2UL << SYSCFG_CFGR1_IR_MOD_Pos)       /*!< 0x00000080 */
7756 #define SYSCFG_CFGR1_BOOSTEN_Pos        (8U)
7757 #define SYSCFG_CFGR1_BOOSTEN_Msk        (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)      /*!< 0x00000100 */
7758 #define SYSCFG_CFGR1_BOOSTEN            SYSCFG_CFGR1_BOOSTEN_Msk                 /*!< I/O analog switch voltage booster enable */
7759 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos    (16U)
7760 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)  /*!< 0x00010000 */
7761 #define SYSCFG_CFGR1_I2C_PB6_FMP        SYSCFG_CFGR1_I2C_PB6_FMP_Msk             /*!< I2C PB6 Fast mode plus */
7762 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos    (17U)
7763 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)  /*!< 0x00020000 */
7764 #define SYSCFG_CFGR1_I2C_PB7_FMP        SYSCFG_CFGR1_I2C_PB7_FMP_Msk             /*!< I2C PB7 Fast mode plus */
7765 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos    (18U)
7766 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)  /*!< 0x00040000 */
7767 #define SYSCFG_CFGR1_I2C_PB8_FMP        SYSCFG_CFGR1_I2C_PB8_FMP_Msk             /*!< I2C PB8 Fast mode plus */
7768 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos    (19U)
7769 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)  /*!< 0x00080000 */
7770 #define SYSCFG_CFGR1_I2C_PB9_FMP        SYSCFG_CFGR1_I2C_PB9_FMP_Msk             /*!< I2C PB9 Fast mode plus */
7771 #define SYSCFG_CFGR1_I2C_PA9_FMP_Pos    (22U)
7772 #define SYSCFG_CFGR1_I2C_PA9_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PA9_FMP_Pos)  /*!< 0x00400000 */
7773 #define SYSCFG_CFGR1_I2C_PA9_FMP        SYSCFG_CFGR1_I2C_PA9_FMP_Msk             /*!< Enable Fast Mode Plus on PA9  */
7774 #define SYSCFG_CFGR1_I2C_PA10_FMP_Pos   (23U)
7775 #define SYSCFG_CFGR1_I2C_PA10_FMP_Msk   (0x1UL << SYSCFG_CFGR1_I2C_PA10_FMP_Pos) /*!< 0x00800000 */
7776 #define SYSCFG_CFGR1_I2C_PA10_FMP       SYSCFG_CFGR1_I2C_PA10_FMP_Msk            /*!< Enable Fast Mode Plus on PA10 */
7777 #define SYSCFG_CFGR1_I2C3_FMP_Pos       (24U)
7778 #define SYSCFG_CFGR1_I2C3_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)     /*!< 0x01000000 */
7779 #define SYSCFG_CFGR1_I2C3_FMP           SYSCFG_CFGR1_I2C3_FMP_Msk                /*!< Enable Fast Mode Plus for I2C3 */
7780 
7781 /******************  Bit definition for SYSCFG_CFGR2 register  ****************/
7782 #define SYSCFG_CFGR2_CCL_Pos            (0U)
7783 #define SYSCFG_CFGR2_CCL_Msk            (0x1UL << SYSCFG_CFGR2_CCL_Pos)         /*!< 0x00000001 */
7784 #define SYSCFG_CFGR2_CCL                SYSCFG_CFGR2_CCL_Msk                    /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input */
7785 #define SYSCFG_CFGR2_SPL_Pos            (1U)
7786 #define SYSCFG_CFGR2_SPL_Msk            (0x1UL << SYSCFG_CFGR2_SPL_Pos)         /*!< 0x00000002 */
7787 #define SYSCFG_CFGR2_SPL                SYSCFG_CFGR2_SPL_Msk                    /*!< Enables and locks the SRAM Parity error signal with TIMERs Break Input */
7788 #define SYSCFG_CFGR2_PVDL_Pos           (2U)
7789 #define SYSCFG_CFGR2_PVDL_Msk           (0x1UL << SYSCFG_CFGR2_PVDL_Pos)        /*!< 0x00000004 */
7790 #define SYSCFG_CFGR2_PVDL               SYSCFG_CFGR2_PVDL_Msk                   /*!< Enables and locks the PVD connection with TIMERs Break Input */
7791 #define SYSCFG_CFGR2_ECCL_Pos           (3U)
7792 #define SYSCFG_CFGR2_ECCL_Msk           (0x1UL << SYSCFG_CFGR2_ECCL_Pos)        /*!< 0x00000008 */
7793 #define SYSCFG_CFGR2_ECCL               SYSCFG_CFGR2_ECCL_Msk                   /*!< Enables and locks the FLASH ECC error with TIMERs Break Input */
7794 #define SYSCFG_CFGR2_BKPL_Pos           (4U)
7795 #define SYSCFG_CFGR2_BKPL_Msk           (0x1UL << SYSCFG_CFGR2_BKPL_Pos)        /*!< 0x00000010 */
7796 #define SYSCFG_CFGR2_BKPL               SYSCFG_CFGR2_BKPL_Msk                   /*!< Enables and locks the BackUp SRAM Parity error signal with TIMERs Break Input */
7797 #define SYSCFG_CFGR2_BKPF_Pos           (7U)
7798 #define SYSCFG_CFGR2_BKPF_Msk           (0x1UL << SYSCFG_CFGR2_BKPF_Pos)        /*!< 0x00000080 */
7799 #define SYSCFG_CFGR2_BKPF               SYSCFG_CFGR2_BKPF_Msk                   /*!< Saves the occurrence of the BackUpSRAM Parity Error */
7800 #define SYSCFG_CFGR2_SPF_Pos            (8U)
7801 #define SYSCFG_CFGR2_SPF_Msk            (0x1UL << SYSCFG_CFGR2_SPF_Pos)         /*!< 0x00000100 */
7802 #define SYSCFG_CFGR2_SPF                SYSCFG_CFGR2_SPF_Msk                    /*!< Saves the occurrence of the SRAM Parity Error */
7803 
7804 /******************  Bit definition for SYSCFG_SCSR register  ****************/
7805 #define SYSCFG_SCSR_SRAM2ER_Pos         (0U)
7806 #define SYSCFG_SCSR_SRAM2ER_Msk         (0x1UL << SYSCFG_SCSR_SRAM2ER_Pos)       /*!< 0x00000001 */
7807 #define SYSCFG_SCSR_SRAM2ER             SYSCFG_SCSR_SRAM2ER_Msk                  /*!< Starts a hardware BackUpSRAM erase operation */
7808 #define SYSCFG_SCSR_SRAM2BSY_Pos        (1U)
7809 #define SYSCFG_SCSR_SRAM2BSY_Msk        (0x1UL << SYSCFG_SCSR_SRAM2BSY_Pos)      /*!< 0x00000002 */
7810 #define SYSCFG_SCSR_SRAM2BSY            SYSCFG_SCSR_SRAM2BSY_Msk                 /*!< BackUpSRAM Erase Ongoing Status Flag*/
7811 
7812 /******************  Bit definition for SYSCFG_SER register  ****************/
7813 #define SYSCFG_SKR_KEY_Pos              (0U)
7814 #define SYSCFG_SKR_KEY_Msk              (0xFFUL << SYSCFG_SKR_KEY_Pos)           /*!< 0x000000FF */
7815 #define SYSCFG_SKR_KEY                  SYSCFG_SKR_KEY_Msk                       /*!< Write BackUpSRAM Key for software erase */
7816 
7817 /******************  Bit definition for SYSCFG_TSCCR register  ****************/
7818 #define SYSCFG_TSCCR_G2IO1_Pos          (0U)
7819 #define SYSCFG_TSCCR_G2IO1_Msk          (0x1UL << SYSCFG_TSCCR_G2IO1_Pos)         /*!< 0x00000001 */
7820 #define SYSCFG_TSCCR_G2IO1              SYSCFG_TSCCR_G2IO1_Msk                    /*!< Enable the comparator mode with the IO1 of Group2 (PB4 on INPLUS of COMP2) */
7821 #define SYSCFG_TSCCR_G2IO3_Pos          (1U)
7822 #define SYSCFG_TSCCR_G2IO3_Msk          (0x1UL << SYSCFG_TSCCR_G2IO3_Pos)         /*!< 0x00000002 */
7823 #define SYSCFG_TSCCR_G2IO3              SYSCFG_TSCCR_G2IO3_Msk                    /*!< Enable the comparator mode with the IO3 of Group2 (PB6 on INPLUS of COMP2) */
7824 #define SYSCFG_TSCCR_G4IO1_Pos          (2U)
7825 #define SYSCFG_TSCCR_G4IO1_Msk          (0x1UL << SYSCFG_TSCCR_G4IO1_Pos)         /*!< 0x00000004 */
7826 #define SYSCFG_TSCCR_G4IO1              SYSCFG_TSCCR_G4IO1_Msk                    /*!< Enable the comparator mode with the IO1 of Group4 (PC6 on INPLUS of COMP1) */
7827 #define SYSCFG_TSCCR_G6IO1_Pos          (3U)
7828 #define SYSCFG_TSCCR_G6IO1_Msk          (0x1UL << SYSCFG_TSCCR_G6IO1_Pos)         /*!< 0x00000008 */
7829 #define SYSCFG_TSCCR_G6IO1              SYSCFG_TSCCR_G6IO1_Msk                    /*!< Enable the comparator mode with the IO1 of Group6 (PD10 on INPLUS of COMP2) */
7830 #define SYSCFG_TSCCR_G7IO2_Pos          (4U)
7831 #define SYSCFG_TSCCR_G7IO2_Msk          (0x1UL << SYSCFG_TSCCR_G7IO2_Pos)         /*!< 0x00000010 */
7832 #define SYSCFG_TSCCR_G7IO2              SYSCFG_TSCCR_G7IO2_Msk                    /*!< Enable the comparator mode with the IO2 of Group7 (PA9 on INPLUS of COMP1) */
7833 #define SYSCFG_TSCCR_TSCIOCTRL_Pos      (5U)
7834 #define SYSCFG_TSCCR_TSCIOCTRL_Msk      (0x1UL << SYSCFG_TSCCR_TSCIOCTRL_Pos)     /*!< 0x00000020 */
7835 #define SYSCFG_TSCCR_TSCIOCTRL          SYSCFG_TSCCR_TSCIOCTRL_Msk                /*!< Program Comparator mode (programmed via alternate function) */
7836 
7837 /*****************  Bit definition for SYSCFG_ITLINEx ISR Wrapper register  ****************/
7838 #define SYSCFG_ITLINE0_SR_WWDG_Pos         (0U)
7839 #define SYSCFG_ITLINE0_SR_WWDG_Msk         (0x1UL << SYSCFG_ITLINE0_SR_WWDG_Pos)       /*!< 0x00000001 */
7840 #define SYSCFG_ITLINE0_SR_WWDG             SYSCFG_ITLINE0_SR_WWDG_Msk                  /*!< WWDG interrupt */
7841 
7842 #define SYSCFG_ITLINE1_SR_PVDOUT_Pos       (0U)
7843 #define SYSCFG_ITLINE1_SR_PVDOUT_Msk       (0x1UL << SYSCFG_ITLINE1_SR_PVDOUT_Pos)     /*!< 0x00000001 */
7844 #define SYSCFG_ITLINE1_SR_PVDOUT           SYSCFG_ITLINE1_SR_PVDOUT_Msk                /*!< PVDOUT interrupt */
7845 #define SYSCFG_ITLINE1_SR_PVMOUT1_Pos      (1U)
7846 #define SYSCFG_ITLINE1_SR_PVMOUT1_Msk      (0x1UL << SYSCFG_ITLINE1_SR_PVMOUT1_Pos)    /*!< 0x00000002 */
7847 #define SYSCFG_ITLINE1_SR_PVMOUT1          SYSCFG_ITLINE1_SR_PVMOUT1_Msk               /*!< VDDUSB interrupt */
7848 #define SYSCFG_ITLINE1_SR_PVMOUT3_Pos      (2U)
7849 #define SYSCFG_ITLINE1_SR_PVMOUT3_Msk      (0x1UL << SYSCFG_ITLINE1_SR_PVMOUT3_Pos)    /*!< 0x00000004 */
7850 #define SYSCFG_ITLINE1_SR_PVMOUT3          SYSCFG_ITLINE1_SR_PVMOUT3_Msk               /*!< VDDADC interrupt */
7851 #define SYSCFG_ITLINE1_SR_PVMOUT4_Pos      (3)
7852 #define SYSCFG_ITLINE1_SR_PVMOUT4_Msk      (0x1UL << SYSCFG_ITLINE1_SR_PVMOUT4_Pos)    /*!< 0x00000008 */
7853 #define SYSCFG_ITLINE1_SR_PVMOUT4          SYSCFG_ITLINE1_SR_PVMOUT4_Msk               /*!< VDDADC interrupt */
7854 
7855 #define SYSCFG_ITLINE2_SR_TAMPER_Pos       (0U)
7856 #define SYSCFG_ITLINE2_SR_TAMPER_Msk       (0x1UL << SYSCFG_ITLINE2_SR_TAMPER_Pos)     /*!< 0x00000001 */
7857 #define SYSCFG_ITLINE2_SR_TAMPER           SYSCFG_ITLINE2_SR_TAMPER_Msk                /*!< TAMPER interrupt */
7858 #define SYSCFG_ITLINE2_SR_RTC_Pos          (1U)
7859 #define SYSCFG_ITLINE2_SR_RTC_Msk          (0x1UL << SYSCFG_ITLINE2_SR_RTC_Pos)        /*!< 0x00000001 */
7860 #define SYSCFG_ITLINE2_SR_RTC              SYSCFG_ITLINE2_SR_RTC_Msk                   /*!< RTC interrupt */
7861 
7862 #define SYSCFG_ITLINE3_SR_FLASH_ECC_Pos    (0U)
7863 #define SYSCFG_ITLINE3_SR_FLASH_ECC_Msk    (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ECC_Pos)  /*!< 0x00000001 */
7864 #define SYSCFG_ITLINE3_SR_FLASH_ECC        SYSCFG_ITLINE3_SR_FLASH_ECC_Msk             /*!< FLASH ECC interrupt */
7865 #define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos    (1U)
7866 #define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk    (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos)  /*!< 0x00000002 */
7867 #define SYSCFG_ITLINE3_SR_FLASH_ITF        SYSCFG_ITLINE3_SR_FLASH_ITF_Msk             /*!< FLASH ITF interrupt */
7868 
7869 #define SYSCFG_ITLINE4_SR_RCC_Pos          (0U)
7870 #define SYSCFG_ITLINE4_SR_RCC_Msk          (0x1UL << SYSCFG_ITLINE4_SR_RCC_Pos)        /*!< 0x00000001 */
7871 #define SYSCFG_ITLINE4_SR_RCC              SYSCFG_ITLINE4_SR_RCC_Msk                   /*!< RCC interrupt */
7872 #define SYSCFG_ITLINE4_SR_CRS_Pos          (1U)
7873 #define SYSCFG_ITLINE4_SR_CRS_Msk          (0x1UL << SYSCFG_ITLINE4_SR_CRS_Pos)        /*!< 0x00000002 */
7874 #define SYSCFG_ITLINE4_SR_CRS              SYSCFG_ITLINE4_SR_CRS_Msk                   /*!< CRS interrupt */
7875 #define SYSCFG_ITLINE5_SR_EXTI0_Pos        (0U)
7876 #define SYSCFG_ITLINE5_SR_EXTI0_Msk        (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos)      /*!< 0x00000001 */
7877 #define SYSCFG_ITLINE5_SR_EXTI0            SYSCFG_ITLINE5_SR_EXTI0_Msk                 /*!< External Interrupt 0 */
7878 #define SYSCFG_ITLINE5_SR_EXTI1_Pos        (1U)
7879 #define SYSCFG_ITLINE5_SR_EXTI1_Msk        (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos)      /*!< 0x00000002 */
7880 #define SYSCFG_ITLINE5_SR_EXTI1            SYSCFG_ITLINE5_SR_EXTI1_Msk                 /*!< External Interrupt 1 */
7881 
7882 #define SYSCFG_ITLINE6_SR_EXTI2_Pos        (0U)
7883 #define SYSCFG_ITLINE6_SR_EXTI2_Msk        (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos)      /*!< 0x00000001 */
7884 #define SYSCFG_ITLINE6_SR_EXTI2            SYSCFG_ITLINE6_SR_EXTI2_Msk                 /*!< External Interrupt 2 */
7885 #define SYSCFG_ITLINE6_SR_EXTI3_Pos        (1U)
7886 #define SYSCFG_ITLINE6_SR_EXTI3_Msk        (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos)      /*!< 0x00000002 */
7887 #define SYSCFG_ITLINE6_SR_EXTI3            SYSCFG_ITLINE6_SR_EXTI3_Msk                 /*!< External Interrupt 3 */
7888 
7889 #define SYSCFG_ITLINE7_SR_EXTI4_Pos        (0U)
7890 #define SYSCFG_ITLINE7_SR_EXTI4_Msk        (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos)      /*!< 0x00000001 */
7891 #define SYSCFG_ITLINE7_SR_EXTI4            SYSCFG_ITLINE7_SR_EXTI4_Msk                 /*!< External Interrupt 4 */
7892 #define SYSCFG_ITLINE7_SR_EXTI5_Pos        (1U)
7893 #define SYSCFG_ITLINE7_SR_EXTI5_Msk        (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos)      /*!< 0x00000002 */
7894 #define SYSCFG_ITLINE7_SR_EXTI5            SYSCFG_ITLINE7_SR_EXTI5_Msk                 /*!< External Interrupt 5 */
7895 #define SYSCFG_ITLINE7_SR_EXTI6_Pos        (2U)
7896 #define SYSCFG_ITLINE7_SR_EXTI6_Msk        (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos)      /*!< 0x00000004 */
7897 #define SYSCFG_ITLINE7_SR_EXTI6            SYSCFG_ITLINE7_SR_EXTI6_Msk                 /*!< External Interrupt 6 */
7898 #define SYSCFG_ITLINE7_SR_EXTI7_Pos        (3U)
7899 #define SYSCFG_ITLINE7_SR_EXTI7_Msk        (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos)      /*!< 0x00000008 */
7900 #define SYSCFG_ITLINE7_SR_EXTI7            SYSCFG_ITLINE7_SR_EXTI7_Msk                 /*!< External Interrupt 7 */
7901 #define SYSCFG_ITLINE7_SR_EXTI8_Pos        (4U)
7902 #define SYSCFG_ITLINE7_SR_EXTI8_Msk        (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos)      /*!< 0x00000010 */
7903 #define SYSCFG_ITLINE7_SR_EXTI8            SYSCFG_ITLINE7_SR_EXTI8_Msk                 /*!< External Interrupt 8 */
7904 #define SYSCFG_ITLINE7_SR_EXTI9_Pos        (5U)
7905 #define SYSCFG_ITLINE7_SR_EXTI9_Msk        (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos)      /*!< 0x00000020 */
7906 #define SYSCFG_ITLINE7_SR_EXTI9            SYSCFG_ITLINE7_SR_EXTI9_Msk                 /*!< External Interrupt 9 */
7907 #define SYSCFG_ITLINE7_SR_EXTI10_Pos       (6U)
7908 #define SYSCFG_ITLINE7_SR_EXTI10_Msk       (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos)     /*!< 0x00000040 */
7909 #define SYSCFG_ITLINE7_SR_EXTI10           SYSCFG_ITLINE7_SR_EXTI10_Msk                /*!< External Interrupt 10 */
7910 #define SYSCFG_ITLINE7_SR_EXTI11_Pos       (7U)
7911 #define SYSCFG_ITLINE7_SR_EXTI11_Msk       (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos)     /*!< 0x00000080 */
7912 #define SYSCFG_ITLINE7_SR_EXTI11           SYSCFG_ITLINE7_SR_EXTI11_Msk                /*!< External Interrupt 11 */
7913 #define SYSCFG_ITLINE7_SR_EXTI12_Pos       (8U)
7914 #define SYSCFG_ITLINE7_SR_EXTI12_Msk       (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos)     /*!< 0x00000100 */
7915 #define SYSCFG_ITLINE7_SR_EXTI12           SYSCFG_ITLINE7_SR_EXTI12_Msk                /*!< External Interrupt 12 */
7916 #define SYSCFG_ITLINE7_SR_EXTI13_Pos       (9U)
7917 #define SYSCFG_ITLINE7_SR_EXTI13_Msk       (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos)     /*!< 0x00000200 */
7918 #define SYSCFG_ITLINE7_SR_EXTI13           SYSCFG_ITLINE7_SR_EXTI13_Msk                /*!< External Interrupt 13 */
7919 #define SYSCFG_ITLINE7_SR_EXTI14_Pos       (10U)
7920 #define SYSCFG_ITLINE7_SR_EXTI14_Msk       (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos)     /*!< 0x00000400 */
7921 #define SYSCFG_ITLINE7_SR_EXTI14           SYSCFG_ITLINE7_SR_EXTI14_Msk                /*!< External Interrupt 14 */
7922 #define SYSCFG_ITLINE7_SR_EXTI15_Pos       (11U)
7923 #define SYSCFG_ITLINE7_SR_EXTI15_Msk       (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos)     /*!< 0x00000800 */
7924 #define SYSCFG_ITLINE7_SR_EXTI15           SYSCFG_ITLINE7_SR_EXTI15_Msk                /*!< External Interrupt 15 */
7925 
7926 #define SYSCFG_ITLINE8_SR_USBFS_Pos        (0U)
7927 #define SYSCFG_ITLINE8_SR_USBFS_Msk        (0x1UL << SYSCFG_ITLINE8_SR_USBFS_Pos)      /*!< 0x00000001 */
7928 #define SYSCFG_ITLINE8_SR_USBFS            SYSCFG_ITLINE8_SR_USBFS_Msk                 /*!< USBFS Interrupt */
7929 
7930 #define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos     (0U)
7931 #define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk     (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos)   /*!< 0x00000001 */
7932 #define SYSCFG_ITLINE9_SR_DMA1_CH1         SYSCFG_ITLINE9_SR_DMA1_CH1_Msk              /*!< DMA1 Channel 1 Interrupt */
7933 
7934 #define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos    (0U)
7935 #define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk    (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos)  /*!< 0x00000001 */
7936 #define SYSCFG_ITLINE10_SR_DMA1_CH2        SYSCFG_ITLINE10_SR_DMA1_CH2_Msk             /*!< DMA1 Channel 2 Interrupt */
7937 #define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos    (1U)
7938 #define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk    (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos)  /*!< 0x00000002 */
7939 #define SYSCFG_ITLINE10_SR_DMA1_CH3        SYSCFG_ITLINE10_SR_DMA1_CH3_Msk             /*!< DMA1 Channel 3 Interrupt */
7940 
7941 #define SYSCFG_ITLINE11_SR_DMAMUX_Pos      (0U)
7942 #define SYSCFG_ITLINE11_SR_DMAMUX_Msk      (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX_Pos)    /*!< 0x00000001 */
7943 #define SYSCFG_ITLINE11_SR_DMAMUX          SYSCFG_ITLINE11_SR_DMAMUX_Msk               /*!< DMAMUX Interrupt */
7944 #define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos    (1U)
7945 #define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk    (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos)  /*!< 0x00000002 */
7946 #define SYSCFG_ITLINE11_SR_DMA1_CH4        SYSCFG_ITLINE11_SR_DMA1_CH4_Msk             /*!< DMA1 Channel 4 Interrupt */
7947 #define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos    (2U)
7948 #define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk    (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos)  /*!< 0x00000004 */
7949 #define SYSCFG_ITLINE11_SR_DMA1_CH5        SYSCFG_ITLINE11_SR_DMA1_CH5_Msk             /*!< DMA1 Channel 5 Interrupt */
7950 #define SYSCFG_ITLINE11_SR_DMA1_CH6_Pos    (3U)
7951 #define SYSCFG_ITLINE11_SR_DMA1_CH6_Msk    (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH6_Pos)  /*!< 0x00000008 */
7952 #define SYSCFG_ITLINE11_SR_DMA1_CH6        SYSCFG_ITLINE11_SR_DMA1_CH6_Msk             /*!< DMA1 Channel 6 Interrupt */
7953 #define SYSCFG_ITLINE11_SR_DMA1_CH7_Pos    (4U)
7954 #define SYSCFG_ITLINE11_SR_DMA1_CH7_Msk    (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH7_Pos)  /*!< 0x00000010 */
7955 #define SYSCFG_ITLINE11_SR_DMA1_CH7        SYSCFG_ITLINE11_SR_DMA1_CH7_Msk             /*!< DMA1 Channel 7 Interrupt */
7956 #define SYSCFG_ITLINE11_SR_DMA2_CH1_Pos    (5U)
7957 #define SYSCFG_ITLINE11_SR_DMA2_CH1_Msk    (0x1UL << SYSCFG_ITLINE11_SR_DMA2_CH1_Pos)  /*!< 0x00000020 */
7958 #define SYSCFG_ITLINE11_SR_DMA2_CH1        SYSCFG_ITLINE11_SR_DMA2_CH1_Msk             /*!< DMA1 Channel 8 Interrupt */
7959 #define SYSCFG_ITLINE11_SR_DMA2_CH2_Pos    (6U)
7960 #define SYSCFG_ITLINE11_SR_DMA2_CH2_Msk    (0x1UL << SYSCFG_ITLINE11_SR_DMA2_CH2_Pos)  /*!< 0x00000040 */
7961 #define SYSCFG_ITLINE11_SR_DMA2_CH2        SYSCFG_ITLINE11_SR_DMA2_CH2_Msk             /*!< DMA1 Channel 9 Interrupt */
7962 #define SYSCFG_ITLINE11_SR_DMA2_CH3_Pos    (7U)
7963 #define SYSCFG_ITLINE11_SR_DMA2_CH3_Msk    (0x1UL << SYSCFG_ITLINE11_SR_DMA2_CH3_Pos)  /*!< 0x00000080 */
7964 #define SYSCFG_ITLINE11_SR_DMA2_CH3        SYSCFG_ITLINE11_SR_DMA2_CH3_Msk             /*!< DMA1 Channel 10 Interrupt */
7965 #define SYSCFG_ITLINE11_SR_DMA2_CH4_Pos    (8U)
7966 #define SYSCFG_ITLINE11_SR_DMA2_CH4_Msk    (0x1UL << SYSCFG_ITLINE11_SR_DMA2_CH4_Pos)  /*!< 0x00000100 */
7967 #define SYSCFG_ITLINE11_SR_DMA2_CH4        SYSCFG_ITLINE11_SR_DMA2_CH4_Msk             /*!< DMA1 Channel 11 Interrupt */
7968 #define SYSCFG_ITLINE11_SR_DMA2_CH5_Pos    (9U)
7969 #define SYSCFG_ITLINE11_SR_DMA2_CH5_Msk    (0x1UL << SYSCFG_ITLINE11_SR_DMA2_CH5_Pos)  /*!< 0x00000200 */
7970 #define SYSCFG_ITLINE11_SR_DMA2_CH5        SYSCFG_ITLINE11_SR_DMA2_CH5_Msk             /*!< DMA1 Channel 12 Interrupt */
7971 
7972 #define SYSCFG_ITLINE12_SR_ADC_Pos         (0U)
7973 #define SYSCFG_ITLINE12_SR_ADC_Msk         (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos)       /*!< 0x00000001 */
7974 #define SYSCFG_ITLINE12_SR_ADC             SYSCFG_ITLINE12_SR_ADC_Msk                  /*!< ADC Interrupt */
7975 #define SYSCFG_ITLINE12_SR_COMP1_Pos       (1U)
7976 #define SYSCFG_ITLINE12_SR_COMP1_Msk       (0x1UL << SYSCFG_ITLINE12_SR_COMP1_Pos)     /*!< 0x00000002 */
7977 #define SYSCFG_ITLINE12_SR_COMP1           SYSCFG_ITLINE12_SR_COMP1_Msk                /*!< COMP1 Interrupt -> exti[17] */
7978 #define SYSCFG_ITLINE12_SR_COMP2_Pos       (2U)
7979 #define SYSCFG_ITLINE12_SR_COMP2_Msk       (0x1UL << SYSCFG_ITLINE12_SR_COMP2_Pos)     /*!< 0x00000004 */
7980 #define SYSCFG_ITLINE12_SR_COMP2           SYSCFG_ITLINE12_SR_COMP2_Msk                /*!< COMP2 Interrupt -> exti[18] */
7981 
7982 #define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos    (0U)
7983 #define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk    (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos)  /*!< 0x00000001 */
7984 #define SYSCFG_ITLINE13_SR_TIM1_CCU        SYSCFG_ITLINE13_SR_TIM1_CCU_Msk             /*!< TIM1 CCU Interrupt */
7985 #define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos    (1U)
7986 #define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk    (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos)  /*!< 0x00000002 */
7987 #define SYSCFG_ITLINE13_SR_TIM1_TRG        SYSCFG_ITLINE13_SR_TIM1_TRG_Msk             /*!< TIM1 TRG Interrupt */
7988 #define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos    (2U)
7989 #define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk    (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos)  /*!< 0x00000004 */
7990 #define SYSCFG_ITLINE13_SR_TIM1_UPD        SYSCFG_ITLINE13_SR_TIM1_UPD_Msk             /*!< TIM1 UPD Interrupt */
7991 #define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos    (3U)
7992 #define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk    (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos)  /*!< 0x00000008 */
7993 #define SYSCFG_ITLINE13_SR_TIM1_BRK        SYSCFG_ITLINE13_SR_TIM1_BRK_Msk             /*!< TIM1 BRK Interrupt */
7994 
7995 #define SYSCFG_ITLINE14_SR_TIM1_CC1_Pos    (0U)
7996 #define SYSCFG_ITLINE14_SR_TIM1_CC1_Msk    (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC1_Pos)  /*!< 0x00000001 */
7997 #define SYSCFG_ITLINE14_SR_TIM1_CC1        SYSCFG_ITLINE14_SR_TIM1_CC1_Msk             /*!< TIM1 CC1 Interrupt */
7998 #define SYSCFG_ITLINE14_SR_TIM1_CC2_Pos    (1U)
7999 #define SYSCFG_ITLINE14_SR_TIM1_CC2_Msk    (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC2_Pos)  /*!< 0x00000002 */
8000 #define SYSCFG_ITLINE14_SR_TIM1_CC2        SYSCFG_ITLINE14_SR_TIM1_CC2_Msk             /*!< TIM1 CC2 Interrupt */
8001 #define SYSCFG_ITLINE14_SR_TIM1_CC3_Pos    (2U)
8002 #define SYSCFG_ITLINE14_SR_TIM1_CC3_Msk    (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC3_Pos)  /*!< 0x00000004 */
8003 #define SYSCFG_ITLINE14_SR_TIM1_CC3        SYSCFG_ITLINE14_SR_TIM1_CC3_Msk             /*!< TIM1 CC3 Interrupt */
8004 #define SYSCFG_ITLINE14_SR_TIM1_CC4_Pos    (3U)
8005 #define SYSCFG_ITLINE14_SR_TIM1_CC4_Msk    (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC4_Pos)  /*!< 0x00000008 */
8006 #define SYSCFG_ITLINE14_SR_TIM1_CC4        SYSCFG_ITLINE14_SR_TIM1_CC4_Msk             /*!< TIM1 CC4 Interrupt */
8007 
8008 #define SYSCFG_ITLINE15_SR_TIM2_Pos        (0U)
8009 #define SYSCFG_ITLINE15_SR_TIM2_Msk        (0x1UL << SYSCFG_ITLINE15_SR_TIM2_Pos)      /*!< 0x00000001 */
8010 #define SYSCFG_ITLINE15_SR_TIM2            SYSCFG_ITLINE15_SR_TIM2_Msk                 /*!< TIM2 GLB Interrupt */
8011 
8012 #define SYSCFG_ITLINE16_SR_TIM3_Pos        (0U)
8013 #define SYSCFG_ITLINE16_SR_TIM3_Msk        (0x1UL << SYSCFG_ITLINE16_SR_TIM3_Pos)      /*!< 0x00000001 */
8014 #define SYSCFG_ITLINE16_SR_TIM3            SYSCFG_ITLINE16_SR_TIM3_Msk                 /*!< TIM3 GLB Interrupt */
8015 
8016 #define SYSCFG_ITLINE17_SR_TIM6_Pos        (0U)
8017 #define SYSCFG_ITLINE17_SR_TIM6_Msk        (0x1UL << SYSCFG_ITLINE17_SR_TIM6_Pos)      /*!< 0x00000001 */
8018 #define SYSCFG_ITLINE17_SR_TIM6            SYSCFG_ITLINE17_SR_TIM6_Msk                 /*!< TIM6 GLB Interrupt */
8019 #define SYSCFG_ITLINE17_SR_DAC_Pos         (1U)
8020 #define SYSCFG_ITLINE17_SR_DAC_Msk         (0x1UL << SYSCFG_ITLINE17_SR_DAC_Pos)       /*!< 0x00000002 */
8021 #define SYSCFG_ITLINE17_SR_DAC             SYSCFG_ITLINE17_SR_DAC_Msk                  /*!< DAC Interrupt */
8022 #define SYSCFG_ITLINE17_SR_LPTIM1_Pos      (2U)
8023 #define SYSCFG_ITLINE17_SR_LPTIM1_Msk      (0x1UL << SYSCFG_ITLINE17_SR_LPTIM1_Pos)    /*!< 0x00000004 */
8024 #define SYSCFG_ITLINE17_SR_LPTIM1          SYSCFG_ITLINE17_SR_LPTIM1_Msk               /*!< LPTIM1 -> exti[24] Interrupt */
8025 
8026 #define SYSCFG_ITLINE18_SR_TIM7_Pos        (0U)
8027 #define SYSCFG_ITLINE18_SR_TIM7_Msk        (0x1UL << SYSCFG_ITLINE18_SR_TIM7_Pos)      /*!< 0x00000001 */
8028 #define SYSCFG_ITLINE18_SR_TIM7            SYSCFG_ITLINE18_SR_TIM7_Msk                 /*!< TIM7 GLB Interrupt */
8029 #define SYSCFG_ITLINE18_SR_LPTIM2_Pos      (1U)
8030 #define SYSCFG_ITLINE18_SR_LPTIM2_Msk      (0x1UL << SYSCFG_ITLINE18_SR_LPTIM2_Pos)    /*!< 0x00000002 */
8031 #define SYSCFG_ITLINE18_SR_LPTIM2          SYSCFG_ITLINE18_SR_LPTIM2_Msk               /*!< LPTIM2 -> exti[25] Interrupt */
8032 
8033 #define SYSCFG_ITLINE19_SR_TIM15_Pos       (0U)
8034 #define SYSCFG_ITLINE19_SR_TIM15_Msk       (0x1UL << SYSCFG_ITLINE19_SR_TIM15_Pos)     /*!< 0x00000001 */
8035 #define SYSCFG_ITLINE19_SR_TIM15           SYSCFG_ITLINE19_SR_TIM15_Msk                /*!< TIM15 GLB Interrupt */
8036 #define SYSCFG_ITLINE19_SR_LPTIM3_Pos      (1U)
8037 #define SYSCFG_ITLINE19_SR_LPTIM3_Msk      (0x1UL << SYSCFG_ITLINE19_SR_LPTIM3_Pos)    /*!< 0x00000002 */
8038 #define SYSCFG_ITLINE19_SR_LPTIM3          SYSCFG_ITLINE19_SR_LPTIM3_Msk               /*!< LPTIM3 GLB Interrupt  -> exti [26]*/
8039 
8040 #define SYSCFG_ITLINE20_SR_TIM16_Pos       (0U)
8041 #define SYSCFG_ITLINE20_SR_TIM16_Msk       (0x1UL << SYSCFG_ITLINE20_SR_TIM16_Pos)     /*!< 0x00000001 */
8042 #define SYSCFG_ITLINE20_SR_TIM16           SYSCFG_ITLINE20_SR_TIM16_Msk                /*!< TIM16 GLB Interrupt */
8043 
8044 #define SYSCFG_ITLINE21_SR_TSC_MCE_Pos     (0U)
8045 #define SYSCFG_ITLINE21_SR_TSC_MCE_Msk     (0x1UL << SYSCFG_ITLINE21_SR_TSC_MCE_Pos)   /*!< 0x00000001 */
8046 #define SYSCFG_ITLINE21_SR_TSC_MCE         SYSCFG_ITLINE21_SR_TSC_MCE_Msk              /*!< TSC_MCE Interrupt */
8047 #define SYSCFG_ITLINE21_SR_TSC_EOA_Pos     (1U)
8048 #define SYSCFG_ITLINE21_SR_TSC_EOA_Msk     (0x1UL << SYSCFG_ITLINE21_SR_TSC_EOA_Pos)   /*!< 0x00000001 */
8049 #define SYSCFG_ITLINE21_SR_TSC_EOA         SYSCFG_ITLINE21_SR_TSC_EOA_Msk              /*!< TSC_MCE Interrupt */
8050 
8051 #define SYSCFG_ITLINE22_SR_LCD_Pos         (0U)
8052 #define SYSCFG_ITLINE22_SR_LCD_Msk         (0x1UL << SYSCFG_ITLINE22_SR_LCD_Pos)       /*!< 0x00000001 */
8053 #define SYSCFG_ITLINE22_SR_LCD             SYSCFG_ITLINE22_SR_LCD_Msk                  /*!< LCD GLB Interrupt */
8054 
8055 #define SYSCFG_ITLINE23_SR_I2C1_Pos        (0U)
8056 #define SYSCFG_ITLINE23_SR_I2C1_Msk        (0x1UL << SYSCFG_ITLINE23_SR_I2C1_Pos)      /*!< 0x00000001 */
8057 #define SYSCFG_ITLINE23_SR_I2C1            SYSCFG_ITLINE23_SR_I2C1_Msk                 /*!< I2C1 GLB Interrupt */
8058 
8059 #define SYSCFG_ITLINE24_SR_I2C2_Pos        (0U)
8060 #define SYSCFG_ITLINE24_SR_I2C2_Msk        (0x1UL << SYSCFG_ITLINE24_SR_I2C2_Pos)      /*!< 0x00000001 */
8061 #define SYSCFG_ITLINE24_SR_I2C2            SYSCFG_ITLINE24_SR_I2C2_Msk                 /*!< I2C2 GLB Interrupt */
8062 #define SYSCFG_ITLINE24_SR_I2C4_Pos        (1U)
8063 #define SYSCFG_ITLINE24_SR_I2C4_Msk        (0x1UL << SYSCFG_ITLINE24_SR_I2C4_Pos)      /*!< 0x00000002 */
8064 #define SYSCFG_ITLINE24_SR_I2C4            SYSCFG_ITLINE24_SR_I2C4_Msk                 /*!< I2C3 GLB Interrupt */
8065 #define SYSCFG_ITLINE24_SR_I2C3_Pos        (2U)
8066 #define SYSCFG_ITLINE24_SR_I2C3_Msk        (0x1UL << SYSCFG_ITLINE24_SR_I2C3_Pos)      /*!< 0x00000004 */
8067 #define SYSCFG_ITLINE24_SR_I2C3            SYSCFG_ITLINE24_SR_I2C3_Msk                 /*!< I2C3 GLB Interrupt  -> exti[23]*/
8068 
8069 #define SYSCFG_ITLINE25_SR_SPI1_Pos        (0U)
8070 #define SYSCFG_ITLINE25_SR_SPI1_Msk        (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos)      /*!< 0x00000001 */
8071 #define SYSCFG_ITLINE25_SR_SPI1            SYSCFG_ITLINE25_SR_SPI1_Msk                 /*!< SPI1 Interrupt */
8072 
8073 #define SYSCFG_ITLINE26_SR_SPI2_Pos        (0U)
8074 #define SYSCFG_ITLINE26_SR_SPI2_Msk        (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos)      /*!< 0x00000001 */
8075 #define SYSCFG_ITLINE26_SR_SPI2            SYSCFG_ITLINE26_SR_SPI2_Msk                 /*!< SPI2  Interrupt */
8076 #define SYSCFG_ITLINE26_SR_SPI3_Pos        (1U)
8077 #define SYSCFG_ITLINE26_SR_SPI3_Msk        (0x1UL << SYSCFG_ITLINE26_SR_SPI3_Pos)      /*!< 0x00000002 */
8078 #define SYSCFG_ITLINE26_SR_SPI3            SYSCFG_ITLINE26_SR_SPI3_Msk                 /*!< SPI3  Interrupt */
8079 
8080 #define SYSCFG_ITLINE27_SR_USART1_Pos      (0U)
8081 #define SYSCFG_ITLINE27_SR_USART1_Msk      (0x1UL << SYSCFG_ITLINE27_SR_USART1_Pos)    /*!< 0x00000001 */
8082 #define SYSCFG_ITLINE27_SR_USART1          SYSCFG_ITLINE27_SR_USART1_Msk               /*!< USART1 GLB Interrupt */
8083 
8084 #define SYSCFG_ITLINE28_SR_USART2_Pos      (0U)
8085 #define SYSCFG_ITLINE28_SR_USART2_Msk      (0x1UL << SYSCFG_ITLINE28_SR_USART2_Pos)    /*!< 0x00000001 */
8086 #define SYSCFG_ITLINE28_SR_USART2          SYSCFG_ITLINE28_SR_USART2_Msk               /*!< USART2 GLB Interrupt */
8087 #define SYSCFG_ITLINE28_SR_LPUART2_Pos     (1U)
8088 #define SYSCFG_ITLINE28_SR_LPUART2_Msk     (0x1UL << SYSCFG_ITLINE28_SR_LPUART2_Pos)   /*!< 0x00000002 */
8089 #define SYSCFG_ITLINE28_SR_LPUART2         SYSCFG_ITLINE28_SR_LPUART2_Msk              /*!< LPUART2 GLB Interrupt -> exti[31] */
8090 
8091 #define SYSCFG_ITLINE29_SR_USART3_Pos      (0U)
8092 #define SYSCFG_ITLINE29_SR_USART3_Msk      (0x1UL << SYSCFG_ITLINE29_SR_USART3_Pos)    /*!< 0x00000001 */
8093 #define SYSCFG_ITLINE29_SR_USART3          SYSCFG_ITLINE29_SR_USART3_Msk               /*!< USART3 GLB Interrupt */
8094 #define SYSCFG_ITLINE29_SR_LPUART1_Pos     (1U)
8095 #define SYSCFG_ITLINE29_SR_LPUART1_Msk     (0x1UL << SYSCFG_ITLINE29_SR_LPUART1_Pos)   /*!< 0x00000002 */
8096 #define SYSCFG_ITLINE29_SR_LPUART1         SYSCFG_ITLINE29_SR_LPUART1_Msk              /*!< LPUART1 GLB Interrupt -> exti[30] */
8097 
8098 #define SYSCFG_ITLINE30_SR_USART4_Pos      (0U)
8099 #define SYSCFG_ITLINE30_SR_USART4_Msk      (0x1UL << SYSCFG_ITLINE30_SR_USART4_Pos)    /*!< 0x00000001 */
8100 #define SYSCFG_ITLINE30_SR_USART4          SYSCFG_ITLINE30_SR_USART4_Msk               /*!< USART4 GLB Interrupt */
8101 #define SYSCFG_ITLINE30_SR_LPUART3_Pos     (1U)
8102 #define SYSCFG_ITLINE30_SR_LPUART3_Msk     (0x1UL << SYSCFG_ITLINE30_SR_LPUART3_Pos)   /*!< 0x00000002 */
8103 #define SYSCFG_ITLINE30_SR_LPUART3         SYSCFG_ITLINE30_SR_LPUART3_Msk              /*!< LPUART3 GLB Interrupt */
8104 
8105 #define SYSCFG_ITLINE31_SR_RNG_Pos         (0U)
8106 #define SYSCFG_ITLINE31_SR_RNG_Msk         (0x1UL << SYSCFG_ITLINE31_SR_RNG_Pos)       /*!< 0x00000001 */
8107 #define SYSCFG_ITLINE31_SR_RNG             SYSCFG_ITLINE31_SR_RNG_Msk                  /*!< RNG Interrupt */
8108 #define SYSCFG_ITLINE31_SR_AES_Pos         (1U)
8109 #define SYSCFG_ITLINE31_SR_AES_Msk         (0x1UL << SYSCFG_ITLINE31_SR_AES_Pos)       /*!< 0x00000002 */
8110 #define SYSCFG_ITLINE31_SR_AES             SYSCFG_ITLINE31_SR_AES_Msk                  /*!< AES Interrupt */
8111 
8112 /******************************************************************************/
8113 /*                                                                            */
8114 /*                                    TIM                                     */
8115 /*                                                                            */
8116 /******************************************************************************/
8117 /*******************  Bit definition for TIM_CR1 register  ********************/
8118 #define TIM_CR1_CEN_Pos           (0U)
8119 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
8120 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
8121 #define TIM_CR1_UDIS_Pos          (1U)
8122 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
8123 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
8124 #define TIM_CR1_URS_Pos           (2U)
8125 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
8126 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
8127 #define TIM_CR1_OPM_Pos           (3U)
8128 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
8129 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
8130 #define TIM_CR1_DIR_Pos           (4U)
8131 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
8132 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
8133 
8134 #define TIM_CR1_CMS_Pos           (5U)
8135 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
8136 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
8137 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */
8138 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */
8139 
8140 #define TIM_CR1_ARPE_Pos          (7U)
8141 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
8142 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
8143 
8144 #define TIM_CR1_CKD_Pos           (8U)
8145 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
8146 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
8147 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */
8148 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */
8149 
8150 #define TIM_CR1_UIFREMAP_Pos      (11U)
8151 #define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
8152 #define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
8153 
8154 /*******************  Bit definition for TIM_CR2 register  ********************/
8155 #define TIM_CR2_CCPC_Pos          (0U)
8156 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
8157 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
8158 #define TIM_CR2_CCUS_Pos          (2U)
8159 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
8160 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
8161 #define TIM_CR2_CCDS_Pos          (3U)
8162 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
8163 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
8164 
8165 #define TIM_CR2_MMS_Pos           (4U)
8166 #define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */
8167 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
8168 #define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000010 */
8169 #define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000020 */
8170 #define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000040 */
8171 
8172 #define TIM_CR2_TI1S_Pos          (7U)
8173 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
8174 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
8175 #define TIM_CR2_OIS1_Pos          (8U)
8176 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
8177 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
8178 #define TIM_CR2_OIS1N_Pos         (9U)
8179 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
8180 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
8181 #define TIM_CR2_OIS2_Pos          (10U)
8182 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
8183 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
8184 #define TIM_CR2_OIS2N_Pos         (11U)
8185 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
8186 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
8187 #define TIM_CR2_OIS3_Pos          (12U)
8188 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
8189 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
8190 #define TIM_CR2_OIS3N_Pos         (13U)
8191 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
8192 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
8193 #define TIM_CR2_OIS4_Pos          (14U)
8194 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
8195 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
8196 #define TIM_CR2_OIS5_Pos          (16U)
8197 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
8198 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
8199 #define TIM_CR2_OIS6_Pos          (18U)
8200 #define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
8201 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
8202 
8203 #define TIM_CR2_MMS2_Pos          (20U)
8204 #define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
8205 #define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
8206 #define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */
8207 #define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */
8208 #define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */
8209 #define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */
8210 
8211 /*******************  Bit definition for TIM_SMCR register  *******************/
8212 #define TIM_SMCR_SMS_Pos          (0U)
8213 #define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
8214 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
8215 #define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */
8216 #define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */
8217 #define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */
8218 #define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */
8219 
8220 #define TIM_SMCR_OCCS_Pos         (3U)
8221 #define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                 /*!< 0x00000008 */
8222 #define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
8223 
8224 #define TIM_SMCR_TS_Pos           (4U)
8225 #define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
8226 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
8227 #define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)               /*!< 0x00000010 */
8228 #define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)               /*!< 0x00000020 */
8229 #define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)               /*!< 0x00000040 */
8230 #define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)               /*!< 0x00100000 */
8231 #define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)               /*!< 0x00200000 */
8232 
8233 #define TIM_SMCR_MSM_Pos          (7U)
8234 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
8235 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
8236 
8237 #define TIM_SMCR_ETF_Pos          (8U)
8238 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
8239 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
8240 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */
8241 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */
8242 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */
8243 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */
8244 
8245 #define TIM_SMCR_ETPS_Pos         (12U)
8246 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
8247 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
8248 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */
8249 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */
8250 
8251 #define TIM_SMCR_ECE_Pos          (14U)
8252 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
8253 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
8254 #define TIM_SMCR_ETP_Pos          (15U)
8255 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
8256 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
8257 
8258 /*******************  Bit definition for TIM_DIER register  *******************/
8259 #define TIM_DIER_UIE_Pos          (0U)
8260 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
8261 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
8262 #define TIM_DIER_CC1IE_Pos        (1U)
8263 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
8264 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
8265 #define TIM_DIER_CC2IE_Pos        (2U)
8266 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
8267 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
8268 #define TIM_DIER_CC3IE_Pos        (3U)
8269 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
8270 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
8271 #define TIM_DIER_CC4IE_Pos        (4U)
8272 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
8273 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
8274 #define TIM_DIER_COMIE_Pos        (5U)
8275 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
8276 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
8277 #define TIM_DIER_TIE_Pos          (6U)
8278 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
8279 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
8280 #define TIM_DIER_BIE_Pos          (7U)
8281 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
8282 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
8283 #define TIM_DIER_UDE_Pos          (8U)
8284 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
8285 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
8286 #define TIM_DIER_CC1DE_Pos        (9U)
8287 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
8288 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
8289 #define TIM_DIER_CC2DE_Pos        (10U)
8290 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
8291 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
8292 #define TIM_DIER_CC3DE_Pos        (11U)
8293 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
8294 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
8295 #define TIM_DIER_CC4DE_Pos        (12U)
8296 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
8297 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
8298 #define TIM_DIER_COMDE_Pos        (13U)
8299 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
8300 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
8301 #define TIM_DIER_TDE_Pos          (14U)
8302 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
8303 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
8304 
8305 /********************  Bit definition for TIM_SR register  ********************/
8306 #define TIM_SR_UIF_Pos            (0U)
8307 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
8308 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
8309 #define TIM_SR_CC1IF_Pos          (1U)
8310 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
8311 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
8312 #define TIM_SR_CC2IF_Pos          (2U)
8313 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
8314 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
8315 #define TIM_SR_CC3IF_Pos          (3U)
8316 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
8317 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
8318 #define TIM_SR_CC4IF_Pos          (4U)
8319 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
8320 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
8321 #define TIM_SR_COMIF_Pos          (5U)
8322 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
8323 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
8324 #define TIM_SR_TIF_Pos            (6U)
8325 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
8326 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
8327 #define TIM_SR_BIF_Pos            (7U)
8328 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
8329 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
8330 #define TIM_SR_B2IF_Pos           (8U)
8331 #define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
8332 #define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
8333 #define TIM_SR_CC1OF_Pos          (9U)
8334 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
8335 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
8336 #define TIM_SR_CC2OF_Pos          (10U)
8337 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
8338 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
8339 #define TIM_SR_CC3OF_Pos          (11U)
8340 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
8341 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
8342 #define TIM_SR_CC4OF_Pos          (12U)
8343 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
8344 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
8345 #define TIM_SR_SBIF_Pos           (13U)
8346 #define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
8347 #define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
8348 #define TIM_SR_CC5IF_Pos          (16U)
8349 #define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
8350 #define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
8351 #define TIM_SR_CC6IF_Pos          (17U)
8352 #define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
8353 #define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
8354 
8355 
8356 /*******************  Bit definition for TIM_EGR register  ********************/
8357 #define TIM_EGR_UG_Pos            (0U)
8358 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
8359 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
8360 #define TIM_EGR_CC1G_Pos          (1U)
8361 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
8362 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
8363 #define TIM_EGR_CC2G_Pos          (2U)
8364 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
8365 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
8366 #define TIM_EGR_CC3G_Pos          (3U)
8367 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
8368 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
8369 #define TIM_EGR_CC4G_Pos          (4U)
8370 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
8371 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
8372 #define TIM_EGR_COMG_Pos          (5U)
8373 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
8374 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
8375 #define TIM_EGR_TG_Pos            (6U)
8376 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
8377 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
8378 #define TIM_EGR_BG_Pos            (7U)
8379 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
8380 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
8381 #define TIM_EGR_B2G_Pos           (8U)
8382 #define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
8383 #define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
8384 
8385 
8386 /******************  Bit definition for TIM_CCMR1 register  *******************/
8387 #define TIM_CCMR1_CC1S_Pos        (0U)
8388 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
8389 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
8390 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */
8391 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */
8392 
8393 #define TIM_CCMR1_OC1FE_Pos       (2U)
8394 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
8395 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
8396 #define TIM_CCMR1_OC1PE_Pos       (3U)
8397 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
8398 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
8399 
8400 #define TIM_CCMR1_OC1M_Pos        (4U)
8401 #define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
8402 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
8403 #define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */
8404 #define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */
8405 #define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */
8406 #define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */
8407 
8408 #define TIM_CCMR1_OC1CE_Pos       (7U)
8409 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
8410 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
8411 
8412 #define TIM_CCMR1_CC2S_Pos        (8U)
8413 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
8414 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
8415 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */
8416 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */
8417 
8418 #define TIM_CCMR1_OC2FE_Pos       (10U)
8419 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
8420 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
8421 #define TIM_CCMR1_OC2PE_Pos       (11U)
8422 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
8423 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
8424 
8425 #define TIM_CCMR1_OC2M_Pos        (12U)
8426 #define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
8427 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
8428 #define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */
8429 #define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */
8430 #define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */
8431 #define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */
8432 
8433 #define TIM_CCMR1_OC2CE_Pos       (15U)
8434 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
8435 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
8436 
8437 /*----------------------------------------------------------------------------*/
8438 #define TIM_CCMR1_IC1PSC_Pos      (2U)
8439 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
8440 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
8441 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */
8442 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */
8443 
8444 #define TIM_CCMR1_IC1F_Pos        (4U)
8445 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
8446 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
8447 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */
8448 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */
8449 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */
8450 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */
8451 
8452 #define TIM_CCMR1_IC2PSC_Pos      (10U)
8453 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
8454 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
8455 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */
8456 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */
8457 
8458 #define TIM_CCMR1_IC2F_Pos        (12U)
8459 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
8460 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
8461 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */
8462 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */
8463 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */
8464 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */
8465 
8466 /******************  Bit definition for TIM_CCMR2 register  *******************/
8467 #define TIM_CCMR2_CC3S_Pos        (0U)
8468 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
8469 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
8470 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */
8471 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */
8472 
8473 #define TIM_CCMR2_OC3FE_Pos       (2U)
8474 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
8475 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
8476 #define TIM_CCMR2_OC3PE_Pos       (3U)
8477 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
8478 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
8479 
8480 #define TIM_CCMR2_OC3M_Pos        (4U)
8481 #define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */
8482 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
8483 #define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */
8484 #define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */
8485 #define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */
8486 #define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */
8487 
8488 #define TIM_CCMR2_OC3CE_Pos       (7U)
8489 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
8490 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
8491 
8492 #define TIM_CCMR2_CC4S_Pos        (8U)
8493 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
8494 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
8495 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */
8496 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */
8497 
8498 #define TIM_CCMR2_OC4FE_Pos       (10U)
8499 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
8500 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
8501 #define TIM_CCMR2_OC4PE_Pos       (11U)
8502 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
8503 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
8504 
8505 #define TIM_CCMR2_OC4M_Pos        (12U)
8506 #define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */
8507 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
8508 #define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */
8509 #define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */
8510 #define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */
8511 #define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */
8512 
8513 #define TIM_CCMR2_OC4CE_Pos       (15U)
8514 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
8515 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
8516 
8517 /*----------------------------------------------------------------------------*/
8518 #define TIM_CCMR2_IC3PSC_Pos      (2U)
8519 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
8520 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
8521 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */
8522 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */
8523 
8524 #define TIM_CCMR2_IC3F_Pos        (4U)
8525 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
8526 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
8527 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */
8528 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */
8529 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */
8530 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */
8531 
8532 #define TIM_CCMR2_IC4PSC_Pos      (10U)
8533 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
8534 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
8535 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */
8536 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */
8537 
8538 #define TIM_CCMR2_IC4F_Pos        (12U)
8539 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
8540 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
8541 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */
8542 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */
8543 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */
8544 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */
8545 
8546 /******************  Bit definition for TIM_CCMR3 register  *******************/
8547 #define TIM_CCMR3_OC5FE_Pos       (2U)
8548 #define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
8549 #define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
8550 #define TIM_CCMR3_OC5PE_Pos       (3U)
8551 #define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
8552 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
8553 
8554 #define TIM_CCMR3_OC5M_Pos        (4U)
8555 #define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */
8556 #define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
8557 #define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */
8558 #define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */
8559 #define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */
8560 #define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */
8561 
8562 #define TIM_CCMR3_OC5CE_Pos       (7U)
8563 #define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
8564 #define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
8565 
8566 #define TIM_CCMR3_OC6FE_Pos       (10U)
8567 #define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
8568 #define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
8569 #define TIM_CCMR3_OC6PE_Pos       (11U)
8570 #define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
8571 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
8572 
8573 #define TIM_CCMR3_OC6M_Pos        (12U)
8574 #define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */
8575 #define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
8576 #define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */
8577 #define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */
8578 #define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */
8579 #define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */
8580 
8581 #define TIM_CCMR3_OC6CE_Pos       (15U)
8582 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
8583 #define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
8584 
8585 /*******************  Bit definition for TIM_CCER register  *******************/
8586 #define TIM_CCER_CC1E_Pos         (0U)
8587 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
8588 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
8589 #define TIM_CCER_CC1P_Pos         (1U)
8590 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
8591 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
8592 #define TIM_CCER_CC1NE_Pos        (2U)
8593 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
8594 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
8595 #define TIM_CCER_CC1NP_Pos        (3U)
8596 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
8597 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
8598 #define TIM_CCER_CC2E_Pos         (4U)
8599 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
8600 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
8601 #define TIM_CCER_CC2P_Pos         (5U)
8602 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
8603 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
8604 #define TIM_CCER_CC2NE_Pos        (6U)
8605 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
8606 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
8607 #define TIM_CCER_CC2NP_Pos        (7U)
8608 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
8609 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
8610 #define TIM_CCER_CC3E_Pos         (8U)
8611 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
8612 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
8613 #define TIM_CCER_CC3P_Pos         (9U)
8614 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
8615 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
8616 #define TIM_CCER_CC3NE_Pos        (10U)
8617 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
8618 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
8619 #define TIM_CCER_CC3NP_Pos        (11U)
8620 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
8621 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
8622 #define TIM_CCER_CC4E_Pos         (12U)
8623 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
8624 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
8625 #define TIM_CCER_CC4P_Pos         (13U)
8626 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
8627 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
8628 #define TIM_CCER_CC4NP_Pos        (15U)
8629 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
8630 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
8631 #define TIM_CCER_CC5E_Pos         (16U)
8632 #define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
8633 #define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
8634 #define TIM_CCER_CC5P_Pos         (17U)
8635 #define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
8636 #define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
8637 #define TIM_CCER_CC6E_Pos         (20U)
8638 #define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
8639 #define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
8640 #define TIM_CCER_CC6P_Pos         (21U)
8641 #define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
8642 #define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
8643 
8644 /*******************  Bit definition for TIM_CNT register  ********************/
8645 #define TIM_CNT_CNT_Pos           (0U)
8646 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
8647 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
8648 #define TIM_CNT_UIFCPY_Pos        (31U)
8649 #define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
8650 #define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
8651 
8652 /*******************  Bit definition for TIM_PSC register  ********************/
8653 #define TIM_PSC_PSC_Pos           (0U)
8654 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
8655 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
8656 
8657 /*******************  Bit definition for TIM_ARR register  ********************/
8658 #define TIM_ARR_ARR_Pos           (0U)
8659 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
8660 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
8661 
8662 /*******************  Bit definition for TIM_RCR register  ********************/
8663 #define TIM_RCR_REP_Pos           (0U)
8664 #define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */
8665 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
8666 
8667 /*******************  Bit definition for TIM_CCR1 register  *******************/
8668 #define TIM_CCR1_CCR1_Pos         (0U)
8669 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */
8670 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
8671 
8672 /*******************  Bit definition for TIM_CCR2 register  *******************/
8673 #define TIM_CCR2_CCR2_Pos         (0U)
8674 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */
8675 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
8676 
8677 /*******************  Bit definition for TIM_CCR3 register  *******************/
8678 #define TIM_CCR3_CCR3_Pos         (0U)
8679 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */
8680 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
8681 
8682 /*******************  Bit definition for TIM_CCR4 register  *******************/
8683 #define TIM_CCR4_CCR4_Pos         (0U)
8684 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */
8685 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
8686 
8687 /*******************  Bit definition for TIM_CCR5 register  *******************/
8688 #define TIM_CCR5_CCR5_Pos         (0U)
8689 #define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */
8690 #define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
8691 #define TIM_CCR5_GC5C1_Pos        (29U)
8692 #define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
8693 #define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
8694 #define TIM_CCR5_GC5C2_Pos        (30U)
8695 #define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
8696 #define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
8697 #define TIM_CCR5_GC5C3_Pos        (31U)
8698 #define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
8699 #define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
8700 
8701 /*******************  Bit definition for TIM_CCR6 register  *******************/
8702 #define TIM_CCR6_CCR6_Pos         (0U)
8703 #define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
8704 #define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
8705 
8706 /*******************  Bit definition for TIM_BDTR register  *******************/
8707 #define TIM_BDTR_DTG_Pos          (0U)
8708 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
8709 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
8710 #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */
8711 #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */
8712 #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */
8713 #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */
8714 #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */
8715 #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */
8716 #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */
8717 #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */
8718 
8719 #define TIM_BDTR_LOCK_Pos         (8U)
8720 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
8721 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
8722 #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */
8723 #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */
8724 
8725 #define TIM_BDTR_OSSI_Pos         (10U)
8726 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
8727 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
8728 #define TIM_BDTR_OSSR_Pos         (11U)
8729 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
8730 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
8731 #define TIM_BDTR_BKE_Pos          (12U)
8732 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
8733 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
8734 #define TIM_BDTR_BKP_Pos          (13U)
8735 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
8736 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
8737 #define TIM_BDTR_AOE_Pos          (14U)
8738 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
8739 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
8740 #define TIM_BDTR_MOE_Pos          (15U)
8741 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
8742 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
8743 
8744 #define TIM_BDTR_BKF_Pos          (16U)
8745 #define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
8746 #define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
8747 #define TIM_BDTR_BK2F_Pos         (20U)
8748 #define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
8749 #define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
8750 
8751 #define TIM_BDTR_BK2E_Pos         (24U)
8752 #define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
8753 #define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
8754 #define TIM_BDTR_BK2P_Pos         (25U)
8755 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
8756 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
8757 
8758 #define TIM_BDTR_BKDSRM_Pos       (26U)
8759 #define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
8760 #define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break disarming/re-arming */
8761 #define TIM_BDTR_BK2DSRM_Pos      (27U)
8762 #define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
8763 #define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 disarming/re-arming */
8764 
8765 #define TIM_BDTR_BKBID_Pos        (28U)
8766 #define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
8767 #define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break BIDirectional */
8768 #define TIM_BDTR_BK2BID_Pos       (29U)
8769 #define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
8770 #define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 BIDirectional */
8771 
8772 /*******************  Bit definition for TIM_DCR register  ********************/
8773 #define TIM_DCR_DBA_Pos           (0U)
8774 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
8775 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
8776 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */
8777 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */
8778 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */
8779 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */
8780 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */
8781 
8782 #define TIM_DCR_DBL_Pos           (8U)
8783 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
8784 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
8785 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */
8786 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */
8787 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */
8788 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */
8789 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */
8790 
8791 /*******************  Bit definition for TIM_DMAR register  *******************/
8792 #define TIM_DMAR_DMAB_Pos         (0U)
8793 #define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */
8794 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
8795 
8796 /*******************  Bit definition for TIM1_OR register  ********************/
8797 #define TIM_OR1_OCREF_CLR_Pos     (0U)
8798 #define TIM_OR1_OCREF_CLR_Msk     (0x1UL << TIM_OR1_OCREF_CLR_Pos)            /*!< 0x00000001 */
8799 #define TIM_OR1_OCREF_CLR         TIM_OR1_OCREF_CLR_Msk                       /*!<OCREF clear input selection */
8800 
8801 /*******************  Bit definition for TIM_AF1 register  *******************/
8802 #define TIM_AF1_BKINE_Pos        (0U)
8803 #define TIM_AF1_BKINE_Msk        (0x1UL << TIM_AF1_BKINE_Pos)                /*!< 0x00000001 */
8804 #define TIM_AF1_BKINE            TIM_AF1_BKINE_Msk                           /*!<BRK BKIN input enable */
8805 #define TIM_AF1_BKCMP1E_Pos      (1U)
8806 #define TIM_AF1_BKCMP1E_Msk      (0x1UL << TIM_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
8807 #define TIM_AF1_BKCMP1E          TIM_AF1_BKCMP1E_Msk                         /*!<BRK COMP1 enable */
8808 #define TIM_AF1_BKCMP2E_Pos      (2U)
8809 #define TIM_AF1_BKCMP2E_Msk      (0x1UL << TIM_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
8810 #define TIM_AF1_BKCMP2E          TIM_AF1_BKCMP2E_Msk                         /*!<BRK COMP2 enable */
8811 #define TIM_AF1_BKINP_Pos        (9U)
8812 #define TIM_AF1_BKINP_Msk        (0x1UL << TIM_AF1_BKINP_Pos)                /*!< 0x00000200 */
8813 #define TIM_AF1_BKINP            TIM_AF1_BKINP_Msk                           /*!<BRK BKIN input polarity */
8814 #define TIM_AF1_BKCMP1P_Pos      (10U)
8815 #define TIM_AF1_BKCMP1P_Msk      (0x1UL << TIM_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
8816 #define TIM_AF1_BKCMP1P          TIM_AF1_BKCMP1P_Msk                         /*!<BRK COMP1 input polarity */
8817 #define TIM_AF1_BKCMP2P_Pos      (11U)
8818 #define TIM_AF1_BKCMP2P_Msk      (0x1UL << TIM_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
8819 #define TIM_AF1_BKCMP2P          TIM_AF1_BKCMP2P_Msk                         /*!<BRK COMP2 input polarity */
8820 
8821 #define TIM_AF1_ETRSEL_Pos       (14U)
8822 #define TIM_AF1_ETRSEL_Msk       (0xFUL << TIM_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
8823 #define TIM_AF1_ETRSEL           TIM_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
8824 #define TIM_AF1_ETRSEL_0         (0x1UL << TIM_AF1_ETRSEL_Pos)               /*!< 0x00004000 */
8825 #define TIM_AF1_ETRSEL_1         (0x2UL << TIM_AF1_ETRSEL_Pos)               /*!< 0x00008000 */
8826 #define TIM_AF1_ETRSEL_2         (0x4UL << TIM_AF1_ETRSEL_Pos)               /*!< 0x00010000 */
8827 #define TIM_AF1_ETRSEL_3         (0x8UL << TIM_AF1_ETRSEL_Pos)               /*!< 0x00020000 */
8828 
8829 /*******************  Bit definition for TIM_AF2 register  *******************/
8830 #define TIM_AF2_BK2INE_Pos       (0U)
8831 #define TIM_AF2_BK2INE_Msk       (0x1UL << TIM_AF2_BK2INE_Pos)               /*!< 0x00000001 */
8832 #define TIM_AF2_BK2INE           TIM_AF2_BK2INE_Msk                          /*!<BRK2 BKIN2 input enable */
8833 #define TIM_AF2_BK2CMP1E_Pos     (1U)
8834 #define TIM_AF2_BK2CMP1E_Msk     (0x1UL << TIM_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */
8835 #define TIM_AF2_BK2CMP1E         TIM_AF2_BK2CMP1E_Msk                        /*!<BRK2 COMP1 enable */
8836 #define TIM_AF2_BK2CMP2E_Pos     (2U)
8837 #define TIM_AF2_BK2CMP2E_Msk     (0x1UL << TIM_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */
8838 #define TIM_AF2_BK2CMP2E         TIM_AF2_BK2CMP2E_Msk                        /*!<BRK2 COMP2 enable */
8839 #define TIM_AF2_BK2INP_Pos       (9U)
8840 #define TIM_AF2_BK2INP_Msk       (0x1UL << TIM_AF2_BK2INP_Pos)               /*!< 0x00000200 */
8841 #define TIM_AF2_BK2INP           TIM_AF2_BK2INP_Msk                          /*!<BRK2 BKIN2 input polarity */
8842 #define TIM_AF2_BK2CMP1P_Pos     (10U)
8843 #define TIM_AF2_BK2CMP1P_Msk     (0x1UL << TIM_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */
8844 #define TIM_AF2_BK2CMP1P         TIM_AF2_BK2CMP1P_Msk                        /*!<BRK2 COMP1 input polarity */
8845 #define TIM_AF2_BK2CMP2P_Pos     (11U)
8846 #define TIM_AF2_BK2CMP2P_Msk     (0x1UL << TIM_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */
8847 #define TIM_AF2_BK2CMP2P         TIM_AF2_BK2CMP2P_Msk                        /*!<BRK2 COMP2 input polarity */
8848 
8849 /*******************  Bit definition for TIM_TISEL register  *********************/
8850 #define TIM_TISEL_TI1SEL_Pos      (0U)
8851 #define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
8852 #define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/
8853 #define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000001 */
8854 #define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000002 */
8855 #define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000004 */
8856 #define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000008 */
8857 
8858 #define TIM_TISEL_TI2SEL_Pos      (8U)
8859 #define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
8860 #define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/
8861 #define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000100 */
8862 #define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000200 */
8863 #define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000400 */
8864 #define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000800 */
8865 
8866 #define TIM_TISEL_TI3SEL_Pos      (16U)
8867 #define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */
8868 #define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/
8869 #define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00010000 */
8870 #define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00020000 */
8871 #define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00040000 */
8872 #define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00080000 */
8873 
8874 #define TIM_TISEL_TI4SEL_Pos      (24U)
8875 #define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */
8876 #define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/
8877 #define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x01000000 */
8878 #define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x02000000 */
8879 #define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x04000000 */
8880 #define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x08000000 */
8881 
8882 /******************************************************************************/
8883 /*                                                                            */
8884 /*                         Low Power Timer (LPTIM)                            */
8885 /*                                                                            */
8886 /******************************************************************************/
8887 /******************  Bit definition for LPTIM_ISR register  *******************/
8888 #define LPTIM_ISR_CC1IF_Pos         (0U)
8889 #define LPTIM_ISR_CC1IF_Msk         (0x1UL << LPTIM_ISR_CC1IF_Pos)             /*!< 0x00000001 */
8890 #define LPTIM_ISR_CC1IF             LPTIM_ISR_CC1IF_Msk                        /*!< Capture/Compare 1 interrupt flag */
8891 #define LPTIM_ISR_ARRM_Pos          (1U)
8892 #define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
8893 #define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
8894 #define LPTIM_ISR_EXTTRIG_Pos       (2U)
8895 #define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
8896 #define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
8897 #define LPTIM_ISR_CMP1OK_Pos        (3U)
8898 #define LPTIM_ISR_CMP1OK_Msk        (0x1UL << LPTIM_ISR_CMP1OK_Pos)            /*!< 0x00000008 */
8899 #define LPTIM_ISR_CMP1OK            LPTIM_ISR_CMP1OK_Msk                       /*!< Compare register 1 update OK */
8900 #define LPTIM_ISR_ARROK_Pos         (4U)
8901 #define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
8902 #define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
8903 #define LPTIM_ISR_UP_Pos            (5U)
8904 #define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
8905 #define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
8906 #define LPTIM_ISR_DOWN_Pos          (6U)
8907 #define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
8908 #define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
8909 #define LPTIM_ISR_UE_Pos            (7U)
8910 #define LPTIM_ISR_UE_Msk            (0x1UL << LPTIM_ISR_UE_Pos)                /*!< 0x00000080 */
8911 #define LPTIM_ISR_UE                LPTIM_ISR_UE_Msk                           /*!< Update event */
8912 #define LPTIM_ISR_REPOK_Pos         (8U)
8913 #define LPTIM_ISR_REPOK_Msk         (0x1UL << LPTIM_ISR_REPOK_Pos)             /*!< 0x00000100 */
8914 #define LPTIM_ISR_REPOK             LPTIM_ISR_REPOK_Msk                        /*!< Repetition register update OK */
8915 #define LPTIM_ISR_CC2IF_Pos         (9U)
8916 #define LPTIM_ISR_CC2IF_Msk         (0x1UL << LPTIM_ISR_CC2IF_Pos)             /*!< 0x00000200 */
8917 #define LPTIM_ISR_CC2IF             LPTIM_ISR_CC2IF_Msk                        /*!< Capture/Compare 2 interrupt flag */
8918 #define LPTIM_ISR_CC3IF_Pos         (10U)
8919 #define LPTIM_ISR_CC3IF_Msk         (0x1UL << LPTIM_ISR_CC3IF_Pos)             /*!< 0x00000400 */
8920 #define LPTIM_ISR_CC3IF             LPTIM_ISR_CC3IF_Msk                        /*!< Capture/Compare 3 interrupt flag */
8921 #define LPTIM_ISR_CC4IF_Pos         (11U)
8922 #define LPTIM_ISR_CC4IF_Msk         (0x1UL << LPTIM_ISR_CC4IF_Pos)             /*!< 0x00000800 */
8923 #define LPTIM_ISR_CC4IF             LPTIM_ISR_CC4IF_Msk                        /*!< Capture/Compare 4 interrupt flag */
8924 #define LPTIM_ISR_CC1OF_Pos         (12U)
8925 #define LPTIM_ISR_CC1OF_Msk         (0x1UL << LPTIM_ISR_CC1OF_Pos)            /*!< 0x00001000 */
8926 #define LPTIM_ISR_CC1OF             LPTIM_ISR_CC1OF_Msk                       /*!< Capture/Compare 1 over-capture flag */
8927 #define LPTIM_ISR_CC2OF_Pos         (13U)
8928 #define LPTIM_ISR_CC2OF_Msk         (0x1UL << LPTIM_ISR_CC2OF_Pos)            /*!< 0x00002000 */
8929 #define LPTIM_ISR_CC2OF             LPTIM_ISR_CC2OF_Msk                       /*!< Capture/Compare 2 over-capture flag */
8930 #define LPTIM_ISR_CC3OF_Pos         (14U)
8931 #define LPTIM_ISR_CC3OF_Msk         (0x1UL << LPTIM_ISR_CC3OF_Pos)            /*!< 0x00004000 */
8932 #define LPTIM_ISR_CC3OF             LPTIM_ISR_CC3OF_Msk                       /*!< Capture/Compare 3 over-capture flag */
8933 #define LPTIM_ISR_CC4OF_Pos         (15U)
8934 #define LPTIM_ISR_CC4OF_Msk         (0x1UL << LPTIM_ISR_CC4OF_Pos)            /*!< 0x00008000 */
8935 #define LPTIM_ISR_CC4OF             LPTIM_ISR_CC4OF_Msk                       /*!< Capture/Compare 4 over-capture flag */
8936 #define LPTIM_ISR_CMP2OK_Pos        (19U)
8937 #define LPTIM_ISR_CMP2OK_Msk        (0x1UL << LPTIM_ISR_CMP2OK_Pos)          /*!< 0x00080000 */
8938 #define LPTIM_ISR_CMP2OK            LPTIM_ISR_CMP2OK_Msk                     /*!< Compare register 2 update OK */
8939 #define LPTIM_ISR_CMP3OK_Pos        (20U)
8940 #define LPTIM_ISR_CMP3OK_Msk        (0x1UL << LPTIM_ISR_CMP3OK_Pos)          /*!< 0x00100000 */
8941 #define LPTIM_ISR_CMP3OK            LPTIM_ISR_CMP3OK_Msk                     /*!< Compare register 3 update OK */
8942 #define LPTIM_ISR_CMP4OK_Pos        (21U)
8943 #define LPTIM_ISR_CMP4OK_Msk        (0x1UL << LPTIM_ISR_CMP4OK_Pos)          /*!< 0x00200000 */
8944 #define LPTIM_ISR_CMP4OK            LPTIM_ISR_CMP4OK_Msk                     /*!< Compare register 4 update OK */
8945 #define LPTIM_ISR_DIEROK_Pos        (24U)
8946 #define LPTIM_ISR_DIEROK_Msk        (0x1UL << LPTIM_ISR_DIEROK_Pos)          /*!< 0x01000000 */
8947 #define LPTIM_ISR_DIEROK            LPTIM_ISR_DIEROK_Msk                     /*!< DMA & interrupt enable update OK */
8948 
8949 /******************  Bit definition for LPTIM_ICR register  *******************/
8950 #define LPTIM_ICR_CC1CF_Pos         (0U)
8951 #define LPTIM_ICR_CC1CF_Msk         (0x1UL << LPTIM_ICR_CC1CF_Pos)             /*!< 0x00000001 */
8952 #define LPTIM_ICR_CC1CF             LPTIM_ICR_CC1CF_Msk                        /*!< Capture/Compare 1 clear flag  */
8953 #define LPTIM_ICR_ARRMCF_Pos        (1U)
8954 #define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
8955 #define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match clear flag */
8956 #define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
8957 #define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
8958 #define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event clear flag */
8959 #define LPTIM_ICR_CMP1OKCF_Pos      (3U)
8960 #define LPTIM_ICR_CMP1OKCF_Msk      (0x1UL << LPTIM_ICR_CMP1OKCF_Pos)          /*!< 0x00000008 */
8961 #define LPTIM_ICR_CMP1OKCF          LPTIM_ICR_CMP1OKCF_Msk                     /*!< Compare register 1 update OK clear flag */
8962 #define LPTIM_ICR_ARROKCF_Pos       (4U)
8963 #define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
8964 #define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK clear flag */
8965 #define LPTIM_ICR_UPCF_Pos          (5U)
8966 #define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
8967 #define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up clear flag */
8968 #define LPTIM_ICR_DOWNCF_Pos        (6U)
8969 #define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
8970 #define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down clear flag */
8971 #define LPTIM_ICR_UECF_Pos          (7U)
8972 #define LPTIM_ICR_UECF_Msk          (0x1UL << LPTIM_ICR_UECF_Pos)              /*!< 0x00000080 */
8973 #define LPTIM_ICR_UECF              LPTIM_ICR_UECF_Msk                         /*!< Update event clear flag */
8974 #define LPTIM_ICR_REPOKCF_Pos       (8U)
8975 #define LPTIM_ICR_REPOKCF_Msk       (0x1UL << LPTIM_ICR_REPOKCF_Pos)           /*!< 0x00000100 */
8976 #define LPTIM_ICR_REPOKCF           LPTIM_ICR_REPOKCF_Msk                      /*!< Repetition register update OK clear flag */
8977 #define LPTIM_ICR_CC2CF_Pos         (9U)
8978 #define LPTIM_ICR_CC2CF_Msk         (0x1UL << LPTIM_ICR_CC2CF_Pos)             /*!< 0x00000200 */
8979 #define LPTIM_ICR_CC2CF             LPTIM_ICR_CC2CF_Msk                        /*!< Capture/Compare 2 clear flag  */
8980 #define LPTIM_ICR_CC3CF_Pos         (10U)
8981 #define LPTIM_ICR_CC3CF_Msk         (0x1UL << LPTIM_ICR_CC3CF_Pos)             /*!< 0x00000400 */
8982 #define LPTIM_ICR_CC3CF             LPTIM_ICR_CC3CF_Msk                        /*!< Capture/Compare 3 clear flag  */
8983 #define LPTIM_ICR_CC4CF_Pos         (11U)
8984 #define LPTIM_ICR_CC4CF_Msk         (0x1UL << LPTIM_ICR_CC4CF_Pos)             /*!< 0x00000800 */
8985 #define LPTIM_ICR_CC4CF             LPTIM_ICR_CC4CF_Msk                        /*!< Capture/Compare 4 clear flag  */
8986 #define LPTIM_ICR_CC1OCF_Pos        (12U)
8987 #define LPTIM_ICR_CC1OCF_Msk        (0x1UL << LPTIM_ICR_CC1OCF_Pos)            /*!< 0x00001000 */
8988 #define LPTIM_ICR_CC1OCF            LPTIM_ICR_CC1OCF_Msk                       /*!< Capture/Compare 1 over-capture clear flag */
8989 #define LPTIM_ICR_CC2OCF_Pos        (13U)
8990 #define LPTIM_ICR_CC2OCF_Msk        (0x1UL << LPTIM_ICR_CC2OCF_Pos)            /*!< 0x00002000 */
8991 #define LPTIM_ICR_CC2OCF            LPTIM_ICR_CC2OCF_Msk                       /*!< Capture/Compare 2 over-capture clear flag */
8992 #define LPTIM_ICR_CC3OCF_Pos        (14U)
8993 #define LPTIM_ICR_CC3OCF_Msk        (0x1UL << LPTIM_ICR_CC3OCF_Pos)            /*!< 0x00004000 */
8994 #define LPTIM_ICR_CC3OCF            LPTIM_ICR_CC3OCF_Msk                       /*!< Capture/Compare 3 over-capture clear flag */
8995 #define LPTIM_ICR_CC4OCF_Pos        (15U)
8996 #define LPTIM_ICR_CC4OCF_Msk        (0x1UL << LPTIM_ICR_CC4OCF_Pos)            /*!< 0x00008000 */
8997 #define LPTIM_ICR_CC4OCF            LPTIM_ICR_CC4OCF_Msk                       /*!< Capture/Compare 4 over-capture clear flag */
8998 #define LPTIM_ICR_CMP2OKCF_Pos      (19U)
8999 #define LPTIM_ICR_CMP2OKCF_Msk      (0x1UL << LPTIM_ICR_CMP2OKCF_Pos)          /*!< 0x00080000 */
9000 #define LPTIM_ICR_CMP2OKCF          LPTIM_ICR_CMP2OKCF_Msk                     /*!< Compare register 2 update OK clear flag */
9001 #define LPTIM_ICR_CMP3OKCF_Pos      (20U)
9002 #define LPTIM_ICR_CMP3OKCF_Msk      (0x1UL << LPTIM_ICR_CMP3OKCF_Pos)          /*!< 0x00100000 */
9003 #define LPTIM_ICR_CMP3OKCF          LPTIM_ICR_CMP3OKCF_Msk                     /*!< Compare register 3 update OK clear flag */
9004 #define LPTIM_ICR_CMP4OKCF_Pos      (21U)
9005 #define LPTIM_ICR_CMP4OKCF_Msk      (0x1UL << LPTIM_ICR_CMP4OKCF_Pos)          /*!< 0x00200000 */
9006 #define LPTIM_ICR_CMP4OKCF          LPTIM_ICR_CMP4OKCF_Msk                     /*!< Compare register 4 update OK clear flag */
9007 #define LPTIM_ICR_DIEROKCF_Pos      (24U)
9008 #define LPTIM_ICR_DIEROKCF_Msk      (0x1UL << LPTIM_ICR_DIEROKCF_Pos)          /*!< 0x01000000 */
9009 #define LPTIM_ICR_DIEROKCF          LPTIM_ICR_DIEROKCF_Msk                     /*!< DMA & interrupt enable update OK clear flag */
9010 
9011 /******************  Bit definition for LPTIM_DIER register *******************/
9012 #define LPTIM_DIER_CC1IE_Pos         (0U)
9013 #define LPTIM_DIER_CC1IE_Msk         (0x1UL << LPTIM_DIER_CC1IE_Pos)           /*!< 0x00000001 */
9014 #define LPTIM_DIER_CC1IE             LPTIM_DIER_CC1IE_Msk                      /*!< Compare/Compare 1 interrupt enable */
9015 #define LPTIM_DIER_ARRMIE_Pos        (1U)
9016 #define LPTIM_DIER_ARRMIE_Msk        (0x1UL << LPTIM_DIER_ARRMIE_Pos)          /*!< 0x00000002 */
9017 #define LPTIM_DIER_ARRMIE            LPTIM_DIER_ARRMIE_Msk                     /*!< Autoreload match interrupt enable */
9018 #define LPTIM_DIER_EXTTRIGIE_Pos     (2U)
9019 #define LPTIM_DIER_EXTTRIGIE_Msk     (0x1UL << LPTIM_DIER_EXTTRIGIE_Pos)       /*!< 0x00000004 */
9020 #define LPTIM_DIER_EXTTRIGIE         LPTIM_DIER_EXTTRIGIE_Msk                  /*!< External trigger edge event interrupt enable */
9021 #define LPTIM_DIER_CMP1OKIE_Pos      (3U)
9022 #define LPTIM_DIER_CMP1OKIE_Msk      (0x1UL << LPTIM_DIER_CMP1OKIE_Pos)        /*!< 0x00000008 */
9023 #define LPTIM_DIER_CMP1OKIE          LPTIM_DIER_CMP1OKIE_Msk                   /*!< Compare register 1 update OK interrupt enable */
9024 #define LPTIM_DIER_ARROKIE_Pos       (4U)
9025 #define LPTIM_DIER_ARROKIE_Msk       (0x1UL << LPTIM_DIER_ARROKIE_Pos)         /*!< 0x00000010 */
9026 #define LPTIM_DIER_ARROKIE           LPTIM_DIER_ARROKIE_Msk                    /*!< Autoreload register update OK interrupt enable */
9027 #define LPTIM_DIER_UPIE_Pos          (5U)
9028 #define LPTIM_DIER_UPIE_Msk          (0x1UL << LPTIM_DIER_UPIE_Pos)            /*!< 0x00000020 */
9029 #define LPTIM_DIER_UPIE              LPTIM_DIER_UPIE_Msk                       /*!< Counter direction change down to up interrupt enable */
9030 #define LPTIM_DIER_DOWNIE_Pos        (6U)
9031 #define LPTIM_DIER_DOWNIE_Msk        (0x1UL << LPTIM_DIER_DOWNIE_Pos)          /*!< 0x00000040 */
9032 #define LPTIM_DIER_DOWNIE            LPTIM_DIER_DOWNIE_Msk                     /*!< Counter direction change up to down interrupt enable */
9033 #define LPTIM_DIER_UEIE_Pos          (7U)
9034 #define LPTIM_DIER_UEIE_Msk          (0x1UL << LPTIM_DIER_UEIE_Pos)            /*!< 0x00000080 */
9035 #define LPTIM_DIER_UEIE              LPTIM_DIER_UEIE_Msk                       /*!< Update event interrupt enable */
9036 #define LPTIM_DIER_REPOKIE_Pos       (8U)
9037 #define LPTIM_DIER_REPOKIE_Msk       (0x1UL << LPTIM_DIER_REPOKIE_Pos)         /*!< 0x00000100 */
9038 #define LPTIM_DIER_REPOKIE           LPTIM_DIER_REPOKIE_Msk                    /*!< Repetition register update OK interrupt enable */
9039 #define LPTIM_DIER_CC2IE_Pos         (9U)
9040 #define LPTIM_DIER_CC2IE_Msk         (0x1UL << LPTIM_DIER_CC2IE_Pos)           /*!< 0x00000200 */
9041 #define LPTIM_DIER_CC2IE             LPTIM_DIER_CC2IE_Msk                      /*!< Capture/Compare 2 interrupt interrupt enable */
9042 #define LPTIM_DIER_CC3IE_Pos         (10U)
9043 #define LPTIM_DIER_CC3IE_Msk         (0x1UL << LPTIM_DIER_CC3IE_Pos)           /*!< 0x00000400 */
9044 #define LPTIM_DIER_CC3IE             LPTIM_DIER_CC3IE_Msk                      /*!< Capture/Compare 3 interrupt interrupt enable */
9045 #define LPTIM_DIER_CC4IE_Pos         (11U)
9046 #define LPTIM_DIER_CC4IE_Msk         (0x1UL << LPTIM_DIER_CC4IE_Pos)           /*!< 0x00000800 */
9047 #define LPTIM_DIER_CC4IE             LPTIM_DIER_CC4IE_Msk                      /*!< Capture/Compare 4 interrupt interrupt enable */
9048 #define LPTIM_DIER_CC1OIE_Pos        (12U)
9049 #define LPTIM_DIER_CC1OIE_Msk        (0x1UL << LPTIM_DIER_CC1OIE_Pos)          /*!< 0x00001000 */
9050 #define LPTIM_DIER_CC1OIE            LPTIM_DIER_CC1OIE_Msk                     /*!< Capture/Compare 1 over-capture interrupt enable */
9051 #define LPTIM_DIER_CC2OIE_Pos        (13U)
9052 #define LPTIM_DIER_CC2OIE_Msk        (0x1UL << LPTIM_DIER_CC2OIE_Pos)          /*!< 0x00002000 */
9053 #define LPTIM_DIER_CC2OIE            LPTIM_DIER_CC2OIE_Msk                     /*!< Capture/Compare 2 over-capture interrupt enable */
9054 #define LPTIM_DIER_CC3OIE_Pos        (14U)
9055 #define LPTIM_DIER_CC3OIE_Msk        (0x1UL << LPTIM_DIER_CC3OIE_Pos)          /*!< 0x00004000 */
9056 #define LPTIM_DIER_CC3OIE            LPTIM_DIER_CC3OIE_Msk                     /*!< Capture/Compare 3 over-capture interrupt enable */
9057 #define LPTIM_DIER_CC4OIE_Pos        (15U)
9058 #define LPTIM_DIER_CC4OIE_Msk        (0x1UL << LPTIM_DIER_CC4OIE_Pos)          /*!< 0x00008000 */
9059 #define LPTIM_DIER_CC4OIE            LPTIM_DIER_CC4OIE_Msk                     /*!< Capture/Compare 4 over-capture interrupt enable */
9060 #define LPTIM_DIER_CC1DE_Pos         (16U)
9061 #define LPTIM_DIER_CC1DE_Msk         (0x1UL << LPTIM_DIER_CC1DE_Pos)           /*!< 0x00010000 */
9062 #define LPTIM_DIER_CC1DE             LPTIM_DIER_CC1DE_Msk                      /*!< Capture/Compare 1 DMA request enable */
9063 #define LPTIM_DIER_CMP2OKIE_Pos      (19U)
9064 #define LPTIM_DIER_CMP2OKIE_Msk      (0x1UL << LPTIM_DIER_CMP2OKIE_Pos)        /*!< 0x00080000 */
9065 #define LPTIM_DIER_CMP2OKIE          LPTIM_DIER_CMP2OKIE_Msk                   /*!< Compare register 2 update OK interrupt enable */
9066 #define LPTIM_DIER_CMP3OKIE_Pos      (20U)
9067 #define LPTIM_DIER_CMP3OKIE_Msk      (0x1UL << LPTIM_DIER_CMP3OKIE_Pos)        /*!< 0x00100000 */
9068 #define LPTIM_DIER_CMP3OKIE          LPTIM_DIER_CMP3OKIE_Msk                   /*!< Compare register 3 update OK interrupt enable */
9069 #define LPTIM_DIER_CMP4OKIE_Pos      (21U)
9070 #define LPTIM_DIER_CMP4OKIE_Msk      (0x1UL << LPTIM_DIER_CMP4OKIE_Pos)        /*!< 0x00200000 */
9071 #define LPTIM_DIER_CMP4OKIE          LPTIM_DIER_CMP4OKIE_Msk                   /*!< Compare register 4 update OK interrupt enable */
9072 #define LPTIM_DIER_UEDE_Pos          (23U)
9073 #define LPTIM_DIER_UEDE_Msk          (0x1UL << LPTIM_DIER_UEDE_Pos)            /*!< 0x00800000 */
9074 #define LPTIM_DIER_UEDE              LPTIM_DIER_UEDE_Msk                       /*!< Update event DMA request enable */
9075 #define LPTIM_DIER_CC2DE_Pos         (25U)
9076 #define LPTIM_DIER_CC2DE_Msk         (0x1UL << LPTIM_DIER_CC2DE_Pos)           /*!< 0x02000000 */
9077 #define LPTIM_DIER_CC2DE             LPTIM_DIER_CC2DE_Msk                      /*!< Capture/Compare 2 DMA request enable */
9078 #define LPTIM_DIER_CC3DE_Pos         (26U)
9079 #define LPTIM_DIER_CC3DE_Msk         (0x1UL << LPTIM_DIER_CC3DE_Pos)           /*!< 0x04000000 */
9080 #define LPTIM_DIER_CC3DE             LPTIM_DIER_CC3DE_Msk                      /*!< Capture/Compare 3 DMA request enable */
9081 #define LPTIM_DIER_CC4DE_Pos         (27U)
9082 #define LPTIM_DIER_CC4DE_Msk         (0x1UL << LPTIM_DIER_CC4DE_Pos)           /*!< 0x08000000 */
9083 #define LPTIM_DIER_CC4DE             LPTIM_DIER_CC4DE_Msk                      /*!< Capture/Compare 4 DMA request enable */
9084 
9085 /******************  Bit definition for LPTIM_CFGR register *******************/
9086 #define LPTIM_CFGR_CKSEL_Pos        (0U)
9087 #define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
9088 #define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
9089 #define LPTIM_CFGR_CKPOL_Pos        (1U)
9090 #define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
9091 #define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
9092 #define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
9093 #define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
9094 #define LPTIM_CFGR_CKFLT_Pos        (3U)
9095 #define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
9096 #define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
9097 #define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
9098 #define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
9099 #define LPTIM_CFGR_TRGFLT_Pos       (6U)
9100 #define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
9101 #define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
9102 #define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
9103 #define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
9104 #define LPTIM_CFGR_PRESC_Pos        (9U)
9105 #define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
9106 #define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
9107 #define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
9108 #define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
9109 #define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
9110 #define LPTIM_CFGR_TRIGSEL_Pos      (13U)
9111 #define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */
9112 #define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
9113 #define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
9114 #define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
9115 #define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
9116 #define LPTIM_CFGR_TRIGEN_Pos       (17U)
9117 #define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
9118 #define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
9119 #define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
9120 #define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
9121 #define LPTIM_CFGR_TIMOUT_Pos       (19U)
9122 #define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
9123 #define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
9124 #define LPTIM_CFGR_WAVE_Pos         (20U)
9125 #define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
9126 #define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
9127 #define LPTIM_CFGR_WAVPOL_Pos       (21U)
9128 #define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
9129 #define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape */
9130 #define LPTIM_CFGR_PRELOAD_Pos      (22U)
9131 #define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
9132 #define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
9133 #define LPTIM_CFGR_COUNTMODE_Pos    (23U)
9134 #define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
9135 #define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
9136 #define LPTIM_CFGR_ENC_Pos          (24U)
9137 #define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
9138 #define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
9139 
9140 /******************  Bit definition for LPTIM_CR register  ********************/
9141 #define LPTIM_CR_ENABLE_Pos         (0U)
9142 #define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
9143 #define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
9144 #define LPTIM_CR_SNGSTRT_Pos        (1U)
9145 #define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */
9146 #define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
9147 #define LPTIM_CR_CNTSTRT_Pos        (2U)
9148 #define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
9149 #define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
9150 #define LPTIM_CR_COUNTRST_Pos       (3U)
9151 #define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
9152 #define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/
9153 #define LPTIM_CR_RSTARE_Pos         (4U)
9154 #define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
9155 #define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/
9156 
9157 /******************  Bit definition for LPTIM_CCR1 register  ******************/
9158 #define LPTIM_CCR1_CCR1_Pos         (0U)
9159 #define LPTIM_CCR1_CCR1_Msk         (0xFFFFUL << LPTIM_CCR1_CCR1_Pos)          /*!< 0x0000FFFF */
9160 #define LPTIM_CCR1_CCR1             LPTIM_CCR1_CCR1_Msk                        /*!< Compare register 1 */
9161 
9162 /******************  Bit definition for LPTIM_ARR register  *******************/
9163 #define LPTIM_ARR_ARR_Pos           (0U)
9164 #define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
9165 #define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
9166 
9167 /******************  Bit definition for LPTIM_CNT register  *******************/
9168 #define LPTIM_CNT_CNT_Pos           (0U)
9169 #define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
9170 #define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
9171 
9172 /******************  Bit definition for LPTIM_CFGR2 register  *****************/
9173 #define LPTIM_CFGR2_IN1SEL_Pos      (0U)
9174 #define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */
9175 #define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */
9176 #define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */
9177 #define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */
9178 #define LPTIM_CFGR2_IN2SEL_Pos      (4U)
9179 #define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */
9180 #define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */
9181 #define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */
9182 #define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */
9183 #define LPTIM_CFGR2_IC1SEL_Pos      (16U)
9184 #define LPTIM_CFGR2_IC1SEL_Msk      (0x3UL << LPTIM_CFGR2_IC1SEL_Pos)          /*!< 0x00030000 */
9185 #define LPTIM_CFGR2_IC1SEL          LPTIM_CFGR2_IC1SEL_Msk                     /*!< IC1SEL[17:16] bits */
9186 #define LPTIM_CFGR2_IC1SEL_0        (0x1UL << LPTIM_CFGR2_IC1SEL_Pos)          /*!< 0x00010000 */
9187 #define LPTIM_CFGR2_IC1SEL_1        (0x2UL << LPTIM_CFGR2_IC1SEL_Pos)          /*!< 0x00020000 */
9188 #define LPTIM_CFGR2_IC2SEL_Pos      (20U)
9189 #define LPTIM_CFGR2_IC2SEL_Msk      (0x3UL << LPTIM_CFGR2_IC2SEL_Pos)          /*!< 0x00300000 */
9190 #define LPTIM_CFGR2_IC2SEL          LPTIM_CFGR2_IC2SEL_Msk                     /*!< IC2SEL[21:20] bits */
9191 #define LPTIM_CFGR2_IC2SEL_0        (0x1U << LPTIM_CFGR2_IC2SEL_Pos)           /*!< 0x00100000 */
9192 #define LPTIM_CFGR2_IC2SEL_1        (0x2U << LPTIM_CFGR2_IC2SEL_Pos)           /*!< 0x00200000 */
9193 #define LPTIM_CFGR2_IC3SEL_Pos      (24U)
9194 #define LPTIM_CFGR2_IC3SEL_Msk      (0x3UL << LPTIM_CFGR2_IC3SEL_Pos)          /*!< 0x03000000 */
9195 #define LPTIM_CFGR2_IC3SEL          LPTIM_CFGR2_IC3SEL_Msk                     /*!< IC3SEL[25:24] bits */
9196 #define LPTIM_CFGR2_IC3SEL_0        (0x1U << LPTIM_CFGR2_IC3SEL_Pos)           /*!< 0x01000000 */
9197 #define LPTIM_CFGR2_IC3SEL_1        (0x2U << LPTIM_CFGR2_IC3SEL_Pos)           /*!< 0x02000000 */
9198 #define LPTIM_CFGR2_IC4SEL_Pos      (28U)
9199 #define LPTIM_CFGR2_IC4SEL_Msk      (0x3UL << LPTIM_CFGR2_IC4SEL_Pos)          /*!< 0x30000000 */
9200 #define LPTIM_CFGR2_IC4SEL          LPTIM_CFGR2_IC4SEL_Msk                     /*!< IC4SEL[29:28] bits */
9201 #define LPTIM_CFGR2_IC4SEL_0        (0x1U << LPTIM_CFGR2_IC4SEL_Pos)           /*!< 0x10000000 */
9202 #define LPTIM_CFGR2_IC4SEL_1        (0x2U << LPTIM_CFGR2_IC4SEL_Pos)           /*!< 0x20000000 */
9203 
9204 /******************  Bit definition for LPTIM_RCR register  *******************/
9205 #define LPTIM_RCR_REP_Pos           (0U)
9206 #define LPTIM_RCR_REP_Msk           (0xFFUL << LPTIM_RCR_REP_Pos)              /*!< 0x000000FF */
9207 #define LPTIM_RCR_REP               LPTIM_RCR_REP_Msk                          /*!< Repetition register value */
9208 
9209 /*****************  Bit definition for LPTIM_CCMR1 register  ******************/
9210 #define LPTIM_CCMR1_CC1SEL_Pos      (0U)
9211 #define LPTIM_CCMR1_CC1SEL_Msk      (0x1UL << LPTIM_CCMR1_CC1SEL_Pos)           /*!< 0x00000001 */
9212 #define LPTIM_CCMR1_CC1SEL          LPTIM_CCMR1_CC1SEL_Msk                      /*!< Capture/Compare 1 selection */
9213 #define LPTIM_CCMR1_CC1E_Pos        (1U)
9214 #define LPTIM_CCMR1_CC1E_Msk        (0x1UL << LPTIM_CCMR1_CC1E_Pos)             /*!< 0x00000002 */
9215 #define LPTIM_CCMR1_CC1E            LPTIM_CCMR1_CC1E_Msk                        /*!< Capture/Compare 1 output enable */
9216 #define LPTIM_CCMR1_CC1P_Pos        (2U)
9217 #define LPTIM_CCMR1_CC1P_Msk        (0x3UL << LPTIM_CCMR1_CC1P_Pos)             /*!< 0x0000000C */
9218 #define LPTIM_CCMR1_CC1P            LPTIM_CCMR1_CC1P_Msk                        /*!< Capture/Compare 1 output polarity */
9219 #define LPTIM_CCMR1_CC1P_0          (0x1UL << LPTIM_CCMR1_CC1P_Pos)             /*!< 0x00000004 */
9220 #define LPTIM_CCMR1_CC1P_1          (0x2UL << LPTIM_CCMR1_CC1P_Pos)             /*!< 0x00000008 */
9221 #define LPTIM_CCMR1_IC1PSC_Pos      (8U)
9222 #define LPTIM_CCMR1_IC1PSC_Msk      (0x3UL << LPTIM_CCMR1_IC1PSC_Pos)           /*!< 0x00000300 */
9223 #define LPTIM_CCMR1_IC1PSC          LPTIM_CCMR1_IC1PSC_Msk                      /*!< Input capture 1 prescaler */
9224 #define LPTIM_CCMR1_IC1PSC_0        (0x1UL << LPTIM_CCMR1_IC1PSC_Pos)           /*!< 0x00000100 */
9225 #define LPTIM_CCMR1_IC1PSC_1        (0x2UL << LPTIM_CCMR1_IC1PSC_Pos)           /*!< 0x00000200 */
9226 #define LPTIM_CCMR1_IC1F_Pos        (12U)
9227 #define LPTIM_CCMR1_IC1F_Msk        (0x3UL << LPTIM_CCMR1_IC1F_Pos)             /*!< 0x00003000 */
9228 #define LPTIM_CCMR1_IC1F            LPTIM_CCMR1_IC1F_Msk                        /*!< Input capture 1 filter */
9229 #define LPTIM_CCMR1_IC1F_0          (0x1UL << LPTIM_CCMR1_IC1F_Pos)             /*!< 0x00001000 */
9230 #define LPTIM_CCMR1_IC1F_1          (0x2UL << LPTIM_CCMR1_IC1F_Pos)             /*!< 0x00002000 */
9231 #define LPTIM_CCMR1_CC2SEL_Pos      (16U)
9232 #define LPTIM_CCMR1_CC2SEL_Msk      (0x1UL << LPTIM_CCMR1_CC2SEL_Pos)           /*!< 0x00010000 */
9233 #define LPTIM_CCMR1_CC2SEL          LPTIM_CCMR1_CC2SEL_Msk                      /*!< Capture/Compare 2 selection */
9234 #define LPTIM_CCMR1_CC2E_Pos        (17U)
9235 #define LPTIM_CCMR1_CC2E_Msk        (0x1UL << LPTIM_CCMR1_CC2E_Pos)             /*!< 0x00020000 */
9236 #define LPTIM_CCMR1_CC2E            LPTIM_CCMR1_CC2E_Msk                        /*!< Capture/Compare 2 output enable */
9237 #define LPTIM_CCMR1_CC2P_Pos        (18U)
9238 #define LPTIM_CCMR1_CC2P_Msk        (0x3UL << LPTIM_CCMR1_CC2P_Pos)             /*!< 0x000C0000 */
9239 #define LPTIM_CCMR1_CC2P            LPTIM_CCMR1_CC2P_Msk                        /*!< Capture/Compare 2 output polarity */
9240 #define LPTIM_CCMR1_CC2P_0          (0x1UL << LPTIM_CCMR1_CC2P_Pos)             /*!< 0x00040000 */
9241 #define LPTIM_CCMR1_CC2P_1          (0x2UL << LPTIM_CCMR1_CC2P_Pos)             /*!< 0x00080000 */
9242 #define LPTIM_CCMR1_IC2PSC_Pos      (24U)
9243 #define LPTIM_CCMR1_IC2PSC_Msk      (0x3UL << LPTIM_CCMR1_IC2PSC_Pos)           /*!< 0x03000000 */
9244 #define LPTIM_CCMR1_IC2PSC          LPTIM_CCMR1_IC2PSC_Msk                      /*!< Input capture 2 prescaler */
9245 #define LPTIM_CCMR1_IC2PSC_0        (0x1UL << LPTIM_CCMR1_IC2PSC_Pos)           /*!< 0x01000000 */
9246 #define LPTIM_CCMR1_IC2PSC_1        (0x2UL << LPTIM_CCMR1_IC2PSC_Pos)           /*!< 0x02000000 */
9247 #define LPTIM_CCMR1_IC2F_Pos        (28U)
9248 #define LPTIM_CCMR1_IC2F_Msk        (0x3UL << LPTIM_CCMR1_IC2F_Pos)             /*!< 0x30000000 */
9249 #define LPTIM_CCMR1_IC2F            LPTIM_CCMR1_IC2F_Msk                        /*!< Input capture 2 filter */
9250 #define LPTIM_CCMR1_IC2F_0          (0x1UL << LPTIM_CCMR1_IC2F_Pos)             /*!< 0x10000000 */
9251 #define LPTIM_CCMR1_IC2F_1          (0x2UL << LPTIM_CCMR1_IC2F_Pos)             /*!< 0x20000000 */
9252 
9253 /*****************  Bit definition for LPTIM_CCMR2 register  ******************/
9254 #define LPTIM_CCMR2_CC3SEL_Pos      (0U)
9255 #define LPTIM_CCMR2_CC3SEL_Msk      (0x1UL << LPTIM_CCMR2_CC3SEL_Pos)           /*!< 0x00000001 */
9256 #define LPTIM_CCMR2_CC3SEL          LPTIM_CCMR2_CC3SEL_Msk                      /*!< Capture/Compare 3 selection */
9257 #define LPTIM_CCMR2_CC3E_Pos        (1U)
9258 #define LPTIM_CCMR2_CC3E_Msk        (0x1UL << LPTIM_CCMR2_CC3E_Pos)             /*!< 0x00000002 */
9259 #define LPTIM_CCMR2_CC3E            LPTIM_CCMR2_CC3E_Msk                        /*!< Capture/Compare 3 output enable */
9260 #define LPTIM_CCMR2_CC3P_Pos        (2U)
9261 #define LPTIM_CCMR2_CC3P_Msk        (0x3UL << LPTIM_CCMR2_CC3P_Pos)             /*!< 0x0000000C */
9262 #define LPTIM_CCMR2_CC3P            LPTIM_CCMR2_CC3P_Msk                        /*!< Capture/Compare 3 output polarity */
9263 #define LPTIM_CCMR2_CC3P_0          (0x1UL << LPTIM_CCMR2_CC3P_Pos)             /*!< 0x00000004 */
9264 #define LPTIM_CCMR2_CC3P_1          (0x2UL << LPTIM_CCMR2_CC3P_Pos)             /*!< 0x00000008 */
9265 #define LPTIM_CCMR2_IC3PSC_Pos      (8U)
9266 #define LPTIM_CCMR2_IC3PSC_Msk      (0x3UL << LPTIM_CCMR2_IC3PSC_Pos)           /*!< 0x00000300 */
9267 #define LPTIM_CCMR2_IC3PSC          LPTIM_CCMR2_IC3PSC_Msk                      /*!< Input capture 3 prescaler */
9268 #define LPTIM_CCMR2_IC3PSC_0        (0x1UL << LPTIM_CCMR2_IC3PSC_Pos)           /*!< 0x00000100 */
9269 #define LPTIM_CCMR2_IC3PSC_1        (0x2UL << LPTIM_CCMR2_IC3PSC_Pos)           /*!< 0x00000200 */
9270 #define LPTIM_CCMR2_IC3F_Pos        (12U)
9271 #define LPTIM_CCMR2_IC3F_Msk        (0x3UL << LPTIM_CCMR2_IC3F_Pos)             /*!< 0x00003000 */
9272 #define LPTIM_CCMR2_IC3F            LPTIM_CCMR2_IC3F_Msk                        /*!< Input capture 3 filter */
9273 #define LPTIM_CCMR2_IC3F_0          (0x1UL << LPTIM_CCMR2_IC3F_Pos)             /*!< 0x00001000 */
9274 #define LPTIM_CCMR2_IC3F_1          (0x2UL << LPTIM_CCMR2_IC3F_Pos)             /*!< 0x00002000 */
9275 #define LPTIM_CCMR2_CC4SEL_Pos      (16U)
9276 #define LPTIM_CCMR2_CC4SEL_Msk      (0x1UL << LPTIM_CCMR2_CC4SEL_Pos)           /*!< 0x00010000 */
9277 #define LPTIM_CCMR2_CC4SEL          LPTIM_CCMR2_CC4SEL_Msk                      /*!< Capture/Compare 4 selection */
9278 #define LPTIM_CCMR2_CC4E_Pos        (17U)
9279 #define LPTIM_CCMR2_CC4E_Msk        (0x1UL << LPTIM_CCMR2_CC4E_Pos)             /*!< 0x00020000 */
9280 #define LPTIM_CCMR2_CC4E            LPTIM_CCMR2_CC4E_Msk                        /*!< Capture/Compare 4 output enable */
9281 #define LPTIM_CCMR2_CC4P_Pos        (18U)
9282 #define LPTIM_CCMR2_CC4P_Msk        (0x3UL << LPTIM_CCMR2_CC4P_Pos)             /*!< 0x000C0000 */
9283 #define LPTIM_CCMR2_CC4P            LPTIM_CCMR2_CC4P_Msk                        /*!< Capture/Compare 4 output polarity */
9284 #define LPTIM_CCMR2_CC4P_0          (0x1UL << LPTIM_CCMR2_CC4P_Pos)             /*!< 0x00040000 */
9285 #define LPTIM_CCMR2_CC4P_1          (0x2UL << LPTIM_CCMR2_CC4P_Pos)             /*!< 0x00080000 */
9286 #define LPTIM_CCMR2_IC4PSC_Pos      (24U)
9287 #define LPTIM_CCMR2_IC4PSC_Msk      (0x3UL << LPTIM_CCMR2_IC4PSC_Pos)           /*!< 0x03000000 */
9288 #define LPTIM_CCMR2_IC4PSC          LPTIM_CCMR2_IC4PSC_Msk                      /*!< Input capture 4 prescaler */
9289 #define LPTIM_CCMR2_IC4PSC_0        (0x1UL << LPTIM_CCMR2_IC4PSC_Pos)           /*!< 0x01000000 */
9290 #define LPTIM_CCMR2_IC4PSC_1        (0x2UL << LPTIM_CCMR2_IC4PSC_Pos)           /*!< 0x02000000 */
9291 #define LPTIM_CCMR2_IC4F_Pos        (28U)
9292 #define LPTIM_CCMR2_IC4F_Msk        (0x3UL << LPTIM_CCMR2_IC4F_Pos)             /*!< 0x30000000 */
9293 #define LPTIM_CCMR2_IC4F            LPTIM_CCMR2_IC4F_Msk                        /*!< Input capture 4 filter */
9294 #define LPTIM_CCMR2_IC4F_0          (0x1UL << LPTIM_CCMR2_IC4F_Pos)             /*!< 0x10000000 */
9295 #define LPTIM_CCMR2_IC4F_1          (0x2UL << LPTIM_CCMR2_IC4F_Pos)             /*!< 0x20000000 */
9296 
9297 /******************  Bit definition for LPTIM_CCR2 register  ******************/
9298 #define LPTIM_CCR2_CCR2_Pos         (0U)
9299 #define LPTIM_CCR2_CCR2_Msk         (0xFFFFUL << LPTIM_CCR2_CCR2_Pos)          /*!< 0x0000FFFF */
9300 #define LPTIM_CCR2_CCR2             LPTIM_CCR2_CCR2_Msk                        /*!< Compare register 2 */
9301 
9302 /******************  Bit definition for LPTIM_CCR3 register  ******************/
9303 #define LPTIM_CCR3_CCR3_Pos         (0U)
9304 #define LPTIM_CCR3_CCR3_Msk         (0xFFFFUL << LPTIM_CCR3_CCR3_Pos)          /*!< 0x0000FFFF */
9305 #define LPTIM_CCR3_CCR3             LPTIM_CCR3_CCR3_Msk                        /*!< Compare register 3 */
9306 
9307 /******************  Bit definition for LPTIM_CCR4 register  ******************/
9308 #define LPTIM_CCR4_CCR4_Pos         (0U)
9309 #define LPTIM_CCR4_CCR4_Msk         (0xFFFFUL << LPTIM_CCR4_CCR4_Pos)          /*!< 0x0000FFFF */
9310 #define LPTIM_CCR4_CCR4             LPTIM_CCR4_CCR4_Msk                        /*!< Compare register 4 */
9311 
9312 /******************************************************************************/
9313 /*                                                                            */
9314 /*                      Analog Comparators (COMP)                             */
9315 /*                                                                            */
9316 /******************************************************************************/
9317 
9318 /******************  Bit definition for COMPx_CSR register  *******************/
9319 #define COMP_CSR_EN_Pos                (0U)
9320 #define COMP_CSR_EN_Msk                (0x1UL << COMP_CSR_EN_Pos)              /*!< 0x00000001 */
9321 #define COMP_CSR_EN                    COMP_CSR_EN_Msk                         /*!< COMPx enable bit */
9322 #define COMP_CSR_INMSEL_Pos            (4U)
9323 #define COMP_CSR_INMSEL_Msk            (0xFUL << COMP_CSR_INMSEL_Pos)          /*!< 0x000000F0 */
9324 #define COMP_CSR_INMSEL                COMP_CSR_INMSEL_Msk                     /*!< COMPx input minus selection bit  */
9325 #define COMP_CSR_INMSEL_0              (0x1UL << COMP_CSR_INMSEL_Pos)          /*!< 0x00000010 */
9326 #define COMP_CSR_INMSEL_1              (0x2UL << COMP_CSR_INMSEL_Pos)          /*!< 0x00000020 */
9327 #define COMP_CSR_INMSEL_2              (0x4UL << COMP_CSR_INMSEL_Pos)          /*!< 0x00000040 */
9328 #define COMP_CSR_INMSEL_3              (0x8UL << COMP_CSR_INMSEL_Pos)          /*!< 0x00000080 */
9329 #define COMP_CSR_INPSEL_Pos            (8U)
9330 #define COMP_CSR_INPSEL_Msk            (0x7UL << COMP_CSR_INPSEL_Pos)          /*!< 0x00000700 */
9331 #define COMP_CSR_INPSEL                COMP_CSR_INPSEL_Msk                     /*!< COMPx input plus selection bit */
9332 #define COMP_CSR_INPSEL_0              (0x1UL << COMP_CSR_INPSEL_Pos)          /*!< 0x00000100 */
9333 #define COMP_CSR_INPSEL_1              (0x2UL << COMP_CSR_INPSEL_Pos)          /*!< 0x00000200 */
9334 #define COMP_CSR_INPSEL_2              (0x4UL << COMP_CSR_INPSEL_Pos)          /*!< 0x00000400 */
9335 #define COMP_CSR_WINMODE_Pos           (11U)
9336 #define COMP_CSR_WINMODE_Msk           (0x1UL << COMP_CSR_WINMODE_Pos)         /*!< 0x00000800 */
9337 #define COMP_CSR_WINMODE               COMP_CSR_WINMODE_Msk                    /*!< COMPx Windows mode selection bit */
9338 #define COMP_CSR_WINOUT_Pos            (14U)
9339 #define COMP_CSR_WINOUT_Msk            (0x1UL << COMP_CSR_WINOUT_Pos)          /*!< 0x00004000 */
9340 #define COMP_CSR_WINOUT                COMP_CSR_WINOUT_Msk                     /*!< COMPx polarity selection bit */
9341 #define COMP_CSR_POLARITY_Pos          (15U)
9342 #define COMP_CSR_POLARITY_Msk          (0x1UL << COMP_CSR_POLARITY_Pos)        /*!< 0x00008000 */
9343 #define COMP_CSR_POLARITY              COMP_CSR_POLARITY_Msk                   /*!< COMPx polarity selection bit */
9344 #define COMP_CSR_HYST_Pos              (16U)
9345 #define COMP_CSR_HYST_Msk              (0x3UL << COMP_CSR_HYST_Pos)            /*!< 0x00030000 */
9346 #define COMP_CSR_HYST                  COMP_CSR_HYST_Msk                       /*!< COMPx hysteresis selection bits */
9347 #define COMP_CSR_HYST_0                (0x1UL << COMP_CSR_HYST_Pos)            /*!< 0x00010000 */
9348 #define COMP_CSR_HYST_1                (0x2UL << COMP_CSR_HYST_Pos)            /*!< 0x00020000 */
9349 #define COMP_CSR_PWRMODE_Pos           (18U)
9350 #define COMP_CSR_PWRMODE_Msk           (0x3UL << COMP_CSR_PWRMODE_Pos)         /*!< 0x000C0000 */
9351 #define COMP_CSR_PWRMODE               COMP_CSR_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator */
9352 #define COMP_CSR_PWRMODE_0             (0x1UL << COMP_CSR_PWRMODE_Pos)         /*!< 0x00010000 */
9353 #define COMP_CSR_PWRMODE_1             (0x2UL << COMP_CSR_PWRMODE_Pos)         /*!< 0x00020000 */
9354 #define COMP_CSR_BLANKSEL_Pos          (20U)
9355 #define COMP_CSR_BLANKSEL_Msk          (0x1FUL << COMP_CSR_BLANKSEL_Pos)       /*!< 0x01F00000 */
9356 #define COMP_CSR_BLANKSEL              COMP_CSR_BLANKSEL_Msk                   /*!< COMPx blanking source selection bits */
9357 #define COMP_CSR_BLANKSEL_0            (0x1UL << COMP_CSR_BLANKSEL_Pos)        /*!< 0x00100000 */
9358 #define COMP_CSR_BLANKSEL_1            (0x2UL << COMP_CSR_BLANKSEL_Pos)        /*!< 0x00200000 */
9359 #define COMP_CSR_BLANKSEL_2            (0x4UL << COMP_CSR_BLANKSEL_Pos)        /*!< 0x00400000 */
9360 #define COMP_CSR_BLANKSEL_3            (0x8UL << COMP_CSR_BLANKSEL_Pos)        /*!< 0x00800000 */
9361 #define COMP_CSR_BLANKSEL_4            (0x10UL << COMP_CSR_BLANKSEL_Pos)       /*!< 0x01000000 */
9362 #define COMP_CSR_VALUE_Pos             (30U)
9363 #define COMP_CSR_VALUE_Msk             (0x1UL << COMP_CSR_VALUE_Pos)           /*!< 0x04000000 */
9364 #define COMP_CSR_VALUE                 COMP_CSR_VALUE_Msk                      /*!< Comparator output level */
9365 #define COMP_CSR_LOCK_Pos              (31U)
9366 #define COMP_CSR_LOCK_Msk              (0x1UL << COMP_CSR_LOCK_Pos)            /*!< 0x80000000 */
9367 #define COMP_CSR_LOCK                  COMP_CSR_LOCK_Msk                       /*!< COMPx Lock Bit */
9368 
9369 /******************************************************************************/
9370 /*                                                                            */
9371 /*                          Touch Sensing Controller (TSC)                    */
9372 /*                                                                            */
9373 /******************************************************************************/
9374 /*******************  Bit definition for TSC_CR register  *********************/
9375 #define TSC_CR_TSCE_Pos          (0U)
9376 #define TSC_CR_TSCE_Msk          (0x1UL << TSC_CR_TSCE_Pos)                    /*!< 0x00000001 */
9377 #define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
9378 #define TSC_CR_START_Pos         (1U)
9379 #define TSC_CR_START_Msk         (0x1UL << TSC_CR_START_Pos)                   /*!< 0x00000002 */
9380 #define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
9381 #define TSC_CR_AM_Pos            (2U)
9382 #define TSC_CR_AM_Msk            (0x1UL << TSC_CR_AM_Pos)                      /*!< 0x00000004 */
9383 #define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
9384 #define TSC_CR_SYNCPOL_Pos       (3U)
9385 #define TSC_CR_SYNCPOL_Msk       (0x1UL << TSC_CR_SYNCPOL_Pos)                 /*!< 0x00000008 */
9386 #define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
9387 #define TSC_CR_IODEF_Pos         (4U)
9388 #define TSC_CR_IODEF_Msk         (0x1UL << TSC_CR_IODEF_Pos)                   /*!< 0x00000010 */
9389 #define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
9390 
9391 #define TSC_CR_MCV_Pos           (5U)
9392 #define TSC_CR_MCV_Msk           (0x7UL << TSC_CR_MCV_Pos)                     /*!< 0x000000E0 */
9393 #define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
9394 #define TSC_CR_MCV_0             (0x1UL << TSC_CR_MCV_Pos)                     /*!< 0x00000020 */
9395 #define TSC_CR_MCV_1             (0x2UL << TSC_CR_MCV_Pos)                     /*!< 0x00000040 */
9396 #define TSC_CR_MCV_2             (0x4UL << TSC_CR_MCV_Pos)                     /*!< 0x00000080 */
9397 
9398 #define TSC_CR_PGPSC_Pos         (12U)
9399 #define TSC_CR_PGPSC_Msk         (0x7UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00007000 */
9400 #define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
9401 #define TSC_CR_PGPSC_0           (0x1UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00001000 */
9402 #define TSC_CR_PGPSC_1           (0x2UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00002000 */
9403 #define TSC_CR_PGPSC_2           (0x4UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00004000 */
9404 
9405 #define TSC_CR_SSPSC_Pos         (15U)
9406 #define TSC_CR_SSPSC_Msk         (0x1UL << TSC_CR_SSPSC_Pos)                   /*!< 0x00008000 */
9407 #define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
9408 #define TSC_CR_SSE_Pos           (16U)
9409 #define TSC_CR_SSE_Msk           (0x1UL << TSC_CR_SSE_Pos)                     /*!< 0x00010000 */
9410 #define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
9411 
9412 #define TSC_CR_SSD_Pos           (17U)
9413 #define TSC_CR_SSD_Msk           (0x7FUL << TSC_CR_SSD_Pos)                    /*!< 0x00FE0000 */
9414 #define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
9415 #define TSC_CR_SSD_0             (0x01UL << TSC_CR_SSD_Pos)                    /*!< 0x00020000 */
9416 #define TSC_CR_SSD_1             (0x02UL << TSC_CR_SSD_Pos)                    /*!< 0x00040000 */
9417 #define TSC_CR_SSD_2             (0x04UL << TSC_CR_SSD_Pos)                    /*!< 0x00080000 */
9418 #define TSC_CR_SSD_3             (0x08UL << TSC_CR_SSD_Pos)                    /*!< 0x00100000 */
9419 #define TSC_CR_SSD_4             (0x10UL << TSC_CR_SSD_Pos)                    /*!< 0x00200000 */
9420 #define TSC_CR_SSD_5             (0x20UL << TSC_CR_SSD_Pos)                    /*!< 0x00400000 */
9421 #define TSC_CR_SSD_6             (0x40UL << TSC_CR_SSD_Pos)                    /*!< 0x00800000 */
9422 
9423 #define TSC_CR_CTPL_Pos          (24U)
9424 #define TSC_CR_CTPL_Msk          (0xFUL << TSC_CR_CTPL_Pos)                    /*!< 0x0F000000 */
9425 #define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
9426 #define TSC_CR_CTPL_0            (0x1UL << TSC_CR_CTPL_Pos)                    /*!< 0x01000000 */
9427 #define TSC_CR_CTPL_1            (0x2UL << TSC_CR_CTPL_Pos)                    /*!< 0x02000000 */
9428 #define TSC_CR_CTPL_2            (0x4UL << TSC_CR_CTPL_Pos)                    /*!< 0x04000000 */
9429 #define TSC_CR_CTPL_3            (0x8UL << TSC_CR_CTPL_Pos)                    /*!< 0x08000000 */
9430 
9431 #define TSC_CR_CTPH_Pos          (28U)
9432 #define TSC_CR_CTPH_Msk          (0xFUL << TSC_CR_CTPH_Pos)                    /*!< 0xF0000000 */
9433 #define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
9434 #define TSC_CR_CTPH_0            (0x1UL << TSC_CR_CTPH_Pos)                    /*!< 0x10000000 */
9435 #define TSC_CR_CTPH_1            (0x2UL << TSC_CR_CTPH_Pos)                    /*!< 0x20000000 */
9436 #define TSC_CR_CTPH_2            (0x4UL << TSC_CR_CTPH_Pos)                    /*!< 0x40000000 */
9437 #define TSC_CR_CTPH_3            (0x8UL << TSC_CR_CTPH_Pos)                    /*!< 0x80000000 */
9438 
9439 /*******************  Bit definition for TSC_IER register  ********************/
9440 #define TSC_IER_EOAIE_Pos        (0U)
9441 #define TSC_IER_EOAIE_Msk        (0x1UL << TSC_IER_EOAIE_Pos)                  /*!< 0x00000001 */
9442 #define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
9443 #define TSC_IER_MCEIE_Pos        (1U)
9444 #define TSC_IER_MCEIE_Msk        (0x1UL << TSC_IER_MCEIE_Pos)                  /*!< 0x00000002 */
9445 #define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
9446 
9447 /*******************  Bit definition for TSC_ICR register  ********************/
9448 #define TSC_ICR_EOAIC_Pos        (0U)
9449 #define TSC_ICR_EOAIC_Msk        (0x1UL << TSC_ICR_EOAIC_Pos)                  /*!< 0x00000001 */
9450 #define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
9451 #define TSC_ICR_MCEIC_Pos        (1U)
9452 #define TSC_ICR_MCEIC_Msk        (0x1UL << TSC_ICR_MCEIC_Pos)                  /*!< 0x00000002 */
9453 #define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
9454 
9455 /*******************  Bit definition for TSC_ISR register  ********************/
9456 #define TSC_ISR_EOAF_Pos         (0U)
9457 #define TSC_ISR_EOAF_Msk         (0x1UL << TSC_ISR_EOAF_Pos)                   /*!< 0x00000001 */
9458 #define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
9459 #define TSC_ISR_MCEF_Pos         (1U)
9460 #define TSC_ISR_MCEF_Msk         (0x1UL << TSC_ISR_MCEF_Pos)                   /*!< 0x00000002 */
9461 #define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
9462 
9463 /*******************  Bit definition for TSC_IOHCR register  ******************/
9464 #define TSC_IOHCR_G1_IO1_Pos     (0U)
9465 #define TSC_IOHCR_G1_IO1_Msk     (0x1UL << TSC_IOHCR_G1_IO1_Pos)               /*!< 0x00000001 */
9466 #define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
9467 #define TSC_IOHCR_G1_IO2_Pos     (1U)
9468 #define TSC_IOHCR_G1_IO2_Msk     (0x1UL << TSC_IOHCR_G1_IO2_Pos)               /*!< 0x00000002 */
9469 #define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
9470 #define TSC_IOHCR_G1_IO3_Pos     (2U)
9471 #define TSC_IOHCR_G1_IO3_Msk     (0x1UL << TSC_IOHCR_G1_IO3_Pos)               /*!< 0x00000004 */
9472 #define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
9473 #define TSC_IOHCR_G1_IO4_Pos     (3U)
9474 #define TSC_IOHCR_G1_IO4_Msk     (0x1UL << TSC_IOHCR_G1_IO4_Pos)               /*!< 0x00000008 */
9475 #define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
9476 #define TSC_IOHCR_G2_IO1_Pos     (4U)
9477 #define TSC_IOHCR_G2_IO1_Msk     (0x1UL << TSC_IOHCR_G2_IO1_Pos)               /*!< 0x00000010 */
9478 #define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
9479 #define TSC_IOHCR_G2_IO2_Pos     (5U)
9480 #define TSC_IOHCR_G2_IO2_Msk     (0x1UL << TSC_IOHCR_G2_IO2_Pos)               /*!< 0x00000020 */
9481 #define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
9482 #define TSC_IOHCR_G2_IO3_Pos     (6U)
9483 #define TSC_IOHCR_G2_IO3_Msk     (0x1UL << TSC_IOHCR_G2_IO3_Pos)               /*!< 0x00000040 */
9484 #define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
9485 #define TSC_IOHCR_G2_IO4_Pos     (7U)
9486 #define TSC_IOHCR_G2_IO4_Msk     (0x1UL << TSC_IOHCR_G2_IO4_Pos)               /*!< 0x00000080 */
9487 #define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
9488 #define TSC_IOHCR_G3_IO1_Pos     (8U)
9489 #define TSC_IOHCR_G3_IO1_Msk     (0x1UL << TSC_IOHCR_G3_IO1_Pos)               /*!< 0x00000100 */
9490 #define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
9491 #define TSC_IOHCR_G3_IO2_Pos     (9U)
9492 #define TSC_IOHCR_G3_IO2_Msk     (0x1UL << TSC_IOHCR_G3_IO2_Pos)               /*!< 0x00000200 */
9493 #define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
9494 #define TSC_IOHCR_G3_IO3_Pos     (10U)
9495 #define TSC_IOHCR_G3_IO3_Msk     (0x1UL << TSC_IOHCR_G3_IO3_Pos)               /*!< 0x00000400 */
9496 #define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
9497 #define TSC_IOHCR_G3_IO4_Pos     (11U)
9498 #define TSC_IOHCR_G3_IO4_Msk     (0x1UL << TSC_IOHCR_G3_IO4_Pos)               /*!< 0x00000800 */
9499 #define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
9500 #define TSC_IOHCR_G4_IO1_Pos     (12U)
9501 #define TSC_IOHCR_G4_IO1_Msk     (0x1UL << TSC_IOHCR_G4_IO1_Pos)               /*!< 0x00001000 */
9502 #define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
9503 #define TSC_IOHCR_G4_IO2_Pos     (13U)
9504 #define TSC_IOHCR_G4_IO2_Msk     (0x1UL << TSC_IOHCR_G4_IO2_Pos)               /*!< 0x00002000 */
9505 #define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
9506 #define TSC_IOHCR_G4_IO3_Pos     (14U)
9507 #define TSC_IOHCR_G4_IO3_Msk     (0x1UL << TSC_IOHCR_G4_IO3_Pos)               /*!< 0x00004000 */
9508 #define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
9509 #define TSC_IOHCR_G4_IO4_Pos     (15U)
9510 #define TSC_IOHCR_G4_IO4_Msk     (0x1UL << TSC_IOHCR_G4_IO4_Pos)               /*!< 0x00008000 */
9511 #define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
9512 #define TSC_IOHCR_G5_IO1_Pos     (16U)
9513 #define TSC_IOHCR_G5_IO1_Msk     (0x1UL << TSC_IOHCR_G5_IO1_Pos)               /*!< 0x00010000 */
9514 #define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
9515 #define TSC_IOHCR_G5_IO2_Pos     (17U)
9516 #define TSC_IOHCR_G5_IO2_Msk     (0x1UL << TSC_IOHCR_G5_IO2_Pos)               /*!< 0x00020000 */
9517 #define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
9518 #define TSC_IOHCR_G5_IO3_Pos     (18U)
9519 #define TSC_IOHCR_G5_IO3_Msk     (0x1UL << TSC_IOHCR_G5_IO3_Pos)               /*!< 0x00040000 */
9520 #define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
9521 #define TSC_IOHCR_G5_IO4_Pos     (19U)
9522 #define TSC_IOHCR_G5_IO4_Msk     (0x1UL << TSC_IOHCR_G5_IO4_Pos)               /*!< 0x00080000 */
9523 #define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
9524 #define TSC_IOHCR_G6_IO1_Pos     (20U)
9525 #define TSC_IOHCR_G6_IO1_Msk     (0x1UL << TSC_IOHCR_G6_IO1_Pos)               /*!< 0x00100000 */
9526 #define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
9527 #define TSC_IOHCR_G6_IO2_Pos     (21U)
9528 #define TSC_IOHCR_G6_IO2_Msk     (0x1UL << TSC_IOHCR_G6_IO2_Pos)               /*!< 0x00200000 */
9529 #define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
9530 #define TSC_IOHCR_G6_IO3_Pos     (22U)
9531 #define TSC_IOHCR_G6_IO3_Msk     (0x1UL << TSC_IOHCR_G6_IO3_Pos)               /*!< 0x00400000 */
9532 #define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
9533 #define TSC_IOHCR_G6_IO4_Pos     (23U)
9534 #define TSC_IOHCR_G6_IO4_Msk     (0x1UL << TSC_IOHCR_G6_IO4_Pos)               /*!< 0x00800000 */
9535 #define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
9536 #define TSC_IOHCR_G7_IO1_Pos     (24U)
9537 #define TSC_IOHCR_G7_IO1_Msk     (0x1UL << TSC_IOHCR_G7_IO1_Pos)               /*!< 0x01000000 */
9538 #define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
9539 #define TSC_IOHCR_G7_IO2_Pos     (25U)
9540 #define TSC_IOHCR_G7_IO2_Msk     (0x1UL << TSC_IOHCR_G7_IO2_Pos)               /*!< 0x02000000 */
9541 #define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
9542 #define TSC_IOHCR_G7_IO3_Pos     (26U)
9543 #define TSC_IOHCR_G7_IO3_Msk     (0x1UL << TSC_IOHCR_G7_IO3_Pos)               /*!< 0x04000000 */
9544 #define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
9545 #define TSC_IOHCR_G7_IO4_Pos     (27U)
9546 #define TSC_IOHCR_G7_IO4_Msk     (0x1UL << TSC_IOHCR_G7_IO4_Pos)               /*!< 0x08000000 */
9547 #define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
9548 
9549 /*******************  Bit definition for TSC_IOASCR register  *****************/
9550 #define TSC_IOASCR_G1_IO1_Pos    (0U)
9551 #define TSC_IOASCR_G1_IO1_Msk    (0x1UL << TSC_IOASCR_G1_IO1_Pos)              /*!< 0x00000001 */
9552 #define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
9553 #define TSC_IOASCR_G1_IO2_Pos    (1U)
9554 #define TSC_IOASCR_G1_IO2_Msk    (0x1UL << TSC_IOASCR_G1_IO2_Pos)              /*!< 0x00000002 */
9555 #define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
9556 #define TSC_IOASCR_G1_IO3_Pos    (2U)
9557 #define TSC_IOASCR_G1_IO3_Msk    (0x1UL << TSC_IOASCR_G1_IO3_Pos)              /*!< 0x00000004 */
9558 #define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
9559 #define TSC_IOASCR_G1_IO4_Pos    (3U)
9560 #define TSC_IOASCR_G1_IO4_Msk    (0x1UL << TSC_IOASCR_G1_IO4_Pos)              /*!< 0x00000008 */
9561 #define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
9562 #define TSC_IOASCR_G2_IO1_Pos    (4U)
9563 #define TSC_IOASCR_G2_IO1_Msk    (0x1UL << TSC_IOASCR_G2_IO1_Pos)              /*!< 0x00000010 */
9564 #define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
9565 #define TSC_IOASCR_G2_IO2_Pos    (5U)
9566 #define TSC_IOASCR_G2_IO2_Msk    (0x1UL << TSC_IOASCR_G2_IO2_Pos)              /*!< 0x00000020 */
9567 #define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
9568 #define TSC_IOASCR_G2_IO3_Pos    (6U)
9569 #define TSC_IOASCR_G2_IO3_Msk    (0x1UL << TSC_IOASCR_G2_IO3_Pos)              /*!< 0x00000040 */
9570 #define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
9571 #define TSC_IOASCR_G2_IO4_Pos    (7U)
9572 #define TSC_IOASCR_G2_IO4_Msk    (0x1UL << TSC_IOASCR_G2_IO4_Pos)              /*!< 0x00000080 */
9573 #define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
9574 #define TSC_IOASCR_G3_IO1_Pos    (8U)
9575 #define TSC_IOASCR_G3_IO1_Msk    (0x1UL << TSC_IOASCR_G3_IO1_Pos)              /*!< 0x00000100 */
9576 #define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
9577 #define TSC_IOASCR_G3_IO2_Pos    (9U)
9578 #define TSC_IOASCR_G3_IO2_Msk    (0x1UL << TSC_IOASCR_G3_IO2_Pos)              /*!< 0x00000200 */
9579 #define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
9580 #define TSC_IOASCR_G3_IO3_Pos    (10U)
9581 #define TSC_IOASCR_G3_IO3_Msk    (0x1UL << TSC_IOASCR_G3_IO3_Pos)              /*!< 0x00000400 */
9582 #define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
9583 #define TSC_IOASCR_G3_IO4_Pos    (11U)
9584 #define TSC_IOASCR_G3_IO4_Msk    (0x1UL << TSC_IOASCR_G3_IO4_Pos)              /*!< 0x00000800 */
9585 #define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
9586 #define TSC_IOASCR_G4_IO1_Pos    (12U)
9587 #define TSC_IOASCR_G4_IO1_Msk    (0x1UL << TSC_IOASCR_G4_IO1_Pos)              /*!< 0x00001000 */
9588 #define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
9589 #define TSC_IOASCR_G4_IO2_Pos    (13U)
9590 #define TSC_IOASCR_G4_IO2_Msk    (0x1UL << TSC_IOASCR_G4_IO2_Pos)              /*!< 0x00002000 */
9591 #define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
9592 #define TSC_IOASCR_G4_IO3_Pos    (14U)
9593 #define TSC_IOASCR_G4_IO3_Msk    (0x1UL << TSC_IOASCR_G4_IO3_Pos)              /*!< 0x00004000 */
9594 #define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
9595 #define TSC_IOASCR_G4_IO4_Pos    (15U)
9596 #define TSC_IOASCR_G4_IO4_Msk    (0x1UL << TSC_IOASCR_G4_IO4_Pos)              /*!< 0x00008000 */
9597 #define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
9598 #define TSC_IOASCR_G5_IO1_Pos    (16U)
9599 #define TSC_IOASCR_G5_IO1_Msk    (0x1UL << TSC_IOASCR_G5_IO1_Pos)              /*!< 0x00010000 */
9600 #define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
9601 #define TSC_IOASCR_G5_IO2_Pos    (17U)
9602 #define TSC_IOASCR_G5_IO2_Msk    (0x1UL << TSC_IOASCR_G5_IO2_Pos)              /*!< 0x00020000 */
9603 #define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
9604 #define TSC_IOASCR_G5_IO3_Pos    (18U)
9605 #define TSC_IOASCR_G5_IO3_Msk    (0x1UL << TSC_IOASCR_G5_IO3_Pos)              /*!< 0x00040000 */
9606 #define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
9607 #define TSC_IOASCR_G5_IO4_Pos    (19U)
9608 #define TSC_IOASCR_G5_IO4_Msk    (0x1UL << TSC_IOASCR_G5_IO4_Pos)              /*!< 0x00080000 */
9609 #define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
9610 #define TSC_IOASCR_G6_IO1_Pos    (20U)
9611 #define TSC_IOASCR_G6_IO1_Msk    (0x1UL << TSC_IOASCR_G6_IO1_Pos)              /*!< 0x00100000 */
9612 #define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
9613 #define TSC_IOASCR_G6_IO2_Pos    (21U)
9614 #define TSC_IOASCR_G6_IO2_Msk    (0x1UL << TSC_IOASCR_G6_IO2_Pos)              /*!< 0x00200000 */
9615 #define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
9616 #define TSC_IOASCR_G6_IO3_Pos    (22U)
9617 #define TSC_IOASCR_G6_IO3_Msk    (0x1UL << TSC_IOASCR_G6_IO3_Pos)              /*!< 0x00400000 */
9618 #define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
9619 #define TSC_IOASCR_G6_IO4_Pos    (23U)
9620 #define TSC_IOASCR_G6_IO4_Msk    (0x1UL << TSC_IOASCR_G6_IO4_Pos)              /*!< 0x00800000 */
9621 #define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
9622 #define TSC_IOASCR_G7_IO1_Pos    (24U)
9623 #define TSC_IOASCR_G7_IO1_Msk    (0x1UL << TSC_IOASCR_G7_IO1_Pos)              /*!< 0x01000000 */
9624 #define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
9625 #define TSC_IOASCR_G7_IO2_Pos    (25U)
9626 #define TSC_IOASCR_G7_IO2_Msk    (0x1UL << TSC_IOASCR_G7_IO2_Pos)              /*!< 0x02000000 */
9627 #define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
9628 #define TSC_IOASCR_G7_IO3_Pos    (26U)
9629 #define TSC_IOASCR_G7_IO3_Msk    (0x1UL << TSC_IOASCR_G7_IO3_Pos)              /*!< 0x04000000 */
9630 #define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
9631 #define TSC_IOASCR_G7_IO4_Pos    (27U)
9632 #define TSC_IOASCR_G7_IO4_Msk    (0x1UL << TSC_IOASCR_G7_IO4_Pos)              /*!< 0x08000000 */
9633 #define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
9634 
9635 /*******************  Bit definition for TSC_IOSCR register  ******************/
9636 #define TSC_IOSCR_G1_IO1_Pos     (0U)
9637 #define TSC_IOSCR_G1_IO1_Msk     (0x1UL << TSC_IOSCR_G1_IO1_Pos)               /*!< 0x00000001 */
9638 #define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
9639 #define TSC_IOSCR_G1_IO2_Pos     (1U)
9640 #define TSC_IOSCR_G1_IO2_Msk     (0x1UL << TSC_IOSCR_G1_IO2_Pos)               /*!< 0x00000002 */
9641 #define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
9642 #define TSC_IOSCR_G1_IO3_Pos     (2U)
9643 #define TSC_IOSCR_G1_IO3_Msk     (0x1UL << TSC_IOSCR_G1_IO3_Pos)               /*!< 0x00000004 */
9644 #define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
9645 #define TSC_IOSCR_G1_IO4_Pos     (3U)
9646 #define TSC_IOSCR_G1_IO4_Msk     (0x1UL << TSC_IOSCR_G1_IO4_Pos)               /*!< 0x00000008 */
9647 #define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
9648 #define TSC_IOSCR_G2_IO1_Pos     (4U)
9649 #define TSC_IOSCR_G2_IO1_Msk     (0x1UL << TSC_IOSCR_G2_IO1_Pos)               /*!< 0x00000010 */
9650 #define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
9651 #define TSC_IOSCR_G2_IO2_Pos     (5U)
9652 #define TSC_IOSCR_G2_IO2_Msk     (0x1UL << TSC_IOSCR_G2_IO2_Pos)               /*!< 0x00000020 */
9653 #define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
9654 #define TSC_IOSCR_G2_IO3_Pos     (6U)
9655 #define TSC_IOSCR_G2_IO3_Msk     (0x1UL << TSC_IOSCR_G2_IO3_Pos)               /*!< 0x00000040 */
9656 #define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
9657 #define TSC_IOSCR_G2_IO4_Pos     (7U)
9658 #define TSC_IOSCR_G2_IO4_Msk     (0x1UL << TSC_IOSCR_G2_IO4_Pos)               /*!< 0x00000080 */
9659 #define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
9660 #define TSC_IOSCR_G3_IO1_Pos     (8U)
9661 #define TSC_IOSCR_G3_IO1_Msk     (0x1UL << TSC_IOSCR_G3_IO1_Pos)               /*!< 0x00000100 */
9662 #define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
9663 #define TSC_IOSCR_G3_IO2_Pos     (9U)
9664 #define TSC_IOSCR_G3_IO2_Msk     (0x1UL << TSC_IOSCR_G3_IO2_Pos)               /*!< 0x00000200 */
9665 #define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
9666 #define TSC_IOSCR_G3_IO3_Pos     (10U)
9667 #define TSC_IOSCR_G3_IO3_Msk     (0x1UL << TSC_IOSCR_G3_IO3_Pos)               /*!< 0x00000400 */
9668 #define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
9669 #define TSC_IOSCR_G3_IO4_Pos     (11U)
9670 #define TSC_IOSCR_G3_IO4_Msk     (0x1UL << TSC_IOSCR_G3_IO4_Pos)               /*!< 0x00000800 */
9671 #define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
9672 #define TSC_IOSCR_G4_IO1_Pos     (12U)
9673 #define TSC_IOSCR_G4_IO1_Msk     (0x1UL << TSC_IOSCR_G4_IO1_Pos)               /*!< 0x00001000 */
9674 #define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
9675 #define TSC_IOSCR_G4_IO2_Pos     (13U)
9676 #define TSC_IOSCR_G4_IO2_Msk     (0x1UL << TSC_IOSCR_G4_IO2_Pos)               /*!< 0x00002000 */
9677 #define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
9678 #define TSC_IOSCR_G4_IO3_Pos     (14U)
9679 #define TSC_IOSCR_G4_IO3_Msk     (0x1UL << TSC_IOSCR_G4_IO3_Pos)               /*!< 0x00004000 */
9680 #define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
9681 #define TSC_IOSCR_G4_IO4_Pos     (15U)
9682 #define TSC_IOSCR_G4_IO4_Msk     (0x1UL << TSC_IOSCR_G4_IO4_Pos)               /*!< 0x00008000 */
9683 #define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
9684 #define TSC_IOSCR_G5_IO1_Pos     (16U)
9685 #define TSC_IOSCR_G5_IO1_Msk     (0x1UL << TSC_IOSCR_G5_IO1_Pos)               /*!< 0x00010000 */
9686 #define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
9687 #define TSC_IOSCR_G5_IO2_Pos     (17U)
9688 #define TSC_IOSCR_G5_IO2_Msk     (0x1UL << TSC_IOSCR_G5_IO2_Pos)               /*!< 0x00020000 */
9689 #define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
9690 #define TSC_IOSCR_G5_IO3_Pos     (18U)
9691 #define TSC_IOSCR_G5_IO3_Msk     (0x1UL << TSC_IOSCR_G5_IO3_Pos)               /*!< 0x00040000 */
9692 #define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
9693 #define TSC_IOSCR_G5_IO4_Pos     (19U)
9694 #define TSC_IOSCR_G5_IO4_Msk     (0x1UL << TSC_IOSCR_G5_IO4_Pos)               /*!< 0x00080000 */
9695 #define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
9696 #define TSC_IOSCR_G6_IO1_Pos     (20U)
9697 #define TSC_IOSCR_G6_IO1_Msk     (0x1UL << TSC_IOSCR_G6_IO1_Pos)               /*!< 0x00100000 */
9698 #define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
9699 #define TSC_IOSCR_G6_IO2_Pos     (21U)
9700 #define TSC_IOSCR_G6_IO2_Msk     (0x1UL << TSC_IOSCR_G6_IO2_Pos)               /*!< 0x00200000 */
9701 #define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
9702 #define TSC_IOSCR_G6_IO3_Pos     (22U)
9703 #define TSC_IOSCR_G6_IO3_Msk     (0x1UL << TSC_IOSCR_G6_IO3_Pos)               /*!< 0x00400000 */
9704 #define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
9705 #define TSC_IOSCR_G6_IO4_Pos     (23U)
9706 #define TSC_IOSCR_G6_IO4_Msk     (0x1UL << TSC_IOSCR_G6_IO4_Pos)               /*!< 0x00800000 */
9707 #define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
9708 #define TSC_IOSCR_G7_IO1_Pos     (24U)
9709 #define TSC_IOSCR_G7_IO1_Msk     (0x1UL << TSC_IOSCR_G7_IO1_Pos)               /*!< 0x01000000 */
9710 #define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
9711 #define TSC_IOSCR_G7_IO2_Pos     (25U)
9712 #define TSC_IOSCR_G7_IO2_Msk     (0x1UL << TSC_IOSCR_G7_IO2_Pos)               /*!< 0x02000000 */
9713 #define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
9714 #define TSC_IOSCR_G7_IO3_Pos     (26U)
9715 #define TSC_IOSCR_G7_IO3_Msk     (0x1UL << TSC_IOSCR_G7_IO3_Pos)               /*!< 0x04000000 */
9716 #define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
9717 #define TSC_IOSCR_G7_IO4_Pos     (27U)
9718 #define TSC_IOSCR_G7_IO4_Msk     (0x1UL << TSC_IOSCR_G7_IO4_Pos)               /*!< 0x08000000 */
9719 #define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
9720 
9721 /*******************  Bit definition for TSC_IOCCR register  ******************/
9722 #define TSC_IOCCR_G1_IO1_Pos     (0U)
9723 #define TSC_IOCCR_G1_IO1_Msk     (0x1UL << TSC_IOCCR_G1_IO1_Pos)               /*!< 0x00000001 */
9724 #define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
9725 #define TSC_IOCCR_G1_IO2_Pos     (1U)
9726 #define TSC_IOCCR_G1_IO2_Msk     (0x1UL << TSC_IOCCR_G1_IO2_Pos)               /*!< 0x00000002 */
9727 #define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
9728 #define TSC_IOCCR_G1_IO3_Pos     (2U)
9729 #define TSC_IOCCR_G1_IO3_Msk     (0x1UL << TSC_IOCCR_G1_IO3_Pos)               /*!< 0x00000004 */
9730 #define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
9731 #define TSC_IOCCR_G1_IO4_Pos     (3U)
9732 #define TSC_IOCCR_G1_IO4_Msk     (0x1UL << TSC_IOCCR_G1_IO4_Pos)               /*!< 0x00000008 */
9733 #define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
9734 #define TSC_IOCCR_G2_IO1_Pos     (4U)
9735 #define TSC_IOCCR_G2_IO1_Msk     (0x1UL << TSC_IOCCR_G2_IO1_Pos)               /*!< 0x00000010 */
9736 #define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
9737 #define TSC_IOCCR_G2_IO2_Pos     (5U)
9738 #define TSC_IOCCR_G2_IO2_Msk     (0x1UL << TSC_IOCCR_G2_IO2_Pos)               /*!< 0x00000020 */
9739 #define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
9740 #define TSC_IOCCR_G2_IO3_Pos     (6U)
9741 #define TSC_IOCCR_G2_IO3_Msk     (0x1UL << TSC_IOCCR_G2_IO3_Pos)               /*!< 0x00000040 */
9742 #define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
9743 #define TSC_IOCCR_G2_IO4_Pos     (7U)
9744 #define TSC_IOCCR_G2_IO4_Msk     (0x1UL << TSC_IOCCR_G2_IO4_Pos)               /*!< 0x00000080 */
9745 #define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
9746 #define TSC_IOCCR_G3_IO1_Pos     (8U)
9747 #define TSC_IOCCR_G3_IO1_Msk     (0x1UL << TSC_IOCCR_G3_IO1_Pos)               /*!< 0x00000100 */
9748 #define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
9749 #define TSC_IOCCR_G3_IO2_Pos     (9U)
9750 #define TSC_IOCCR_G3_IO2_Msk     (0x1UL << TSC_IOCCR_G3_IO2_Pos)               /*!< 0x00000200 */
9751 #define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
9752 #define TSC_IOCCR_G3_IO3_Pos     (10U)
9753 #define TSC_IOCCR_G3_IO3_Msk     (0x1UL << TSC_IOCCR_G3_IO3_Pos)               /*!< 0x00000400 */
9754 #define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
9755 #define TSC_IOCCR_G3_IO4_Pos     (11U)
9756 #define TSC_IOCCR_G3_IO4_Msk     (0x1UL << TSC_IOCCR_G3_IO4_Pos)               /*!< 0x00000800 */
9757 #define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
9758 #define TSC_IOCCR_G4_IO1_Pos     (12U)
9759 #define TSC_IOCCR_G4_IO1_Msk     (0x1UL << TSC_IOCCR_G4_IO1_Pos)               /*!< 0x00001000 */
9760 #define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
9761 #define TSC_IOCCR_G4_IO2_Pos     (13U)
9762 #define TSC_IOCCR_G4_IO2_Msk     (0x1UL << TSC_IOCCR_G4_IO2_Pos)               /*!< 0x00002000 */
9763 #define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
9764 #define TSC_IOCCR_G4_IO3_Pos     (14U)
9765 #define TSC_IOCCR_G4_IO3_Msk     (0x1UL << TSC_IOCCR_G4_IO3_Pos)               /*!< 0x00004000 */
9766 #define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
9767 #define TSC_IOCCR_G4_IO4_Pos     (15U)
9768 #define TSC_IOCCR_G4_IO4_Msk     (0x1UL << TSC_IOCCR_G4_IO4_Pos)               /*!< 0x00008000 */
9769 #define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
9770 #define TSC_IOCCR_G5_IO1_Pos     (16U)
9771 #define TSC_IOCCR_G5_IO1_Msk     (0x1UL << TSC_IOCCR_G5_IO1_Pos)               /*!< 0x00010000 */
9772 #define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
9773 #define TSC_IOCCR_G5_IO2_Pos     (17U)
9774 #define TSC_IOCCR_G5_IO2_Msk     (0x1UL << TSC_IOCCR_G5_IO2_Pos)               /*!< 0x00020000 */
9775 #define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
9776 #define TSC_IOCCR_G5_IO3_Pos     (18U)
9777 #define TSC_IOCCR_G5_IO3_Msk     (0x1UL << TSC_IOCCR_G5_IO3_Pos)               /*!< 0x00040000 */
9778 #define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
9779 #define TSC_IOCCR_G5_IO4_Pos     (19U)
9780 #define TSC_IOCCR_G5_IO4_Msk     (0x1UL << TSC_IOCCR_G5_IO4_Pos)               /*!< 0x00080000 */
9781 #define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
9782 #define TSC_IOCCR_G6_IO1_Pos     (20U)
9783 #define TSC_IOCCR_G6_IO1_Msk     (0x1UL << TSC_IOCCR_G6_IO1_Pos)               /*!< 0x00100000 */
9784 #define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
9785 #define TSC_IOCCR_G6_IO2_Pos     (21U)
9786 #define TSC_IOCCR_G6_IO2_Msk     (0x1UL << TSC_IOCCR_G6_IO2_Pos)               /*!< 0x00200000 */
9787 #define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
9788 #define TSC_IOCCR_G6_IO3_Pos     (22U)
9789 #define TSC_IOCCR_G6_IO3_Msk     (0x1UL << TSC_IOCCR_G6_IO3_Pos)               /*!< 0x00400000 */
9790 #define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
9791 #define TSC_IOCCR_G6_IO4_Pos     (23U)
9792 #define TSC_IOCCR_G6_IO4_Msk     (0x1UL << TSC_IOCCR_G6_IO4_Pos)               /*!< 0x00800000 */
9793 #define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
9794 #define TSC_IOCCR_G7_IO1_Pos     (24U)
9795 #define TSC_IOCCR_G7_IO1_Msk     (0x1UL << TSC_IOCCR_G7_IO1_Pos)               /*!< 0x01000000 */
9796 #define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
9797 #define TSC_IOCCR_G7_IO2_Pos     (25U)
9798 #define TSC_IOCCR_G7_IO2_Msk     (0x1UL << TSC_IOCCR_G7_IO2_Pos)               /*!< 0x02000000 */
9799 #define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
9800 #define TSC_IOCCR_G7_IO3_Pos     (26U)
9801 #define TSC_IOCCR_G7_IO3_Msk     (0x1UL << TSC_IOCCR_G7_IO3_Pos)               /*!< 0x04000000 */
9802 #define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
9803 #define TSC_IOCCR_G7_IO4_Pos     (27U)
9804 #define TSC_IOCCR_G7_IO4_Msk     (0x1UL << TSC_IOCCR_G7_IO4_Pos)               /*!< 0x08000000 */
9805 #define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
9806 
9807 /*******************  Bit definition for TSC_IOGCSR register  *****************/
9808 #define TSC_IOGCSR_G1E_Pos       (0U)
9809 #define TSC_IOGCSR_G1E_Msk       (0x1UL << TSC_IOGCSR_G1E_Pos)                 /*!< 0x00000001 */
9810 #define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
9811 #define TSC_IOGCSR_G2E_Pos       (1U)
9812 #define TSC_IOGCSR_G2E_Msk       (0x1UL << TSC_IOGCSR_G2E_Pos)                 /*!< 0x00000002 */
9813 #define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
9814 #define TSC_IOGCSR_G3E_Pos       (2U)
9815 #define TSC_IOGCSR_G3E_Msk       (0x1UL << TSC_IOGCSR_G3E_Pos)                 /*!< 0x00000004 */
9816 #define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
9817 #define TSC_IOGCSR_G4E_Pos       (3U)
9818 #define TSC_IOGCSR_G4E_Msk       (0x1UL << TSC_IOGCSR_G4E_Pos)                 /*!< 0x00000008 */
9819 #define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
9820 #define TSC_IOGCSR_G5E_Pos       (4U)
9821 #define TSC_IOGCSR_G5E_Msk       (0x1UL << TSC_IOGCSR_G5E_Pos)                 /*!< 0x00000010 */
9822 #define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
9823 #define TSC_IOGCSR_G6E_Pos       (5U)
9824 #define TSC_IOGCSR_G6E_Msk       (0x1UL << TSC_IOGCSR_G6E_Pos)                 /*!< 0x00000020 */
9825 #define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
9826 #define TSC_IOGCSR_G7E_Pos       (6U)
9827 #define TSC_IOGCSR_G7E_Msk       (0x1UL << TSC_IOGCSR_G7E_Pos)                 /*!< 0x00000040 */
9828 #define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
9829 #define TSC_IOGCSR_G1S_Pos       (16U)
9830 #define TSC_IOGCSR_G1S_Msk       (0x1UL << TSC_IOGCSR_G1S_Pos)                 /*!< 0x00010000 */
9831 #define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
9832 #define TSC_IOGCSR_G2S_Pos       (17U)
9833 #define TSC_IOGCSR_G2S_Msk       (0x1UL << TSC_IOGCSR_G2S_Pos)                 /*!< 0x00020000 */
9834 #define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
9835 #define TSC_IOGCSR_G3S_Pos       (18U)
9836 #define TSC_IOGCSR_G3S_Msk       (0x1UL << TSC_IOGCSR_G3S_Pos)                 /*!< 0x00040000 */
9837 #define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
9838 #define TSC_IOGCSR_G4S_Pos       (19U)
9839 #define TSC_IOGCSR_G4S_Msk       (0x1UL << TSC_IOGCSR_G4S_Pos)                 /*!< 0x00080000 */
9840 #define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
9841 #define TSC_IOGCSR_G5S_Pos       (20U)
9842 #define TSC_IOGCSR_G5S_Msk       (0x1UL << TSC_IOGCSR_G5S_Pos)                 /*!< 0x00100000 */
9843 #define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
9844 #define TSC_IOGCSR_G6S_Pos       (21U)
9845 #define TSC_IOGCSR_G6S_Msk       (0x1UL << TSC_IOGCSR_G6S_Pos)                 /*!< 0x00200000 */
9846 #define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
9847 #define TSC_IOGCSR_G7S_Pos       (22U)
9848 #define TSC_IOGCSR_G7S_Msk       (0x1UL << TSC_IOGCSR_G7S_Pos)                 /*!< 0x00400000 */
9849 #define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
9850 
9851 /*******************  Bit definition for TSC_IOGXCR register  *****************/
9852 #define TSC_IOGXCR_CNT_Pos       (0U)
9853 #define TSC_IOGXCR_CNT_Msk       (0x3FFFUL << TSC_IOGXCR_CNT_Pos)              /*!< 0x00003FFF */
9854 #define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
9855 
9856 /******************************************************************************/
9857 /*                                                                            */
9858 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
9859 /*                                                                            */
9860 /******************************************************************************/
9861 /******************  Bit definition for USART_CR1 register  *******************/
9862 #define USART_CR1_UE_Pos                (0U)
9863 #define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */
9864 #define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */
9865 #define USART_CR1_UESM_Pos              (1U)
9866 #define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */
9867 #define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */
9868 #define USART_CR1_RE_Pos                (2U)
9869 #define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */
9870 #define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */
9871 #define USART_CR1_TE_Pos                (3U)
9872 #define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */
9873 #define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */
9874 #define USART_CR1_IDLEIE_Pos            (4U)
9875 #define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */
9876 #define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */
9877 #define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)
9878 #define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
9879 #define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
9880 #define USART_CR1_TCIE_Pos              (6U)
9881 #define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */
9882 #define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */
9883 #define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)
9884 #define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */
9885 #define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */
9886 #define USART_CR1_PEIE_Pos              (8U)
9887 #define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */
9888 #define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */
9889 #define USART_CR1_PS_Pos                (9U)
9890 #define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */
9891 #define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */
9892 #define USART_CR1_PCE_Pos               (10U)
9893 #define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */
9894 #define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */
9895 #define USART_CR1_WAKE_Pos              (11U)
9896 #define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */
9897 #define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */
9898 #define USART_CR1_M_Pos                 (12U)
9899 #define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */
9900 #define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */
9901 #define USART_CR1_M0_Pos                (12U)
9902 #define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */
9903 #define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */
9904 #define USART_CR1_MME_Pos               (13U)
9905 #define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */
9906 #define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */
9907 #define USART_CR1_CMIE_Pos              (14U)
9908 #define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */
9909 #define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */
9910 #define USART_CR1_OVER8_Pos             (15U)
9911 #define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */
9912 #define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */
9913 #define USART_CR1_DEDT_Pos              (16U)
9914 #define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */
9915 #define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
9916 #define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */
9917 #define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */
9918 #define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */
9919 #define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */
9920 #define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */
9921 #define USART_CR1_DEAT_Pos              (21U)
9922 #define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */
9923 #define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
9924 #define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */
9925 #define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */
9926 #define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */
9927 #define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */
9928 #define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */
9929 #define USART_CR1_RTOIE_Pos             (26U)
9930 #define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */
9931 #define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */
9932 #define USART_CR1_EOBIE_Pos             (27U)
9933 #define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */
9934 #define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */
9935 #define USART_CR1_M1_Pos                (28U)
9936 #define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */
9937 #define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */
9938 #define USART_CR1_FIFOEN_Pos            (29U)
9939 #define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */
9940 #define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */
9941 #define USART_CR1_TXFEIE_Pos            (30U)
9942 #define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */
9943 #define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */
9944 #define USART_CR1_RXFFIE_Pos            (31U)
9945 #define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */
9946 #define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */
9947 
9948 /* Legacy define */
9949 #define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE
9950 #define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE
9951 
9952 /******************  Bit definition for USART_CR2 register  *******************/
9953 #define USART_CR2_SLVEN_Pos             (0U)
9954 #define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */
9955 #define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */
9956 #define USART_CR2_DIS_NSS_Pos           (3U)
9957 #define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */
9958 #define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */
9959 #define USART_CR2_ADDM7_Pos             (4U)
9960 #define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */
9961 #define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */
9962 #define USART_CR2_LBDL_Pos              (5U)
9963 #define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */
9964 #define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */
9965 #define USART_CR2_LBDIE_Pos             (6U)
9966 #define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */
9967 #define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */
9968 #define USART_CR2_LBCL_Pos              (8U)
9969 #define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */
9970 #define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */
9971 #define USART_CR2_CPHA_Pos              (9U)
9972 #define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */
9973 #define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */
9974 #define USART_CR2_CPOL_Pos              (10U)
9975 #define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */
9976 #define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */
9977 #define USART_CR2_CLKEN_Pos             (11U)
9978 #define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */
9979 #define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */
9980 #define USART_CR2_STOP_Pos              (12U)
9981 #define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */
9982 #define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */
9983 #define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */
9984 #define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */
9985 #define USART_CR2_LINEN_Pos             (14U)
9986 #define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */
9987 #define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */
9988 #define USART_CR2_SWAP_Pos              (15U)
9989 #define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */
9990 #define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */
9991 #define USART_CR2_RXINV_Pos             (16U)
9992 #define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */
9993 #define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */
9994 #define USART_CR2_TXINV_Pos             (17U)
9995 #define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */
9996 #define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */
9997 #define USART_CR2_DATAINV_Pos           (18U)
9998 #define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */
9999 #define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */
10000 #define USART_CR2_MSBFIRST_Pos          (19U)
10001 #define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */
10002 #define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */
10003 #define USART_CR2_ABREN_Pos             (20U)
10004 #define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */
10005 #define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/
10006 #define USART_CR2_ABRMODE_Pos           (21U)
10007 #define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */
10008 #define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
10009 #define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */
10010 #define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */
10011 #define USART_CR2_RTOEN_Pos             (23U)
10012 #define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */
10013 #define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */
10014 #define USART_CR2_ADD_Pos               (24U)
10015 #define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */
10016 #define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */
10017 
10018 /******************  Bit definition for USART_CR3 register  *******************/
10019 #define USART_CR3_EIE_Pos               (0U)
10020 #define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */
10021 #define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */
10022 #define USART_CR3_IREN_Pos              (1U)
10023 #define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */
10024 #define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */
10025 #define USART_CR3_IRLP_Pos              (2U)
10026 #define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */
10027 #define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */
10028 #define USART_CR3_HDSEL_Pos             (3U)
10029 #define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */
10030 #define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */
10031 #define USART_CR3_NACK_Pos              (4U)
10032 #define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */
10033 #define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */
10034 #define USART_CR3_SCEN_Pos              (5U)
10035 #define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */
10036 #define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */
10037 #define USART_CR3_DMAR_Pos              (6U)
10038 #define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */
10039 #define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */
10040 #define USART_CR3_DMAT_Pos              (7U)
10041 #define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */
10042 #define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */
10043 #define USART_CR3_RTSE_Pos              (8U)
10044 #define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */
10045 #define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */
10046 #define USART_CR3_CTSE_Pos              (9U)
10047 #define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */
10048 #define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */
10049 #define USART_CR3_CTSIE_Pos             (10U)
10050 #define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */
10051 #define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */
10052 #define USART_CR3_ONEBIT_Pos            (11U)
10053 #define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */
10054 #define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */
10055 #define USART_CR3_OVRDIS_Pos            (12U)
10056 #define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */
10057 #define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */
10058 #define USART_CR3_DDRE_Pos              (13U)
10059 #define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */
10060 #define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */
10061 #define USART_CR3_DEM_Pos               (14U)
10062 #define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */
10063 #define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */
10064 #define USART_CR3_DEP_Pos               (15U)
10065 #define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */
10066 #define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */
10067 #define USART_CR3_SCARCNT_Pos           (17U)
10068 #define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */
10069 #define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
10070 #define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */
10071 #define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */
10072 #define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */
10073 #define USART_CR3_WUS_Pos               (20U)
10074 #define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */
10075 #define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
10076 #define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */
10077 #define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */
10078 #define USART_CR3_WUFIE_Pos             (22U)
10079 #define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */
10080 #define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */
10081 #define USART_CR3_TXFTIE_Pos            (23U)
10082 #define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */
10083 #define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */
10084 #define USART_CR3_TCBGTIE_Pos           (24U)
10085 #define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */
10086 #define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */
10087 #define USART_CR3_RXFTCFG_Pos           (25U)
10088 #define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */
10089 #define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */
10090 #define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */
10091 #define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */
10092 #define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */
10093 #define USART_CR3_RXFTIE_Pos            (28U)
10094 #define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */
10095 #define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */
10096 #define USART_CR3_TXFTCFG_Pos           (29U)
10097 #define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */
10098 #define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */
10099 #define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */
10100 #define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */
10101 #define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */
10102 
10103 /******************  Bit definition for USART_BRR register  *******************/
10104 #define USART_BRR_DIV_FRACTION_Pos      (0U)
10105 #define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */
10106 #define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */
10107 #define USART_BRR_DIV_MANTISSA_Pos      (4U)
10108 #define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
10109 #define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */
10110 
10111 /******************  Bit definition for USART_GTPR register  ******************/
10112 #define USART_GTPR_PSC_Pos              (0U)
10113 #define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */
10114 #define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */
10115 #define USART_GTPR_GT_Pos               (8U)
10116 #define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */
10117 #define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */
10118 
10119 /*******************  Bit definition for USART_RTOR register  *****************/
10120 #define USART_RTOR_RTO_Pos              (0U)
10121 #define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */
10122 #define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */
10123 #define USART_RTOR_BLEN_Pos             (24U)
10124 #define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */
10125 #define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */
10126 
10127 /*******************  Bit definition for USART_RQR register  ******************/
10128 #define USART_RQR_ABRRQ_Pos             (0U)
10129 #define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */
10130 #define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */
10131 #define USART_RQR_SBKRQ_Pos             (1U)
10132 #define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */
10133 #define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */
10134 #define USART_RQR_MMRQ_Pos              (2U)
10135 #define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */
10136 #define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */
10137 #define USART_RQR_RXFRQ_Pos             (3U)
10138 #define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */
10139 #define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */
10140 #define USART_RQR_TXFRQ_Pos             (4U)
10141 #define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */
10142 #define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */
10143 
10144 /*******************  Bit definition for USART_ISR register  ******************/
10145 #define USART_ISR_PE_Pos                (0U)
10146 #define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */
10147 #define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */
10148 #define USART_ISR_FE_Pos                (1U)
10149 #define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */
10150 #define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */
10151 #define USART_ISR_NE_Pos                (2U)
10152 #define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */
10153 #define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */
10154 #define USART_ISR_ORE_Pos               (3U)
10155 #define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */
10156 #define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */
10157 #define USART_ISR_IDLE_Pos              (4U)
10158 #define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */
10159 #define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */
10160 #define USART_ISR_RXNE_RXFNE_Pos        (5U)
10161 #define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */
10162 #define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */
10163 #define USART_ISR_TC_Pos                (6U)
10164 #define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */
10165 #define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */
10166 #define USART_ISR_TXE_TXFNF_Pos         (7U)
10167 #define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */
10168 #define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
10169 #define USART_ISR_LBDF_Pos              (8U)
10170 #define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */
10171 #define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */
10172 #define USART_ISR_CTSIF_Pos             (9U)
10173 #define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */
10174 #define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */
10175 #define USART_ISR_CTS_Pos               (10U)
10176 #define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */
10177 #define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */
10178 #define USART_ISR_RTOF_Pos              (11U)
10179 #define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */
10180 #define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */
10181 #define USART_ISR_EOBF_Pos              (12U)
10182 #define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */
10183 #define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */
10184 #define USART_ISR_UDR_Pos               (13U)
10185 #define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */
10186 #define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */
10187 #define USART_ISR_ABRE_Pos              (14U)
10188 #define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */
10189 #define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */
10190 #define USART_ISR_ABRF_Pos              (15U)
10191 #define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */
10192 #define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */
10193 #define USART_ISR_BUSY_Pos              (16U)
10194 #define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */
10195 #define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */
10196 #define USART_ISR_CMF_Pos               (17U)
10197 #define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */
10198 #define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */
10199 #define USART_ISR_SBKF_Pos              (18U)
10200 #define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */
10201 #define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */
10202 #define USART_ISR_RWU_Pos               (19U)
10203 #define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */
10204 #define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */
10205 #define USART_ISR_WUF_Pos               (20U)
10206 #define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */
10207 #define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */
10208 #define USART_ISR_TEACK_Pos             (21U)
10209 #define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */
10210 #define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */
10211 #define USART_ISR_REACK_Pos             (22U)
10212 #define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */
10213 #define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */
10214 #define USART_ISR_TXFE_Pos              (23U)
10215 #define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */
10216 #define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */
10217 #define USART_ISR_RXFF_Pos              (24U)
10218 #define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */
10219 #define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */
10220 #define USART_ISR_TCBGT_Pos             (25U)
10221 #define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */
10222 #define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */
10223 #define USART_ISR_RXFT_Pos              (26U)
10224 #define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */
10225 #define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */
10226 #define USART_ISR_TXFT_Pos              (27U)
10227 #define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */
10228 #define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */
10229 
10230 /*******************  Bit definition for USART_ICR register  ******************/
10231 #define USART_ICR_PECF_Pos              (0U)
10232 #define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */
10233 #define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */
10234 #define USART_ICR_FECF_Pos              (1U)
10235 #define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */
10236 #define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */
10237 #define USART_ICR_NECF_Pos              (2U)
10238 #define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */
10239 #define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */
10240 #define USART_ICR_ORECF_Pos             (3U)
10241 #define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */
10242 #define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */
10243 #define USART_ICR_IDLECF_Pos            (4U)
10244 #define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */
10245 #define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */
10246 #define USART_ICR_TXFECF_Pos            (5U)
10247 #define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */
10248 #define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */
10249 #define USART_ICR_TCCF_Pos              (6U)
10250 #define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */
10251 #define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */
10252 #define USART_ICR_TCBGTCF_Pos           (7U)
10253 #define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */
10254 #define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */
10255 #define USART_ICR_LBDCF_Pos             (8U)
10256 #define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */
10257 #define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */
10258 #define USART_ICR_CTSCF_Pos             (9U)
10259 #define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */
10260 #define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */
10261 #define USART_ICR_RTOCF_Pos             (11U)
10262 #define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */
10263 #define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */
10264 #define USART_ICR_EOBCF_Pos             (12U)
10265 #define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */
10266 #define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */
10267 #define USART_ICR_UDRCF_Pos             (13U)
10268 #define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */
10269 #define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */
10270 #define USART_ICR_CMCF_Pos              (17U)
10271 #define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */
10272 #define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */
10273 #define USART_ICR_WUCF_Pos              (20U)
10274 #define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */
10275 #define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */
10276 
10277 /*******************  Bit definition for USART_RDR register  ******************/
10278 #define USART_RDR_RDR_Pos               (0U)
10279 #define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */
10280 #define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */
10281 
10282 /*******************  Bit definition for USART_TDR register  ******************/
10283 #define USART_TDR_TDR_Pos               (0U)
10284 #define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */
10285 #define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */
10286 
10287 /*******************  Bit definition for USART_PRESC register  ******************/
10288 #define USART_PRESC_PRESCALER_Pos       (0U)
10289 #define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */
10290 #define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */
10291 #define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */
10292 #define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */
10293 #define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */
10294 #define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */
10295 
10296 /******************************************************************************/
10297 /*                                                                            */
10298 /*                                 VREFBUF                                    */
10299 /*                                                                            */
10300 /******************************************************************************/
10301 /*******************  Bit definition for VREFBUF_CSR register  ****************/
10302 #define VREFBUF_CSR_ENVR_Pos    (0U)
10303 #define VREFBUF_CSR_ENVR_Msk    (0x1UL << VREFBUF_CSR_ENVR_Pos)                /*!< 0x00000001 */
10304 #define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                           /*!<Voltage reference buffer enable */
10305 #define VREFBUF_CSR_HIZ_Pos     (1U)
10306 #define VREFBUF_CSR_HIZ_Msk     (0x1UL << VREFBUF_CSR_HIZ_Pos)                 /*!< 0x00000002 */
10307 #define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                            /*!<High impedance mode             */
10308 #define VREFBUF_CSR_VRS_Pos     (2U)
10309 #define VREFBUF_CSR_VRS_Msk     (0x1UL << VREFBUF_CSR_VRS_Pos)                 /*!< 0x00000004 */
10310 #define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                            /*!<Voltage reference scale         */
10311 #define VREFBUF_CSR_VRR_Pos     (3U)
10312 #define VREFBUF_CSR_VRR_Msk     (0x1UL << VREFBUF_CSR_VRR_Pos)                 /*!< 0x00000008 */
10313 #define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                            /*!<Voltage reference buffer ready  */
10314 
10315 /*******************  Bit definition for VREFBUF_CCR register  ******************/
10316 #define VREFBUF_CCR_TRIM_Pos    (0U)
10317 #define VREFBUF_CCR_TRIM_Msk    (0x3FUL << VREFBUF_CCR_TRIM_Pos)               /*!< 0x0000003F */
10318 #define VREFBUF_CCR_TRIM        VREFBUF_CCR_TRIM_Msk                           /*!<TRIM[5:0] bits (Trimming code)  */
10319 
10320 /******************************************************************************/
10321 /*                                                                            */
10322 /*           Single Wire Protocol Master Interface (SWPMI)                    */
10323 /*                                                                            */
10324 /******************************************************************************/
10325 
10326 /*******************  Bit definition for SWPMI_CR register   ********************/
10327 #define SWPMI_CR_RXDMA_Pos       (0U)
10328 #define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */
10329 #define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */
10330 #define SWPMI_CR_TXDMA_Pos       (1U)
10331 #define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */
10332 #define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */
10333 #define SWPMI_CR_RXMODE_Pos      (2U)
10334 #define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */
10335 #define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */
10336 #define SWPMI_CR_TXMODE_Pos      (3U)
10337 #define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */
10338 #define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */
10339 #define SWPMI_CR_LPBK_Pos        (4U)
10340 #define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */
10341 #define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */
10342 #define SWPMI_CR_SWPACT_Pos      (5U)
10343 #define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */
10344 #define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */
10345 #define SWPMI_CR_DEACT_Pos       (10U)
10346 #define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */
10347 #define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */
10348 #define SWPMI_CR_SWPEN_Pos       (11U)
10349 #define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */
10350 #define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */
10351 
10352 /*******************  Bit definition for SWPMI_BRR register  ********************/
10353 #define SWPMI_BRR_BR_Pos         (0U)
10354 #define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */
10355 #define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */
10356 
10357 /*******************  Bit definition for SWPMI_ISR register  ********************/
10358 #define SWPMI_ISR_RXBFF_Pos      (0U)
10359 #define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */
10360 #define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */
10361 #define SWPMI_ISR_TXBEF_Pos      (1U)
10362 #define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */
10363 #define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */
10364 #define SWPMI_ISR_RXBERF_Pos     (2U)
10365 #define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */
10366 #define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */
10367 #define SWPMI_ISR_RXOVRF_Pos     (3U)
10368 #define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */
10369 #define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */
10370 #define SWPMI_ISR_TXUNRF_Pos     (4U)
10371 #define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */
10372 #define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */
10373 #define SWPMI_ISR_RXNE_Pos       (5U)
10374 #define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */
10375 #define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */
10376 #define SWPMI_ISR_TXE_Pos        (6U)
10377 #define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */
10378 #define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */
10379 #define SWPMI_ISR_TCF_Pos        (7U)
10380 #define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */
10381 #define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */
10382 #define SWPMI_ISR_SRF_Pos        (8U)
10383 #define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */
10384 #define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */
10385 #define SWPMI_ISR_SUSP_Pos       (9U)
10386 #define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */
10387 #define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */
10388 #define SWPMI_ISR_DEACTF_Pos     (10U)
10389 #define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */
10390 #define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */
10391 #define SWPMI_ISR_RDYF_Pos       (11U)
10392 #define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */
10393 #define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */
10394 
10395 /*******************  Bit definition for SWPMI_ICR register  ********************/
10396 #define SWPMI_ICR_CRXBFF_Pos     (0U)
10397 #define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */
10398 #define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */
10399 #define SWPMI_ICR_CTXBEF_Pos     (1U)
10400 #define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */
10401 #define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */
10402 #define SWPMI_ICR_CRXBERF_Pos    (2U)
10403 #define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */
10404 #define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */
10405 #define SWPMI_ICR_CRXOVRF_Pos    (3U)
10406 #define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */
10407 #define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */
10408 #define SWPMI_ICR_CTXUNRF_Pos    (4U)
10409 #define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */
10410 #define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */
10411 #define SWPMI_ICR_CTCF_Pos       (7U)
10412 #define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */
10413 #define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */
10414 #define SWPMI_ICR_CSRF_Pos       (8U)
10415 #define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */
10416 #define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */
10417 #define SWPMI_ICR_CRDYF_Pos      (11U)
10418 #define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */
10419 #define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */
10420 
10421 /*******************  Bit definition for SWPMI_IER register  ********************/
10422 #define SWPMI_IER_RXBFIE_Pos     (0U)
10423 #define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */
10424 #define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */
10425 #define SWPMI_IER_TXBEIE_Pos     (1U)
10426 #define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */
10427 #define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */
10428 #define SWPMI_IER_RXBERIE_Pos    (2U)
10429 #define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */
10430 #define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */
10431 #define SWPMI_IER_RXOVRIE_Pos    (3U)
10432 #define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */
10433 #define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */
10434 #define SWPMI_IER_TXUNRIE_Pos    (4U)
10435 #define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */
10436 #define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */
10437 #define SWPMI_IER_RIE_Pos        (5U)
10438 #define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */
10439 #define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */
10440 #define SWPMI_IER_TIE_Pos        (6U)
10441 #define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */
10442 #define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */
10443 #define SWPMI_IER_TCIE_Pos       (7U)
10444 #define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */
10445 #define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */
10446 #define SWPMI_IER_SRIE_Pos       (8U)
10447 #define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */
10448 #define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */
10449 #define SWPMI_IER_RDYIE_Pos      (11U)
10450 #define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */
10451 #define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */
10452 
10453 /*******************  Bit definition for SWPMI_RFL register  ********************/
10454 #define SWPMI_RFL_RFL_Pos        (0U)
10455 #define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
10456 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
10457 #define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
10458 
10459 /*******************  Bit definition for SWPMI_TDR register  ********************/
10460 #define SWPMI_TDR_TD_Pos         (0U)
10461 #define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */
10462 #define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */
10463 
10464 /*******************  Bit definition for SWPMI_RDR register  ********************/
10465 #define SWPMI_RDR_RD_Pos         (0U)
10466 #define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */
10467 #define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Receive Data Register           */
10468 
10469 
10470 /*******************  Bit definition for SWPMI_OR register  ********************/
10471 #define SWPMI_OR_TBYP_Pos        (0U)
10472 #define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */
10473 #define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */
10474 #define SWPMI_OR_CLASS_Pos       (1U)
10475 #define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */
10476 #define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */
10477 
10478 /******************************************************************************/
10479 /*                                                                            */
10480 /*                            Window WATCHDOG                                 */
10481 /*                                                                            */
10482 /******************************************************************************/
10483 /*******************  Bit definition for WWDG_CR register  ********************/
10484 #define WWDG_CR_T_Pos           (0U)
10485 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
10486 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
10487 #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
10488 #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
10489 #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
10490 #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
10491 #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
10492 #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
10493 #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
10494 
10495 #define WWDG_CR_WDGA_Pos        (7U)
10496 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
10497 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
10498 
10499 /*******************  Bit definition for WWDG_CFR register  *******************/
10500 #define WWDG_CFR_W_Pos          (0U)
10501 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
10502 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
10503 #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
10504 #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
10505 #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
10506 #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
10507 #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
10508 #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
10509 #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
10510 
10511 #define WWDG_CFR_EWI_Pos        (9U)
10512 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
10513 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
10514 
10515 #define WWDG_CFR_WDGTB_Pos      (11U)
10516 #define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */
10517 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */
10518 #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */
10519 #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */
10520 #define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */
10521 
10522 /*******************  Bit definition for WWDG_SR register  ********************/
10523 #define WWDG_SR_EWIF_Pos        (0U)
10524 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
10525 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
10526 
10527 
10528 /******************************************************************************/
10529 /*                                                                            */
10530 /*                                DBG                                         */
10531 /*                                                                            */
10532 /******************************************************************************/
10533 
10534 /********************  Bit definition for DBGMCU_IDCODE register  *************/
10535 #define DBGMCU_IDCODE_DEV_ID_Pos          (0U)
10536 #define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)  /*!< 0x00000FFF */
10537 #define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk
10538 #define DBGMCU_IDCODE_REV_ID_Pos          (16U)
10539 #define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
10540 #define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk
10541 
10542 /********************  Bit definition for DBGMCU_CR register  *****************/
10543 #define DBGMCU_CR_DBG_STOP_Pos           (1U)
10544 #define DBGMCU_CR_DBG_STOP_Msk           (0x1UL << DBGMCU_CR_DBG_STOP_Pos)     /*!< 0x00000002 */
10545 #define DBGMCU_CR_DBG_STOP               DBGMCU_CR_DBG_STOP_Msk
10546 #define DBGMCU_CR_DBG_STANDBY_Pos        (2U)
10547 #define DBGMCU_CR_DBG_STANDBY_Msk        (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)  /*!< 0x00000004 */
10548 #define DBGMCU_CR_DBG_STANDBY            DBGMCU_CR_DBG_STANDBY_Msk
10549 
10550 /********************  Bit definition for DBGMCU_APB1FZR register  ***********/
10551 #define DBGMCU_APBFZ1_DBG_TIM2_STOP_Pos                  (0U)
10552 #define DBGMCU_APBFZ1_DBG_TIM2_STOP_Msk                  (0x1UL << DBGMCU_APBFZ1_DBG_TIM2_STOP_Pos)  /*!< 0x00000001 */
10553 #define DBGMCU_APBFZ1_DBG_TIM2_STOP                      DBGMCU_APBFZ1_DBG_TIM2_STOP_Msk
10554 #define DBGMCU_APBFZ1_DBG_TIM3_STOP_Pos                  (1U)
10555 #define DBGMCU_APBFZ1_DBG_TIM3_STOP_Msk                  (0x1UL << DBGMCU_APBFZ1_DBG_TIM3_STOP_Pos)  /*!< 0x00000002 */
10556 #define DBGMCU_APBFZ1_DBG_TIM3_STOP                      DBGMCU_APBFZ1_DBG_TIM3_STOP_Msk
10557 #define DBGMCU_APBFZ1_DBG_TIM4_STOP_Pos                  (2U)
10558 #define DBGMCU_APBFZ1_DBG_TIM4_STOP_Msk                  (0x1UL << DBGMCU_APBFZ1_DBG_TIM4_STOP_Pos)  /*!< 0x00000004 */
10559 #define DBGMCU_APBFZ1_DBG_TIM4_STOP                      DBGMCU_APBFZ1_DBG_TIM4_STOP_Msk
10560 #define DBGMCU_APBFZ1_DBG_TIM6_STOP_Pos                  (4U)
10561 #define DBGMCU_APBFZ1_DBG_TIM6_STOP_Msk                  (0x1UL << DBGMCU_APBFZ1_DBG_TIM6_STOP_Pos)  /*!< 0x00000010 */
10562 #define DBGMCU_APBFZ1_DBG_TIM6_STOP                      DBGMCU_APBFZ1_DBG_TIM6_STOP_Msk
10563 #define DBGMCU_APBFZ1_DBG_TIM7_STOP_Pos                  (5U)
10564 #define DBGMCU_APBFZ1_DBG_TIM7_STOP_Msk                  (0x1UL << DBGMCU_APBFZ1_DBG_TIM7_STOP_Pos)  /*!< 0x00000020 */
10565 #define DBGMCU_APBFZ1_DBG_TIM7_STOP                      DBGMCU_APBFZ1_DBG_TIM7_STOP_Msk
10566 #define DBGMCU_APBFZ1_DBG_RTC_STOP_Pos                   (10U)
10567 #define DBGMCU_APBFZ1_DBG_RTC_STOP_Msk                   (0x1UL << DBGMCU_APBFZ1_DBG_RTC_STOP_Pos)   /*!< 0x00000400 */
10568 #define DBGMCU_APBFZ1_DBG_RTC_STOP                       DBGMCU_APBFZ1_DBG_RTC_STOP_Msk
10569 #define DBGMCU_APBFZ1_DBG_WWDG_STOP_Pos                  (11U)
10570 #define DBGMCU_APBFZ1_DBG_WWDG_STOP_Msk                  (0x1UL << DBGMCU_APBFZ1_DBG_WWDG_STOP_Pos)  /*!< 0x00000800 */
10571 #define DBGMCU_APBFZ1_DBG_WWDG_STOP                      DBGMCU_APBFZ1_DBG_WWDG_STOP_Msk
10572 #define DBGMCU_APBFZ1_DBG_IWDG_STOP_Pos                  (12U)
10573 #define DBGMCU_APBFZ1_DBG_IWDG_STOP_Msk                  (0x1UL << DBGMCU_APBFZ1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
10574 #define DBGMCU_APBFZ1_DBG_IWDG_STOP                      DBGMCU_APBFZ1_DBG_IWDG_STOP_Msk
10575 #define DBGMCU_APBFZ1_DBG_I2C3_STOP_Pos                  (21U)
10576 #define DBGMCU_APBFZ1_DBG_I2C3_STOP_Msk                  (0x1UL << DBGMCU_APBFZ1_DBG_I2C3_STOP_Pos) /*!< 0x00200000 */
10577 #define DBGMCU_APBFZ1_DBG_I2C3_STOP                      DBGMCU_APBFZ1_DBG_I2C3_STOP_Msk
10578 #define DBGMCU_APBFZ1_DBG_I2C1_STOP_Pos                  (22U)
10579 #define DBGMCU_APBFZ1_DBG_I2C1_STOP_Msk                  (0x1UL << DBGMCU_APBFZ1_DBG_I2C1_STOP_Pos) /*!< 0x00400000 */
10580 #define DBGMCU_APBFZ1_DBG_I2C1_STOP                      DBGMCU_APBFZ1_DBG_I2C1_STOP_Msk
10581 #define DBGMCU_APBFZ1_DBG_LPTIM2_STOP_Pos                (30U)
10582 #define DBGMCU_APBFZ1_DBG_LPTIM2_STOP_Msk                (0x1UL << DBGMCU_APBFZ1_DBG_LPTIM2_STOP_Pos) /*!< 0x40000000 */
10583 #define DBGMCU_APBFZ1_DBG_LPTIM2_STOP                    DBGMCU_APBFZ1_DBG_LPTIM2_STOP_Msk
10584 #define DBGMCU_APBFZ1_DBG_LPTIM1_STOP_Pos                (31U)
10585 #define DBGMCU_APBFZ1_DBG_LPTIM1_STOP_Msk                (0x1UL << DBGMCU_APBFZ1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
10586 #define DBGMCU_APBFZ1_DBG_LPTIM1_STOP                    DBGMCU_APBFZ1_DBG_LPTIM1_STOP_Msk
10587 
10588 /********************  Bit definition for DBGMCU_APB2FZR register  ************/
10589 #define DBGMCU_APBFZ2_DBG_TIM1_STOP_Pos                  (11U)
10590 #define DBGMCU_APBFZ2_DBG_TIM1_STOP_Msk                  (0x1UL << DBGMCU_APBFZ2_DBG_TIM1_STOP_Pos)  /*!< 0x00000800 */
10591 #define DBGMCU_APBFZ2_DBG_TIM1_STOP                      DBGMCU_APBFZ2_DBG_TIM1_STOP_Msk
10592 #define DBGMCU_APBFZ2_DBG_TIM14_STOP_Pos                 (15U)
10593 #define DBGMCU_APBFZ2_DBG_TIM14_STOP_Msk                 (0x1UL << DBGMCU_APBFZ2_DBG_TIM14_STOP_Pos) /*!< 0x00008000 */
10594 #define DBGMCU_APBFZ2_DBG_TIM14_STOP                     DBGMCU_APBFZ2_DBG_TIM14_STOP_Msk
10595 #define DBGMCU_APBFZ2_DBG_TIM15_STOP_Pos                 (16U)
10596 #define DBGMCU_APBFZ2_DBG_TIM15_STOP_Msk                 (0x1UL << DBGMCU_APBFZ2_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
10597 #define DBGMCU_APBFZ2_DBG_TIM15_STOP                     DBGMCU_APBFZ2_DBG_TIM15_STOP_Msk
10598 #define DBGMCU_APBFZ2_DBG_TIM16_STOP_Pos                 (17U)
10599 #define DBGMCU_APBFZ2_DBG_TIM16_STOP_Msk                 (0x1UL << DBGMCU_APBFZ2_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
10600 #define DBGMCU_APBFZ2_DBG_TIM16_STOP                     DBGMCU_APBFZ2_DBG_TIM16_STOP_Msk
10601 #define DBGMCU_APBFZ2_DBG_LPTIM3_STOP_Pos                (18U)
10602 #define DBGMCU_APBFZ2_DBG_LPTIM3_STOP_Msk                (0x1UL << DBGMCU_APBFZ2_DBG_LPTIM3_STOP_Pos) /*!< 0x00040000 */
10603 #define DBGMCU_APBFZ2_DBG_LPTIM3_STOP                    DBGMCU_APBFZ2_DBG_LPTIM3_STOP_Msk
10604 
10605 /********************  Bit definition for DBGMCU_SR register  ************/
10606 #define DBGMCU_SR_AP1_PRESENT_Pos                     (0U)
10607 #define DBGMCU_SR_AP1_PRESENT_Msk                     (0x1UL << DBGMCU_SR_AP1_PRESENT_Pos)           /*!< 0x00000001 */
10608 #define DBGMCU_SR_AP1_PRESENT                         DBGMCU_SR_AP1_PRESENT_Msk
10609 #define DBGMCU_SR_AP0_PRESENT_Pos                     (1U)
10610 #define DBGMCU_SR_AP0_PRESENT_Msk                     (0x1UL << DBGMCU_SR_AP0_PRESENT_Pos)           /*!< 0x00000002 */
10611 #define DBGMCU_SR_AP0_PRESENT                         DBGMCU_SR_AP0_PRESENT_Msk
10612 #define DBGMCU_SR_AP1_ENABLED_Pos                     (16U)
10613 #define DBGMCU_SR_AP1_ENABLED_Msk                     (0x1UL << DBGMCU_SR_AP1_ENABLED_Pos)           /*!< 0x00010000 */
10614 #define DBGMCU_SR_AP1_ENABLED                         DBGMCU_SR_AP1_ENABLED_Msk
10615 #define DBGMCU_SR_AP0_ENABLED_Pos                     (17U)
10616 #define DBGMCU_SR_AP0_ENABLED_Msk                     (0x1UL << DBGMCU_SR_AP0_ENABLED_Pos)           /*!< 0x00020000 */
10617 #define DBGMCU_SR_AP0_ENABLED                         DBGMCU_SR_AP0_ENABLED_Msk
10618 
10619 /********************  Bit definition for DBGMCU_DBG_AUTH_HOST register  ************/
10620 #define DBGMCU_DBG_AUTH_HOST_AP1_MESSAGE_Pos          (0U)
10621 #define DBGMCU_DBG_AUTH_HOST_AP1_MESSAGE_Msk          (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_AP1_MESSAGE_Pos)  /*!< 0xFFFFFFFF */
10622 #define DBGMCU_DBG_AUTH_HOST_AP1_MESSAGE              DBGMCU_DBG_AUTH_HOST_AP1_MESSAGE_Msk
10623 
10624 /********************  Bit definition for DBGMCU_DBG_AUTH_DEVICE register  ************/
10625 #define DBGMCU_DBG_AUTH_DEVICE_MESSAGE_Pos            (0U)
10626 #define DBGMCU_DBG_AUTH_DEVICE_MESSAGE_Msk            (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_DEVICE_MESSAGE_Pos)  /*!< 0xFFFFFFFF */
10627 #define DBGMCU_DBG_AUTH_DEVICE_MESSAGE                DBGMCU_DBG_AUTH_DEVICE_MESSAGE_Msk
10628 
10629 /********************  Bit definition for DBGMCU_PIDR4 register  ************/
10630 #define DBGMCU_PIDR4_JEP106CON_Pos                   (0U)
10631 #define DBGMCU_PIDR4_JEP106CON_Msk                   (0xFUL << DBGMCU_PIDR4_JEP106CON_Pos)                  /*!< 0x0000000F */
10632 #define DBGMCU_PIDR4_JEP106CON                       DBGMCU_PIDR4_JEP106CON_Msk
10633 #define DBGMCU_PIDR4_SIZE_Pos                        (4U)
10634 #define DBGMCU_PIDR4_SIZE_Msk                        (0xFUL << DBGMCU_PIDR4_SIZE_Pos)                       /*!< 0x0000000F */
10635 #define DBGMCU_PIDR4_SIZE                            DBGMCU_PIDR4_SIZE_Msk
10636 
10637 /********************  Bit definition for DBGMCU_PIDR0 register  ************/
10638 #define DBGMCU_PIDR0_PARTNUM_Pos                     (0U)
10639 #define DBGMCU_PIDR0_PARTNUM_Msk                     (0xFFUL << DBGMCU_PIDR0_PARTNUM_Pos)                   /*!< 0x000000FF */
10640 #define DBGMCU_PIDR0_PARTNUM                         DBGMCU_PIDR0_PARTNUM_Msk
10641 
10642 /********************  Bit definition for DBGMCU_PIDR1 register  ************/
10643 #define DBGMCU_PIDR1_PARTNUM_Pos                     (0U)
10644 #define DBGMCU_PIDR1_PARTNUM_Msk                     (0xFUL << DBGMCU_PIDR1_PARTNUM_Pos)                    /*!< 0x0000000F */
10645 #define DBGMCU_PIDR1_PARTNUM                         DBGMCU_PIDR1_PARTNUM_Msk
10646 #define DBGMCU_PIDR1_JEP106ID_Pos                    (4U)
10647 #define DBGMCU_PIDR1_JEP106ID_Msk                    (0xFUL << DBGMCU_PIDR1_JEP106ID_Pos)                   /*!< 0x0000000F */
10648 #define DBGMCU_PIDR1_JEP106ID                        DBGMCU_PIDR1_JEP106ID_Msk
10649 
10650 /********************  Bit definition for DBGMCU_PIDR2 register  ************/
10651 #define DBGMCU_PIDR2_JEP106ID_Pos                     (0U)
10652 #define DBGMCU_PIDR2_JEP106ID_Msk                     (0x7UL << DBGMCU_PIDR2_JEP106ID_Pos)                    /*!< 0x00000007 */
10653 #define DBGMCU_PIDR2_JEP106ID                         DBGMCU_PIDR2_JEP106ID_Msk
10654 #define DBGMCU_PIDR2_JEDEC_Pos                        (4U)
10655 #define DBGMCU_PIDR2_JEDEC_Msk                        (0x1UL << DBGMCU_PIDR2_JEDEC_Pos)                       /*!< 0x00000008 */
10656 #define DBGMCU_PIDR2_JEDEC                            DBGMCU_PIDR2_JEDEC_Msk
10657 #define DBGMCU_PIDR2_REVISION_Pos                     (4U)
10658 #define DBGMCU_PIDR2_REVISION_Msk                     (0xFUL << DBGMCU_PIDR2_REVISION_Pos)                    /*!< 0x000000F0 */
10659 #define DBGMCU_PIDR2_REVISION                         DBGMCU_PIDR2_REVISION_Msk
10660 
10661 /********************  Bit definition for DBGMCU_PIDR3 register  ************/
10662 #define DBGMCU_PIDR3_CMOD_Pos                         (0U)
10663 #define DBGMCU_PIDR3_CMOD_Msk                         (0xFUL << DBGMCU_PIDR3_CMOD_Pos)                            /*!< 0x0000000F */
10664 #define DBGMCU_PIDR3_CMOD                             DBGMCU_PIDR3_CMOD_Msk
10665 #define DBGMCU_PIDR3_REVAND_Pos                       (4U)
10666 #define DBGMCU_PIDR3_REVAND_Msk                       (0xFUL << DBGMCU_PIDR3_REVAND_Pos)                          /*!< 0x000000F0 */
10667 #define DBGMCU_PIDR3_REVAND                           DBGMCU_PIDR3_REVAND_Msk
10668 
10669 /********************  Bit definition for DBGMCU_CIDR0 register  ************/
10670 #define DBGMCU_CIDR0_PREAMBLE_Pos                     (0U)
10671 #define DBGMCU_CIDR0_PREAMBLE_Msk                     (0xFFUL << DBGMCU_CIDR0_PREAMBLE_Pos)                    /*!< 0x000000FF */
10672 #define DBGMCU_CIDR0_PREAMBLE                         DBGMCU_CIDR0_PREAMBLE_Msk
10673 
10674 /********************  Bit definition for DBGMCU_CIDR1 register  ************/
10675 #define DBGMCU_CIDR1_PREAMBLE_Pos                     (0U)
10676 #define DBGMCU_CIDR1_PREAMBLE_Msk                     (0xFUL << DBGMCU_CIDR1_PREAMBLE_Pos)                    /*!< 0x0000000F */
10677 #define DBGMCU_CIDR1_PREAMBLE                         DBGMCU_CIDR1_PREAMBLE_Msk
10678 #define DBGMCU_CIDR1_CLASS_Pos                        (4U)
10679 #define DBGMCU_CIDR1_CLASS_Msk                        (0xFUL << DBGMCU_CIDR1_CLASS_Pos)                       /*!< 0x000000F0 */
10680 #define DBGMCU_CIDR1_CLASS                            DBGMCU_CIDR1_CLASS_Msk
10681 
10682 /********************  Bit definition for DBGMCU_CIDR2 register  ************/
10683 #define DBGMCU_CIDR2_PREAMBLE_Pos                     (0U)
10684 #define DBGMCU_CIDR2_PREAMBLE_Msk                     (0xFFUL << DBGMCU_CIDR2_PREAMBLE_Pos)                    /*!< 0x000000FF */
10685 #define DBGMCU_CIDR2_PREAMBLE                         DBGMCU_CIDR2_PREAMBLE_Msk
10686 
10687 /********************  Bit definition for DBGMCU_CIDR3 register  ************/
10688 #define DBGMCU_CIDR3_PREAMBLE_Pos                     (0U)
10689 #define DBGMCU_CIDR3_PREAMBLE_Msk                     (0xFFUL << DBGMCU_CIDR3_PREAMBLE_Pos)                    /*!< 0x000000FF */
10690 #define DBGMCU_CIDR3_PREAMBLE                         DBGMCU_CIDR3_PREAMBLE_Msk
10691 
10692 /******************************************************************************/
10693 /*                                                                            */
10694 /*                         USB Dual Role Device FS Endpoint registers         */
10695 /*                                                                            */
10696 /******************************************************************************/
10697 
10698 /******************  Bits definition for USB_DRD_CNTR register  *******************/
10699 #define USB_CNTR_HOST_Pos               (31U)
10700 #define USB_CNTR_HOST_Msk               (0x1UL << USB_CNTR_HOST_Pos)    /*!< 0x80000000 */
10701 #define USB_CNTR_HOST                   USB_CNTR_HOST_Msk               /*!< Host Mode  */
10702 #define USB_CNTR_THR512M_Pos            (16U)
10703 #define USB_CNTR_THR512M_Msk            (0x1UL << USB_CNTR_THR512M_Pos)  /*!< 0x00010000 */
10704 #define USB_CNTR_THR512M                USB_CNTR_THR512M_Msk             /*!< 512byte Threshold interrupt mask */
10705 #define USB_CNTR_CTRM_Pos               (15U)
10706 #define USB_CNTR_CTRM_Msk               (0x1UL << USB_CNTR_CTRM_Pos)    /*!< 0x00008000 */
10707 #define USB_CNTR_CTRM                   USB_CNTR_CTRM_Msk               /*!< Correct Transfer Mask */
10708 #define USB_CNTR_PMAOVRM_Pos            (14U)
10709 #define USB_CNTR_PMAOVRM_Msk            (0x1UL << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
10710 #define USB_CNTR_PMAOVRM                USB_CNTR_PMAOVRM_Msk            /*!< DMA OVeR/underrun Mask */
10711 #define USB_CNTR_ERRM_Pos               (13U)
10712 #define USB_CNTR_ERRM_Msk               (0x1UL << USB_CNTR_ERRM_Pos)    /*!< 0x00002000 */
10713 #define USB_CNTR_ERRM                   USB_CNTR_ERRM_Msk               /*!< ERRor Mask */
10714 #define USB_CNTR_WKUPM_Pos              (12U)
10715 #define USB_CNTR_WKUPM_Msk              (0x1UL << USB_CNTR_WKUPM_Pos)   /*!< 0x00001000 */
10716 #define USB_CNTR_WKUPM                  USB_CNTR_WKUPM_Msk              /*!< WaKe UP Mask */
10717 #define USB_CNTR_SUSPM_Pos              (11U)
10718 #define USB_CNTR_SUSPM_Msk              (0x1UL << USB_CNTR_SUSPM_Pos)   /*!< 0x00000800 */
10719 #define USB_CNTR_SUSPM                  USB_CNTR_SUSPM_Msk              /*!< SUSPend Mask */
10720 #define USB_CNTR_RESETM_Pos             (10U)
10721 #define USB_CNTR_RESETM_Msk             (0x1UL << USB_CNTR_RESETM_Pos)  /*!< 0x00000400 */
10722 #define USB_CNTR_RESETM                 USB_CNTR_RESETM_Msk             /*!< RESET Mask */
10723 #define USB_CNTR_DCON                   USB_CNTR_RESETM_Msk             /*!< Disconnection Connection Mask */
10724 #define USB_CNTR_SOFM_Pos               (9U)
10725 #define USB_CNTR_SOFM_Msk               (0x1UL << USB_CNTR_SOFM_Pos)    /*!< 0x00000200 */
10726 #define USB_CNTR_SOFM                   USB_CNTR_SOFM_Msk               /*!< Start Of Frame Mask */
10727 #define USB_CNTR_ESOFM_Pos              (8U)
10728 #define USB_CNTR_ESOFM_Msk              (0x1UL << USB_CNTR_ESOFM_Pos)   /*!< 0x00000100 */
10729 #define USB_CNTR_ESOFM                  USB_CNTR_ESOFM_Msk              /*!< Expected Start Of Frame Mask */
10730 #define USB_CNTR_L1REQM_Pos             (7U)
10731 #define USB_CNTR_L1REQM_Msk             (0x1UL << USB_CNTR_L1REQM_Pos)  /*!< 0x00000080 */
10732 #define USB_CNTR_L1REQM                 USB_CNTR_L1REQM_Msk             /*!< LPM L1 state request interrupt Mask */
10733 #define USB_CNTR_L1XACT_Pos             (6U)
10734 #define USB_CNTR_L1XACT_Msk             (0x1UL << USB_CNTR_L1XACT_Pos)  /*!< 0x00000040 */
10735 #define USB_CNTR_L1XACT                 USB_CNTR_L1XACT_Msk             /*!< Host LPM L1 transaction request Mask */
10736 #define USB_CNTR_L1RES_Pos              (5U)
10737 #define USB_CNTR_L1RES_Msk              (0x1UL << USB_CNTR_L1RES_Pos)   /*!< 0x00000020 */
10738 #define USB_CNTR_L1RES                  USB_CNTR_L1RES_Msk              /*!< LPM L1 Resume request/ Remote Wakeup Mask */
10739 #define USB_CNTR_L2RES_Pos              (4U)
10740 #define USB_CNTR_L2RES_Msk              (0x1UL << USB_CNTR_L2RES_Pos)   /*!< 0x00000010 */
10741 #define USB_CNTR_L2RES                  USB_CNTR_L2RES_Msk              /*!< L2 Remote Wakeup / Resume driver Mask */
10742 #define USB_CNTR_SUSPEN_Pos             (3U)
10743 #define USB_CNTR_SUSPEN_Msk             (0x1UL << USB_CNTR_SUSPEN_Pos)  /*!< 0x00000008 */
10744 #define USB_CNTR_SUSPEN                 USB_CNTR_SUSPEN_Msk             /*!< Suspend state enable Mask */
10745 #define USB_CNTR_SUSPRDY_Pos            (2U)
10746 #define USB_CNTR_SUSPRDY_Msk            (0x1UL << USB_CNTR_SUSPRDY_Pos) /*!< 0x00000004 */
10747 #define USB_CNTR_SUSPRDY                USB_CNTR_SUSPRDY_Msk            /*!< Suspend state effective Mask */
10748 #define USB_CNTR_PDWN_Pos               (1U)
10749 #define USB_CNTR_PDWN_Msk               (0x1UL << USB_CNTR_PDWN_Pos)    /*!< 0x00000002 */
10750 #define USB_CNTR_PDWN                   USB_CNTR_PDWN_Msk               /*!< Power DoWN Mask */
10751 #define USB_CNTR_USBRST_Pos             (0U)
10752 #define USB_CNTR_USBRST_Msk             (0x1UL << USB_CNTR_USBRST_Pos)  /*!< 0x00000001 */
10753 #define USB_CNTR_USBRST                 USB_CNTR_USBRST_Msk             /*!< USB Reset Mask */
10754 
10755 /******************  Bits definition for USB_DRD_ISTR register  *******************/
10756 #define USB_ISTR_IDN_Pos                (0U)
10757 #define USB_ISTR_IDN_Msk                (0xFUL << USB_ISTR_IDN_Pos)     /*!< 0x0000000F */
10758 #define USB_ISTR_IDN                    USB_ISTR_IDN_Msk                /*!< EndPoint IDentifier (read-only bit) Mask */
10759 #define USB_ISTR_DIR_Pos                (4U)
10760 #define USB_ISTR_DIR_Msk                (0x1UL << USB_ISTR_DIR_Pos)     /*!< 0x00000010 */
10761 #define USB_ISTR_DIR                    USB_ISTR_DIR_Msk                /*!< DIRection of transaction (read-only bit) Mask */
10762 #define USB_ISTR_L1REQ_Pos              (7U)
10763 #define USB_ISTR_L1REQ_Msk              (0x1UL << USB_ISTR_L1REQ_Pos)   /*!< 0x00000080 */
10764 #define USB_ISTR_L1REQ                  USB_ISTR_L1REQ_Msk              /*!< LPM L1 state request Mask */
10765 #define USB_ISTR_ESOF_Pos               (8U)
10766 #define USB_ISTR_ESOF_Msk               (0x1UL << USB_ISTR_ESOF_Pos)    /*!< 0x00000100 */
10767 #define USB_ISTR_ESOF                   USB_ISTR_ESOF_Msk               /*!< Expected Start Of Frame (clear-only bit) Mask */
10768 #define USB_ISTR_SOF_Pos                (9U)
10769 #define USB_ISTR_SOF_Msk                (0x1UL << USB_ISTR_SOF_Pos)     /*!< 0x00000200 */
10770 #define USB_ISTR_SOF                    USB_ISTR_SOF_Msk                /*!< Start Of Frame (clear-only bit) Mask */
10771 #define USB_ISTR_RESET_Pos              (10U)
10772 #define USB_ISTR_RESET_Msk              (0x1UL << USB_ISTR_RESET_Pos)   /*!< 0x00000400 */
10773 #define USB_ISTR_RESET                  USB_ISTR_RESET_Msk              /*!< RESET Mask */
10774 #define USB_ISTR_DCON_Pos               (10U)
10775 #define USB_ISTR_DCON_Msk               (0x1UL << USB_ISTR_DCON_Pos)    /*!< 0x00000400 */
10776 #define USB_ISTR_DCON                   USB_ISTR_DCON_Msk               /*!< HOST MODE-Device Connection or disconnection Mask */
10777 #define USB_ISTR_SUSP_Pos               (11U)
10778 #define USB_ISTR_SUSP_Msk               (0x1UL << USB_ISTR_SUSP_Pos)    /*!< 0x00000800 */
10779 #define USB_ISTR_SUSP                   USB_ISTR_SUSP_Msk               /*!< SUSPend (clear-only bit) Mask */
10780 #define USB_ISTR_WKUP_Pos               (12U)
10781 #define USB_ISTR_WKUP_Msk               (0x1UL << USB_ISTR_WKUP_Pos)    /*!< 0x00001000 */
10782 #define USB_ISTR_WKUP                   USB_ISTR_WKUP_Msk               /*!< WaKe UP (clear-only bit) Mask */
10783 #define USB_ISTR_ERR_Pos                (13U)
10784 #define USB_ISTR_ERR_Msk                (0x1UL << USB_ISTR_ERR_Pos)     /*!< 0x00002000 */
10785 #define USB_ISTR_ERR                    USB_ISTR_ERR_Msk                /*!< ERRor (clear-only bit) Mask */
10786 #define USB_ISTR_PMAOVR_Pos             (14U)
10787 #define USB_ISTR_PMAOVR_Msk             (0x1UL << USB_ISTR_PMAOVR_Pos)  /*!< 0x00004000 */
10788 #define USB_ISTR_PMAOVR                 USB_ISTR_PMAOVR_Msk             /*!< PMA OVeR/underrun (clear-only bit) Mask */
10789 #define USB_ISTR_CTR_Pos                (15U)
10790 #define USB_ISTR_CTR_Msk                (0x1UL << USB_ISTR_CTR_Pos)     /*!< 0x00008000 */
10791 #define USB_ISTR_CTR                    USB_ISTR_CTR_Msk                /*!< Correct TRansfer (clear-only bit) Mask */
10792 #define USB_ISTR_THR512_Pos             (16U)
10793 #define USB_ISTR_THR512_Msk             (0x1UL << USB_ISTR_THR512_Pos)  /*!< 0x00010000 */
10794 #define USB_ISTR_THR512                 USB_ISTR_THR512_Msk             /*!< 512byte threshold interrupt (used with isochrnous single buffer ) */
10795 #define USB_ISTR_DCON_STAT_Pos          (29U)
10796 #define USB_ISTR_DCON_STAT_Msk          (0x1UL << USB_ISTR_DCON_STAT_Pos)/*!< 0x20000000 */
10797 #define USB_ISTR_DCON_STAT              USB_ISTR_DCON_STAT_Msk           /*!< Device Connection status (connected/Disconnected) don't cause an interrupt */
10798 #define USB_ISTR_LS_DCONN_Pos           (30U)
10799 #define USB_ISTR_LS_DCONN_Msk           (0x1UL << USB_ISTR_LS_DCONN_Pos)/*!< 0x40000000 */
10800 #define USB_ISTR_LS_DCONN               USB_ISTR_LS_DCONN_Msk           /*!< LS_DCONN Mask */
10801 
10802 /******************  Bits definition for USB_DRD_FNR register  ********************/
10803 #define USB_FNR_FN_Pos                  (0U)
10804 #define USB_FNR_FN_Msk                  (0x7FFUL << USB_FNR_FN_Pos)     /*!< 0x000007FF */
10805 #define USB_FNR_FN                      USB_FNR_FN_Msk                  /*!< Frame Number Mask */
10806 #define USB_FNR_LSOF_Pos                (11U)
10807 #define USB_FNR_LSOF_Msk                (0x3UL << USB_FNR_LSOF_Pos)     /*!< 0x00001800 */
10808 #define USB_FNR_LSOF                    USB_FNR_LSOF_Msk                /*!< Lost SOF  Mask */
10809 #define USB_FNR_LCK_Pos                 (13U)
10810 #define USB_FNR_LCK_Msk                 (0x1UL << USB_FNR_LCK_Pos)      /*!< 0x00002000 */
10811 #define USB_FNR_LCK                     USB_FNR_LCK_Msk                 /*!< LoCKed Mask */
10812 #define USB_FNR_RXDM_Pos                (14U)
10813 #define USB_FNR_RXDM_Msk                (0x1UL << USB_FNR_RXDM_Pos)     /*!< 0x00004000 */
10814 #define USB_FNR_RXDM                    USB_FNR_RXDM_Msk                /*!< status of D- data line Mask */
10815 #define USB_FNR_RXDP_Pos                (15U)
10816 #define USB_FNR_RXDP_Msk                (0x1UL << USB_FNR_RXDP_Pos)     /*!< 0x00008000 */
10817 #define USB_FNR_RXDP                    USB_FNR_RXDP_Msk                /*!< status of D+ data line Mask */
10818 
10819 /******************  Bits definition for USB_DRD_DADDR register    ****************/
10820 #define USB_DADDR_ADD_Pos               (0U)
10821 #define USB_DADDR_ADD_Msk               (0x7FUL << USB_DADDR_ADD_Pos)   /*!< 0x0000007F */
10822 #define USB_DADDR_ADD                   USB_DADDR_ADD_Msk               /*!<  ADD[6:0] bits (Device Address)Mask */
10823 #define USB_DADDR_ADD0_Pos              (0U)
10824 #define USB_DADDR_ADD0_Msk              (0x1UL << USB_DADDR_ADD0_Pos)   /*!< 0x00000001 */
10825 #define USB_DADDR_ADD0                  USB_DADDR_ADD0_Msk              /*!< Bit 0 Mask */
10826 #define USB_DADDR_ADD1_Pos              (1U)
10827 #define USB_DADDR_ADD1_Msk              (0x1UL << USB_DADDR_ADD1_Pos)   /*!< 0x00000002 */
10828 #define USB_DADDR_ADD1                  USB_DADDR_ADD1_Msk              /*!< Bit 1 Mask */
10829 #define USB_DADDR_ADD2_Pos              (2U)
10830 #define USB_DADDR_ADD2_Msk              (0x1UL << USB_DADDR_ADD2_Pos)   /*!< 0x00000004 */
10831 #define USB_DADDR_ADD2                  USB_DADDR_ADD2_Msk              /*!< Bit 2 Mask */
10832 #define USB_DADDR_ADD3_Pos              (3U)
10833 #define USB_DADDR_ADD3_Msk              (0x1UL << USB_DADDR_ADD3_Pos)   /*!< 0x00000008 */
10834 #define USB_DADDR_ADD3                  USB_DADDR_ADD3_Msk              /*!< Bit 3 Mask */
10835 #define USB_DADDR_ADD4_Pos              (4U)
10836 #define USB_DADDR_ADD4_Msk              (0x1UL << USB_DADDR_ADD4_Pos)   /*!< 0x00000010 */
10837 #define USB_DADDR_ADD4                  USB_DADDR_ADD4_Msk              /*!< Bit 4 Mask */
10838 #define USB_DADDR_ADD5_Pos              (5U)
10839 #define USB_DADDR_ADD5_Msk              (0x1UL << USB_DADDR_ADD5_Pos)   /*!< 0x00000020 */
10840 #define USB_DADDR_ADD5                  USB_DADDR_ADD5_Msk              /*!< Bit 5 Mask */
10841 #define USB_DADDR_ADD6_Pos              (6U)
10842 #define USB_DADDR_ADD6_Msk              (0x1UL << USB_DADDR_ADD6_Pos)   /*!< 0x00000040 */
10843 #define USB_DADDR_ADD6                  USB_DADDR_ADD6_Msk              /*!< Bit 6 Mask */
10844 #define USB_DADDR_EF_Pos                (7U)
10845 #define USB_DADDR_EF_Msk                (0x1UL << USB_DADDR_EF_Pos)     /*!< 0x00000080 */
10846 #define USB_DADDR_EF                    USB_DADDR_EF_Msk                /*!< Enable Function Mask */
10847 
10848 /******************  Bit definition for USB_DRD_BTABLE register  ******************/
10849 #define USB_BTABLE_BTABLE_Pos          (3U)
10850 #define USB_BTABLE_BTABLE_Msk          (0xFFF8UL << USB_BTABLE_BTABLE_Pos)/*!< 0x00000000 */
10851 #define USB_BTABLE_BTABLE              USB_BTABLE_BTABLE_Msk              /*!< Buffer Table Mask */
10852 
10853 /*******************  Bit definition for LPMCSR register  *********************/
10854 #define USB_LPMCSR_LMPEN_Pos           (0U)
10855 #define USB_LPMCSR_LMPEN_Msk           (0x1UL << USB_LPMCSR_LMPEN_Pos)  /*!< 0x00000001 */
10856 #define USB_LPMCSR_LMPEN               USB_LPMCSR_LMPEN_Msk             /*!< LPM support enable Mask */
10857 #define USB_LPMCSR_LPMACK_Pos          (1U)
10858 #define USB_LPMCSR_LPMACK_Msk          (0x1UL << USB_LPMCSR_LPMACK_Pos) /*!< 0x00000002 */
10859 #define USB_LPMCSR_LPMACK              USB_LPMCSR_LPMACK_Msk            /*!< LPM Token acknowledge enable Mask */
10860 #define USB_LPMCSR_REMWAKE_Pos         (3U)
10861 #define USB_LPMCSR_REMWAKE_Msk         (0x1UL << USB_LPMCSR_REMWAKE_Pos)/*!< 0x00000008 */
10862 #define USB_LPMCSR_REMWAKE             USB_LPMCSR_REMWAKE_Msk           /*!< bRemoteWake value received with last ACKed LPM Token Mask */
10863 #define USB_LPMCSR_BESL_Pos            (4U)
10864 #define USB_LPMCSR_BESL_Msk            (0xFUL << USB_LPMCSR_BESL_Pos)   /*!< 0x000000F0 */
10865 #define USB_LPMCSR_BESL                USB_LPMCSR_BESL_Msk              /*!< BESL value received with last ACKed LPM Token Mask */
10866 
10867 /******************  Bits definition for USB_DRD_BCDR register  *******************/
10868 #define USB_BCDR_BCDEN_Pos             (0U)
10869 #define USB_BCDR_BCDEN_Msk             (0x1UL << USB_BCDR_BCDEN_Pos)    /*!< 0x00000001 */
10870 #define USB_BCDR_BCDEN                 USB_BCDR_BCDEN_Msk               /*!< Battery charging detector (BCD) enable Mask */
10871 #define USB_BCDR_DCDEN_Pos             (1U)
10872 #define USB_BCDR_DCDEN_Msk             (0x1UL << USB_BCDR_DCDEN_Pos)    /*!< 0x00000002 */
10873 #define USB_BCDR_DCDEN                 USB_BCDR_DCDEN_Msk               /*!< Data contact detection (DCD) mode enable Mask */
10874 #define USB_BCDR_PDEN_Pos              (2U)
10875 #define USB_BCDR_PDEN_Msk              (0x1UL << USB_BCDR_PDEN_Pos)     /*!< 0x00000004 */
10876 #define USB_BCDR_PDEN                  USB_BCDR_PDEN_Msk                /*!< Primary detection (PD) mode enable Mask */
10877 #define USB_BCDR_SDEN_Pos              (3U)
10878 #define USB_BCDR_SDEN_Msk              (0x1UL << USB_BCDR_SDEN_Pos)     /*!< 0x00000008 */
10879 #define USB_BCDR_SDEN                  USB_BCDR_SDEN_Msk                /*!< Secondary detection (SD) mode enable Mask */
10880 #define USB_BCDR_DCDET_Pos             (4U)
10881 #define USB_BCDR_DCDET_Msk             (0x1UL << USB_BCDR_DCDET_Pos)    /*!< 0x00000010 */
10882 #define USB_BCDR_DCDET                 USB_BCDR_DCDET_Msk               /*!< Data contact detection (DCD) status Mask */
10883 #define USB_BCDR_PDET_Pos              (5U)
10884 #define USB_BCDR_PDET_Msk              (0x1UL << USB_BCDR_PDET_Pos)     /*!< 0x00000020 */
10885 #define USB_BCDR_PDET                  USB_BCDR_PDET_Msk                /*!< Primary detection (PD) status Mask */
10886 #define USB_BCDR_SDET_Pos              (6U)
10887 #define USB_BCDR_SDET_Msk              (0x1UL << USB_BCDR_SDET_Pos)     /*!< 0x00000040 */
10888 #define USB_BCDR_SDET                  USB_BCDR_SDET_Msk                /*!< Secondary detection (SD) status Mask */
10889 #define USB_BCDR_PS2DET_Pos            (7U)
10890 #define USB_BCDR_PS2DET_Msk            (0x1UL << USB_BCDR_PS2DET_Pos)   /*!< 0x00000080 */
10891 #define USB_BCDR_PS2DET                USB_BCDR_PS2DET_Msk              /*!< PS2 port or proprietary charger detected Mask */
10892 #define USB_BCDR_DPPU_Pos              (15U)
10893 #define USB_BCDR_DPPU_Msk              (0x1UL << USB_BCDR_DPPU_Pos)     /*!< 0x00008000 */
10894 #define USB_BCDR_DPPU                  USB_BCDR_DPPU_Msk                /*!< DP Pull-up Enable Mask */
10895 #define USB_BCDR_DPPD_Pos              (15U)
10896 #define USB_BCDR_DPPD_Msk              (0x1UL << USB_BCDR_DPPD_Pos)     /*!< 0x00008000 */
10897 #define USB_BCDR_DPPD                  USB_BCDR_DPPD_Msk                /*!< DP Pull-Down Enable Mask */
10898 
10899 /******************  Bits definition for USB_DRD_CHEP register  *******************/
10900 #define USB_CHEP_ERRRX_Pos             (26U)
10901 #define USB_CHEP_ERRRX_Msk             (0x01UL << USB_CHEP_ERRRX_Pos)   /*!< 0x04000000 */
10902 #define USB_CHEP_ERRRX                 USB_CHEP_ERRRX_Msk               /*!< Receive error */
10903 #define USB_EP_ERRRX                   USB_CHEP_ERRRX_Msk               /*!< EP Receive error */
10904 #define USB_CH_ERRRX                   USB_CHEP_ERRRX_Msk               /*!< CH Receive error */
10905 #define USB_CHEP_ERRTX_Pos             (25U)
10906 #define USB_CHEP_ERRTX_Msk             (0x01UL << USB_CHEP_ERRTX_Pos)   /*!< 0x02000000 */
10907 #define USB_CHEP_ERRTX                 USB_CHEP_ERRTX_Msk               /*!< Transmit error */
10908 #define USB_EP_ERRTX                   USB_CHEP_ERRTX_Msk               /*!< EP Transmit error */
10909 #define USB_CH_ERRTX                   USB_CHEP_ERRTX_Msk               /*!< CH Transmit error */
10910 #define USB_CHEP_LSEP_Pos              (24U)
10911 #define USB_CHEP_LSEP_Msk              (0x01UL << USB_CHEP_LSEP_Pos)    /*!< 0x01000000 */
10912 #define USB_CHEP_LSEP                  USB_CHEP_LSEP_Msk                /*!< Low Speed Endpoint (host with Hub Only) */
10913 #define USB_CHEP_NAK_Pos               (23U)
10914 #define USB_CHEP_NAK_Msk               (0x01UL << USB_CHEP_NAK_Pos)     /*!< 0x00800000 */
10915 #define USB_CHEP_NAK                   USB_CHEP_NAK_Msk                 /*!< Previous NAK detected */
10916 #define USB_CHEP_DEVADDR_Pos           (16U)
10917 #define USB_CHEP_DEVADDR_Msk           (0x7FU << USB_CHEP_DEVADDR_Pos)  /*!< 0x7F000000 */
10918 #define USB_CHEP_DEVADDR               USB_CHEP_DEVADDR_Msk             /* Target Endpoint address*/
10919 #define USB_CHEP_VTRX_Pos              (15U)
10920 #define USB_CHEP_VTRX_Msk              (0x1UL << USB_CHEP_VTRX_Pos)     /*!< 0x00008000 */
10921 #define USB_CHEP_VTRX                  USB_CHEP_VTRX_Msk                /*!< USB valid transaction received Mask */
10922 #define USB_EP_VTRX                    USB_CHEP_VTRX_Msk                /*!< USB Endpoint valid transaction received Mask */
10923 #define USB_CH_VTRX                    USB_CHEP_VTRX_Msk                /*!< USB valid Channel transaction received Mask */
10924 #define USB_CHEP_DTOG_RX_Pos           (14U)
10925 #define USB_CHEP_DTOG_RX_Msk           (0x1UL << USB_CHEP_DTOG_RX_Pos)  /*!< 0x00004000 */
10926 #define USB_CHEP_DTOG_RX               USB_CHEP_DTOG_RX_Msk             /*!< Data Toggle, for reception transfers Mask */
10927 #define USB_EP_DTOG_RX                 USB_CHEP_DTOG_RX_Msk             /*!< EP Data Toggle, for reception transfers Mask */
10928 #define USB_CH_DTOG_RX                 USB_CHEP_DTOG_RX_Msk             /*!< CH Data Toggle, for reception transfers Mask */
10929 #define USB_CHEP_RX_STRX_Pos           (12U)
10930 #define USB_CHEP_RX_STRX_Msk           (0x3UL << USB_CHEP_RX_STRX_Pos)  /*!< 0x00003000 */
10931 #define USB_CHEP_RX_STRX               USB_CHEP_RX_STRX_Msk             /*!< Status bits, for reception transfers Mask */
10932 #define USB_EP_RX_STRX                 USB_CHEP_RX_STRX_Msk             /*!< Status bits, for EP reception transfers Mask */
10933 #define USB_CH_RX_STRX                 USB_CHEP_RX_STRX_Msk             /*!< Status bits, for CH reception transfers Mask */
10934 #define USB_CHEP_SETUP_Pos             (11U)
10935 #define USB_CHEP_SETUP_Msk             (0x1UL << USB_CHEP_SETUP_Pos)    /*!< 0x00000800 */
10936 #define USB_CHEP_SETUP                 USB_CHEP_SETUP_Msk               /*!< Setup transaction completed Mask */
10937 #define USB_EP_SETUP                   USB_CHEP_SETUP_Msk               /*!< EP Setup transaction completed Mask */
10938 #define USB_CH_SETUP                   USB_CHEP_SETUP_Msk               /*!< CH Setup transaction completed Mask */
10939 #define USB_CHEP_UTYPE_Pos             (9U)
10940 #define USB_CHEP_UTYPE_Msk             (0x3UL << USB_CHEP_UTYPE_Pos)    /*!< 0x00000600 */
10941 #define USB_CHEP_UTYPE                 USB_CHEP_UTYPE_Msk               /*!< USB type of transaction Mask */
10942 #define USB_EP_UTYPE                   USB_CHEP_UTYPE_Msk               /*!< USB type of EP transaction Mask */
10943 #define USB_CH_UTYPE                   USB_CHEP_UTYPE_Msk               /*!< USB type of CH transaction Mask */
10944 #define USB_CHEP_KIND_Pos              (8U)
10945 #define USB_CHEP_KIND_Msk              (0x1UL << USB_CHEP_KIND_Pos)     /*!< 0x00000100 */
10946 #define USB_CHEP_KIND                  USB_CHEP_KIND_Msk                /*!< EndPoint KIND Mask */
10947 #define USB_EP_KIND                    USB_CHEP_KIND_Msk                /*!< EndPoint KIND Mask */
10948 #define USB_CH_KIND                    USB_CHEP_KIND_Msk                /*!< Channel KIND Mask */
10949 #define USB_CHEP_VTTX_Pos              (7U)
10950 #define USB_CHEP_VTTX_Msk              (0x1UL << USB_CHEP_VTTX_Pos)     /*!< 0x00000080 */
10951 #define USB_CHEP_VTTX                  USB_CHEP_VTTX_Msk                /*!< Valid USB transaction transmitted Mask */
10952 #define USB_EP_VTTX                    USB_CHEP_VTTX_Msk                /*!< USB Endpoint valid transaction transmitted Mask */
10953 #define USB_CH_VTTX                    USB_CHEP_VTTX_Msk                /*!< USB valid Channel transaction transmitted Mask */
10954 #define USB_CHEP_DTOG_TX_Pos           (6U)
10955 #define USB_CHEP_DTOG_TX_Msk           (0x1UL << USB_CHEP_DTOG_TX_Pos)  /*!< 0x00000040 */
10956 #define USB_CHEP_DTOG_TX               USB_CHEP_DTOG_TX_Msk             /*!< Data Toggle, for transmission transfers Mask */
10957 #define USB_EP_DTOG_TX                 USB_CHEP_DTOG_TX_Msk             /*!< EP Data Toggle, for transmission transfers Mask */
10958 #define USB_CH_DTOG_TX                 USB_CHEP_DTOG_TX_Msk             /*!< CH Data Toggle, for transmission transfers Mask */
10959 #define USB_CHEP_TX_STTX_Pos           (4U)
10960 #define USB_CHEP_TX_STTX_Msk           (0x3UL << USB_CHEP_TX_STTX_Pos)  /*!< 0x00000030 */
10961 #define USB_CHEP_TX_STTX               USB_CHEP_TX_STTX_Msk             /*!< Status bits, for transmission transfers Mask */
10962 #define USB_EP_TX_STTX                 USB_CHEP_TX_STTX_Msk             /*!< Status bits, for EP transmission transfers Mask */
10963 #define USB_CH_TX_STTX                 USB_CHEP_TX_STTX_Msk             /*!< Status bits, for CH transmission transfers Mask */
10964 #define USB_CHEP_ADDR_Pos              (0U)
10965 #define USB_CHEP_ADDR_Msk              (0xFUL << USB_CHEP_ADDR_Pos)     /*!< 0x0000000F */
10966 #define USB_CHEP_ADDR                  USB_CHEP_ADDR_Msk                /*!< Endpoint address Mask */
10967 
10968 /* EndPoint Register MASK (no toggle fields) */
10969 #define USB_CHEP_REG_MASK                          (USB_CHEP_ERRRX | USB_CHEP_ERRTX | USB_CHEP_LSEP | \
10970                                                     USB_CHEP_DEVADDR | USB_CHEP_VTRX | USB_CHEP_SETUP | \
10971                                                     USB_CHEP_UTYPE | USB_CHEP_KIND | USB_CHEP_VTTX | USB_CHEP_ADDR | \
10972                                                     USB_CHEP_NAK) /* 0x07FF8F8F */
10973 
10974 #define USB_CHEP_TX_DTOGMASK                       (USB_CHEP_TX_STTX | USB_CHEP_REG_MASK)
10975 #define USB_CHEP_RX_DTOGMASK                       (USB_CHEP_RX_STRX | USB_CHEP_REG_MASK)
10976 
10977 #define USB_CHEP_TX_DTOG1                          (0x00000010UL)           /*!< Channel/EndPoint TX Data Toggle bit1 */
10978 #define USB_CHEP_TX_DTOG2                          (0x00000020UL)           /*!< Channel/EndPoint TX Data Toggle bit2 */
10979 #define USB_CHEP_RX_DTOG1                          (0x00001000UL)           /*!< Channel/EndPoint RX Data Toggle bit1 */
10980 #define USB_CHEP_RX_DTOG2                          (0x00002000UL)           /*!< Channel/EndPoint RX Data Toggle bit1 */
10981 
10982 /*!< EP_TYPE[1:0] Channel/EndPoint TYPE */
10983 #define USB_EP_TYPE_MASK                           (0x00000600UL)           /*!< Channel/EndPoint TYPE Mask */
10984 #define USB_EP_BULK                                (0x00000000UL)           /*!< Channel/EndPoint BULK */
10985 #define USB_EP_CONTROL                             (0x00000200UL)           /*!< Channel/EndPoint CONTROL */
10986 #define USB_EP_ISOCHRONOUS                         (0x00000400UL)           /*!< Channel/EndPoint ISOCHRONOUS */
10987 #define USB_EP_INTERRUPT                           (0x00000600UL)           /*!< Channel/EndPoint INTERRUPT */
10988 
10989 #define USB_EP_T_MASK                              ((~USB_EP_UTYPE) & USB_CHEP_REG_MASK) /* =0x898F */
10990 #define USB_CH_T_MASK                              ((~USB_CH_UTYPE) & USB_CHEP_REG_MASK) /* =0x898F */
10991 
10992 #define USB_EP_KIND_MASK                           ((~USB_EP_KIND) & USB_CHEP_REG_MASK) /*!< EP_KIND EndPoint KIND */
10993 #define USB_CH_KIND_MASK                           ((~USB_CH_KIND) & USB_CHEP_REG_MASK) /*!< EP_KIND EndPoint KIND */
10994 
10995 /*!< STAT_TX[1:0] STATus for TX transfer */
10996 #define USB_EP_TX_DIS                              (0x00000000UL)           /*!< EndPoint TX Disabled */
10997 #define USB_EP_TX_STALL                            (0x00000010UL)           /*!< EndPoint TX STALLed */
10998 #define USB_EP_TX_NAK                              (0x00000020UL)           /*!< EndPoint TX NAKed */
10999 #define USB_EP_TX_VALID                            (0x00000030UL)           /*!< EndPoint TX VALID */
11000 
11001 #define USB_CH_TX_DIS                              (0x00000000UL)           /*!< Channel TX Disabled */
11002 #define USB_CH_TX_STALL                            (0x00000010UL)           /*!< Channel TX STALLed */
11003 #define USB_CH_TX_NAK                              (0x00000020UL)           /*!< Channel TX NAKed */
11004 #define USB_CH_TX_VALID                            (0x00000030UL)           /*!< Channel TX VALID */
11005 
11006 #define USB_EP_TX_ACK_SBUF                         (0x00000000UL)           /*!< ACK single buffer mode */
11007 #define USB_EP_TX_ACK_DBUF                         (0x00000030UL)           /*!< ACK Double buffer mode */
11008 
11009 #define USB_CH_TX_ACK_SBUF                         (0x00000000UL)           /*!< ACK single buffer mode */
11010 #define USB_CH_TX_ACK_DBUF                         (0x00000030UL)           /*!< ACK Double buffer mode */
11011 
11012 /*!< STAT_RX[1:0] STATus for RX transfer */
11013 #define USB_EP_RX_DIS                              (0x00000000UL)           /*!< EndPoint RX Disabled */
11014 #define USB_EP_RX_STALL                            (0x00001000UL)           /*!< EndPoint RX STALLed */
11015 #define USB_EP_RX_NAK                              (0x00002000UL)           /*!< EndPoint RX NAKed */
11016 #define USB_EP_RX_VALID                            (0x00003000UL)           /*!< EndPoint RX VALID */
11017 
11018 #define USB_EP_RX_ACK_SBUF                         (0x00000000UL)           /*!< ACK single buffer mode */
11019 #define USB_EP_RX_ACK_DBUF                         (0x00003000UL)           /*!< ACK Double buffer mode */
11020 
11021 
11022 
11023 #define USB_CH_RX_DIS                              (0x00000000UL)           /*!< EndPoint RX Disabled */
11024 #define USB_CH_RX_STALL                            (0x00001000UL)           /*!< EndPoint RX STALLed */
11025 #define USB_CH_RX_NAK                              (0x00002000UL)           /*!< Channel RX NAKed */
11026 #define USB_CH_RX_VALID                            (0x00003000UL)           /*!< Channel RX VALID */
11027 
11028 #define USB_CH_RX_ACK_SBUF                         (0x00000000UL)           /*!< ACK single buffer mode */
11029 #define USB_CH_RX_ACK_DBUF                         (0x00003000UL)           /*!< ACK Double buffer mode */
11030 
11031 /*! <used For Double Buffer Enable Disable */
11032 #define USB_CHEP_DB_MSK                            (0xFFFF0F0FUL)
11033 
11034 /*Buffer Descriptor Mask*/
11035 #define USB_PMA_TXBD_ADDMSK                        (0xFFFF0000UL)
11036 #define USB_PMA_TXBD_COUNTMSK                      (0x0000FFFFUL)
11037 #define USB_PMA_RXBD_ADDMSK                        (0xFFFF0000UL)
11038 #define USB_PMA_RXBD_COUNTMSK                      (0x03FFFFFFUL)
11039 /**
11040   * @}
11041   */
11042 
11043 /**
11044   * @}
11045   */
11046 
11047 /** @addtogroup Exported_macros
11048   * @{
11049   */
11050 
11051 /******************************* ADC Instances ********************************/
11052 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
11053 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
11054 
11055 /******************************* AES Instances ********************************/
11056 #define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
11057 
11058 
11059 /******************************** COMP Instances ******************************/
11060 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
11061                                         ((INSTANCE) == COMP2))
11062 
11063 #define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
11064 
11065 /******************** COMP Instances with window mode capability **************/
11066 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
11067                                                ((INSTANCE) == COMP2))
11068 
11069 /******************************* CRC Instances ********************************/
11070 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
11071 
11072 /******************************* DAC Instances ********************************/
11073 #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1))
11074 
11075 /******************************** DMA Instances *******************************/
11076 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
11077                                        ((INSTANCE) == DMA1_Channel2) || \
11078                                        ((INSTANCE) == DMA1_Channel3) || \
11079                                        ((INSTANCE) == DMA1_Channel4) || \
11080                                        ((INSTANCE) == DMA1_Channel5) || \
11081                                        ((INSTANCE) == DMA1_Channel6) || \
11082                                        ((INSTANCE) == DMA1_Channel7) || \
11083                                        ((INSTANCE) == DMA2_Channel1) || \
11084                                        ((INSTANCE) == DMA2_Channel2) || \
11085                                        ((INSTANCE) == DMA2_Channel3) || \
11086                                        ((INSTANCE) == DMA2_Channel4) || \
11087                                        ((INSTANCE) == DMA2_Channel5))
11088 
11089 /****************************** DMA STREAM Instances ***************************/
11090 #define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \
11091                                           ((INSTANCE) == DMA1_Stream1)   || \
11092                                           ((INSTANCE) == DMA1_Stream2)   || \
11093                                           ((INSTANCE) == DMA1_Stream3)   || \
11094                                           ((INSTANCE) == DMA1_Stream4)   || \
11095                                           ((INSTANCE) == DMA1_Stream5)   || \
11096                                           ((INSTANCE) == DMA1_Stream6)   || \
11097                                           ((INSTANCE) == DMA1_Stream7)   || \
11098                                           ((INSTANCE) == DMA2_Stream0)   || \
11099                                           ((INSTANCE) == DMA2_Stream1)   || \
11100                                           ((INSTANCE) == DMA2_Stream2)   || \
11101                                           ((INSTANCE) == DMA2_Stream3)   || \
11102                                           ((INSTANCE) == DMA2_Stream4)   || \
11103                                           ((INSTANCE) == DMA2_Stream5)   || \
11104                                           ((INSTANCE) == DMA2_Stream6)   || \
11105                                           ((INSTANCE) == DMA2_Stream7))
11106 
11107 /******************************** DMAMUX Instances ****************************/
11108 #define IS_DMAMUX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMAMUX1)
11109 
11110 #define IS_DMAMUX_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX_RequestGenerator0) || \
11111                                                       ((INSTANCE) == DMAMUX_RequestGenerator1) || \
11112                                                       ((INSTANCE) == DMAMUX_RequestGenerator2) || \
11113                                                       ((INSTANCE) == DMAMUX_RequestGenerator3))
11114 
11115 /******************************* GPIO Instances *******************************/
11116 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
11117                                         ((INSTANCE) == GPIOB) || \
11118                                         ((INSTANCE) == GPIOC) || \
11119                                         ((INSTANCE) == GPIOD) || \
11120                                         ((INSTANCE) == GPIOE) || \
11121                                         ((INSTANCE) == GPIOF))
11122 /******************************* GPIO AF Instances ****************************/
11123 #define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
11124 
11125 /**************************** GPIO Lock Instances *****************************/
11126 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
11127 
11128 /******************************** I2C Instances *******************************/
11129 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
11130                                        ((INSTANCE) == I2C2) || \
11131                                        ((INSTANCE) == I2C3) || \
11132                                        ((INSTANCE) == I2C4))
11133 /************** I2C Instances : wakeup capability from stop modes *************/
11134 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
11135                                                    ((INSTANCE) == I2C3))
11136 
11137 /****************************** LTDC Instances ********************************/
11138 #define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)
11139 
11140 /******************************* RNG Instances ********************************/
11141 #define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
11142 
11143 /****************************** RTC Instances *********************************/
11144 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
11145 
11146 
11147 /******************************** SMBUS Instances *****************************/
11148 #define IS_SMBUS_INSTANCE(INSTANCE)  (((INSTANCE) == I2C1)  || \
11149                                       ((INSTANCE) == I2C3))
11150 
11151 /******************************** SPI Instances *******************************/
11152 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
11153                                        ((INSTANCE) == SPI2) || \
11154                                        ((INSTANCE) == SPI3))
11155 
11156 /****************** LPTIM Instances : All supported instances *****************/
11157 #define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) ||\
11158                                          ((INSTANCE) == LPTIM2) ||\
11159                                          ((INSTANCE) == LPTIM3))
11160 
11161 /****************** LPTIM Instances : DMA supported instances *****************/
11162 #define IS_LPTIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) ||\
11163                                              ((INSTANCE) == LPTIM2) ||\
11164                                              ((INSTANCE) == LPTIM3))
11165 
11166 /************* LPTIM Instances : at least 1 capture/compare channel ***********/
11167 #define IS_LPTIM_CC1_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) ||\
11168                                              ((INSTANCE) == LPTIM2) ||\
11169                                              ((INSTANCE) == LPTIM3))
11170 
11171 
11172 /************* LPTIM Instances : at least 2 capture/compare channel ***********/
11173 #define IS_LPTIM_CC2_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) ||\
11174                                              ((INSTANCE) == LPTIM2) ||\
11175                                              ((INSTANCE) == LPTIM3))
11176 
11177 /************* LPTIM Instances : at least 3 capture/compare channel ***********/
11178 #define IS_LPTIM_CC3_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) ||\
11179                                              ((INSTANCE) == LPTIM3))
11180 
11181 
11182 /************* LPTIM Instances : at least 4 capture/compare channel ***********/
11183 #define IS_LPTIM_CC4_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) ||\
11184                                              ((INSTANCE) == LPTIM3))
11185 
11186 /****************** LPTIM Instances : supporting encoder interface **************/
11187 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)    (((INSTANCE) == LPTIM1) ||\
11188                                                           ((INSTANCE) == LPTIM3))
11189 
11190 /****************** LPTIM Instances : supporting Input Capture **************/
11191 #define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE)    (((INSTANCE) == LPTIM1) ||\
11192                                                       ((INSTANCE) == LPTIM2) ||\
11193                                                       ((INSTANCE) == LPTIM3))
11194 
11195 /****************** TIM Instances : All supported instances *******************/
11196 #define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
11197                                          ((INSTANCE) == TIM2)   || \
11198                                          ((INSTANCE) == TIM3)   || \
11199                                          ((INSTANCE) == TIM6)   || \
11200                                          ((INSTANCE) == TIM7)   || \
11201                                          ((INSTANCE) == TIM15)  || \
11202                                          ((INSTANCE) == TIM16))
11203 
11204 /****************** TIM Instances : supporting 32 bits counter ****************/
11205 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
11206 
11207 /****************** TIM Instances : supporting the break function *************/
11208 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
11209                                             ((INSTANCE) == TIM15)   || \
11210                                             ((INSTANCE) == TIM16))
11211 
11212 /************** TIM Instances : supporting Break source selection *************/
11213 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
11214                                                ((INSTANCE) == TIM15)  || \
11215                                                ((INSTANCE) == TIM16))
11216 
11217 /****************** TIM Instances : supporting 2 break inputs *****************/
11218 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
11219 
11220 /************* TIM Instances : at least 1 capture/compare channel *************/
11221 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
11222                                          ((INSTANCE) == TIM2)   || \
11223                                          ((INSTANCE) == TIM3)   || \
11224                                          ((INSTANCE) == TIM15)  || \
11225                                          ((INSTANCE) == TIM16))
11226 
11227 /************ TIM Instances : at least 2 capture/compare channels *************/
11228 #define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
11229                                          ((INSTANCE) == TIM2)   || \
11230                                          ((INSTANCE) == TIM3)   || \
11231                                          ((INSTANCE) == TIM15))
11232 
11233 /************ TIM Instances : at least 3 capture/compare channels *************/
11234 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
11235                                          ((INSTANCE) == TIM2)   || \
11236                                          ((INSTANCE) == TIM3))
11237 
11238 /************ TIM Instances : at least 4 capture/compare channels *************/
11239 #define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
11240                                          ((INSTANCE) == TIM2)   || \
11241                                          ((INSTANCE) == TIM3))
11242 
11243 /****************** TIM Instances : at least 5 capture/compare channels *******/
11244 #define IS_TIM_CC5_INSTANCE(INSTANCE)   ((INSTANCE) == TIM1)
11245 
11246 /****************** TIM Instances : at least 6 capture/compare channels *******/
11247 #define IS_TIM_CC6_INSTANCE(INSTANCE)   ((INSTANCE) == TIM1)
11248 
11249 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
11250 #define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
11251                                             ((INSTANCE) == TIM15)  || \
11252                                             ((INSTANCE) == TIM16))
11253 
11254 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
11255 #define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
11256                                             ((INSTANCE) == TIM2)   || \
11257                                             ((INSTANCE) == TIM3)   || \
11258                                             ((INSTANCE) == TIM6)   || \
11259                                             ((INSTANCE) == TIM7)   || \
11260                                             ((INSTANCE) == TIM15)  || \
11261                                             ((INSTANCE) == TIM16))
11262 
11263 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
11264 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
11265                                             ((INSTANCE) == TIM2)   || \
11266                                             ((INSTANCE) == TIM3)   || \
11267                                             ((INSTANCE) == TIM15)  || \
11268                                             ((INSTANCE) == TIM16))
11269 
11270 /******************** TIM Instances : DMA burst feature ***********************/
11271 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
11272                                             ((INSTANCE) == TIM2)   || \
11273                                             ((INSTANCE) == TIM3)   || \
11274                                             ((INSTANCE) == TIM15)  || \
11275                                             ((INSTANCE) == TIM16))
11276 
11277 /******************* TIM Instances : output(s) available **********************/
11278 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
11279     ((((INSTANCE) == TIM1) &&                  \
11280      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11281       ((CHANNEL) == TIM_CHANNEL_2) ||          \
11282       ((CHANNEL) == TIM_CHANNEL_3) ||          \
11283       ((CHANNEL) == TIM_CHANNEL_4) ||          \
11284       ((CHANNEL) == TIM_CHANNEL_5) ||          \
11285       ((CHANNEL) == TIM_CHANNEL_6)))           \
11286      ||                                        \
11287      (((INSTANCE) == TIM2) &&                  \
11288      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11289       ((CHANNEL) == TIM_CHANNEL_2) ||          \
11290       ((CHANNEL) == TIM_CHANNEL_3) ||          \
11291       ((CHANNEL) == TIM_CHANNEL_4)))           \
11292      ||                                        \
11293      (((INSTANCE) == TIM3) &&                  \
11294      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11295       ((CHANNEL) == TIM_CHANNEL_2) ||          \
11296       ((CHANNEL) == TIM_CHANNEL_3) ||          \
11297       ((CHANNEL) == TIM_CHANNEL_4)))           \
11298      ||                                        \
11299      (((INSTANCE) == TIM15) &&                 \
11300      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11301       ((CHANNEL) == TIM_CHANNEL_2)))           \
11302      ||                                        \
11303      (((INSTANCE) == TIM16) &&                 \
11304      (((CHANNEL) == TIM_CHANNEL_1))))
11305 
11306 /****************** TIM Instances : supporting complementary output(s) ********/
11307 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
11308    ((((INSTANCE) == TIM1) &&                    \
11309      (((CHANNEL) == TIM_CHANNEL_1) ||           \
11310       ((CHANNEL) == TIM_CHANNEL_2) ||           \
11311       ((CHANNEL) == TIM_CHANNEL_3)))            \
11312     ||                                          \
11313     (((INSTANCE) == TIM15) &&                   \
11314      ((CHANNEL) == TIM_CHANNEL_1))              \
11315     ||                                          \
11316     (((INSTANCE) == TIM16) &&                   \
11317      ((CHANNEL) == TIM_CHANNEL_1)))
11318 
11319 /****************** TIM Instances : supporting clock division *****************/
11320 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
11321                                                     ((INSTANCE) == TIM2)    || \
11322                                                     ((INSTANCE) == TIM3)    || \
11323                                                     ((INSTANCE) == TIM15)   || \
11324                                                     ((INSTANCE) == TIM16))
11325 
11326 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
11327 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
11328                                                         ((INSTANCE) == TIM2) || \
11329                                                         ((INSTANCE) == TIM3))
11330 
11331 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
11332 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
11333                                                         ((INSTANCE) == TIM2) || \
11334                                                         ((INSTANCE) == TIM3))
11335 
11336 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
11337 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
11338                                                         ((INSTANCE) == TIM2) || \
11339                                                         ((INSTANCE) == TIM3) || \
11340                                                         ((INSTANCE) == TIM15))
11341 
11342 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
11343 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
11344                                                         ((INSTANCE) == TIM2) || \
11345                                                         ((INSTANCE) == TIM3) || \
11346                                                         ((INSTANCE) == TIM15))
11347 
11348 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
11349 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
11350 
11351 /****************** TIM Instances : supporting commutation event generation ***/
11352 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
11353                                                      ((INSTANCE) == TIM15)  || \
11354                                                      ((INSTANCE) == TIM16))
11355 
11356 /****************** TIM Instances : supporting counting mode selection ********/
11357 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
11358                                                         ((INSTANCE) == TIM2) || \
11359                                                         ((INSTANCE) == TIM3))
11360 
11361 /****************** TIM Instances : supporting encoder interface **************/
11362 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
11363                                                       ((INSTANCE) == TIM2)  || \
11364                                                       ((INSTANCE) == TIM3))
11365 
11366 /****************** TIM Instances : supporting Hall sensor interface **********/
11367 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
11368                                                          ((INSTANCE) == TIM2)   || \
11369                                                          ((INSTANCE) == TIM3))
11370 
11371 /**************** TIM Instances : external trigger input available ************/
11372 #define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
11373                                             ((INSTANCE) == TIM2)  || \
11374                                             ((INSTANCE) == TIM3))
11375 
11376 /************* TIM Instances : supporting ETR source selection ***************/
11377 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
11378                                              ((INSTANCE) == TIM2)  || \
11379                                              ((INSTANCE) == TIM3))
11380 
11381 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
11382 #define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
11383                                             ((INSTANCE) == TIM2)  || \
11384                                             ((INSTANCE) == TIM3)  || \
11385                                             ((INSTANCE) == TIM6)  || \
11386                                             ((INSTANCE) == TIM7)  || \
11387                                             ((INSTANCE) == TIM15))
11388 
11389 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
11390 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
11391                                             ((INSTANCE) == TIM2)  || \
11392                                             ((INSTANCE) == TIM3)  || \
11393                                             ((INSTANCE) == TIM15))
11394 
11395 /****************** TIM Instances : supporting OCxREF clear *******************/
11396 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
11397                                                        ((INSTANCE) == TIM2) || \
11398                                                        ((INSTANCE) == TIM3))
11399 
11400 /******** TIM Instances : supporting bitfield OCCS in SMCR register ***********/
11401 #define IS_TIM_OCCS_INSTANCE(INSTANCE)                (((INSTANCE) == TIM1)  || \
11402                                                        ((INSTANCE) == TIM2)  || \
11403                                                        ((INSTANCE) == TIM3))
11404 
11405 /****************** TIM Instances : remapping capability **********************/
11406 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
11407                                             ((INSTANCE) == TIM2)  || \
11408                                             ((INSTANCE) == TIM3))
11409 
11410 /****************** TIM Instances : supporting repetition counter *************/
11411 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
11412                                                        ((INSTANCE) == TIM15) || \
11413                                                        ((INSTANCE) == TIM16))
11414 
11415 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
11416 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1))
11417 
11418 /******************* TIM Instances : Timer input XOR function *****************/
11419 #define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
11420                                             ((INSTANCE) == TIM2)   || \
11421                                             ((INSTANCE) == TIM3)   || \
11422                                             ((INSTANCE) == TIM15))
11423 
11424 /******************* TIM Instances : Timer input selection ********************/
11425 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
11426                                          ((INSTANCE) == TIM2)   || \
11427                                          ((INSTANCE) == TIM3)   || \
11428                                          ((INSTANCE) == TIM15)  || \
11429                                          ((INSTANCE) == TIM16))
11430 
11431 /************ TIM Instances : Advanced timers  ********************************/
11432 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1))
11433 
11434 /****************************** TSC Instances *********************************/
11435 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
11436 
11437 /******************** USART Instances : Synchronous mode **********************/
11438 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11439                                      ((INSTANCE) == USART2) || \
11440                                      ((INSTANCE) == USART3) || \
11441                                      ((INSTANCE) == USART4))
11442 
11443 
11444 /******************** USART Instances : SPI slave mode ************************/
11445 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11446                                               ((INSTANCE) == USART2) || \
11447                                               ((INSTANCE) == USART3) || \
11448                                               ((INSTANCE) == USART4))
11449 
11450 /******************** UART Instances : Asynchronous mode **********************/
11451 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1)  || \
11452                                     ((INSTANCE) == USART2)  || \
11453                                     ((INSTANCE) == USART3)  || \
11454                                     ((INSTANCE) == USART4))
11455 
11456 /******************** UART Instances : FIFO mode.******************************/
11457 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1)  || \
11458                                          ((INSTANCE) == USART2)  || \
11459                                          ((INSTANCE) == LPUART1) || \
11460                                          ((INSTANCE) == LPUART2) || \
11461                                          ((INSTANCE) == LPUART3))
11462 
11463 /****************** UART Instances : Auto Baud Rate detection *****************/
11464 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11465                                                             ((INSTANCE) == USART2))
11466 
11467 /*********************** UART Instances : Driver Enable ***********************/
11468 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1)  || \
11469                                                   ((INSTANCE) == USART2)  || \
11470                                                   ((INSTANCE) == USART3)  || \
11471                                                   ((INSTANCE) == USART4)  || \
11472                                                   ((INSTANCE) == LPUART1) || \
11473                                                   ((INSTANCE) == LPUART2) || \
11474                                                   ((INSTANCE) == LPUART3))
11475 
11476 /********************* UART Instances : Half-Duplex mode **********************/
11477 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1)  || \
11478                                                ((INSTANCE) == USART2)  || \
11479                                                ((INSTANCE) == USART3)  || \
11480                                                ((INSTANCE) == USART4)  || \
11481                                                ((INSTANCE) == LPUART1) || \
11482                                                ((INSTANCE) == LPUART2) || \
11483                                                ((INSTANCE) == LPUART3))
11484 
11485 /******************* UART Instances : Hardware Flow control *******************/
11486 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1)  || \
11487                                            ((INSTANCE) == USART2)  || \
11488                                            ((INSTANCE) == USART3)  || \
11489                                            ((INSTANCE) == USART4)  || \
11490                                            ((INSTANCE) == LPUART1) || \
11491                                            ((INSTANCE) == LPUART2) || \
11492                                            ((INSTANCE) == LPUART3))
11493 
11494 /******************** UART Instances : Wake-up from Stop mode **********************/
11495 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
11496                                                       ((INSTANCE) == USART2) || \
11497                                                       ((INSTANCE) == LPUART1)|| \
11498                                                       ((INSTANCE) == LPUART2)|| \
11499                                                       ((INSTANCE) == LPUART3))
11500 
11501 /************************* UART Instances : LIN mode **************************/
11502 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11503                                         ((INSTANCE) == USART2))
11504 
11505 /************************* UART Instances : IRDA mode *************************/
11506 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11507                                     ((INSTANCE) == USART2))
11508 
11509 /********************* USART Instances : Smard card mode **********************/
11510 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11511                                          ((INSTANCE) == USART2))
11512 
11513 /****************************** LPUART Instance *******************************/
11514 #define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1) || \
11515                                       ((INSTANCE) == LPUART2) || \
11516                                       ((INSTANCE) == LPUART3))
11517 
11518 /****************************** IWDG Instances ********************************/
11519 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
11520 
11521 /******************************* USB DRD FS PCD Instances *************************/
11522 #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_DRD_FS)
11523 
11524 /****************************** WWDG Instances ********************************/
11525 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
11526 
11527 /****************************** OPAMP Instances *******************************/
11528 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP1)
11529 
11530 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP_COMMON)
11531 
11532 /****************** LCD Instances : All supported instances *****************/
11533 #define IS_LCD_ALL_INSTANCE(INSTANCE)    ((INSTANCE) == LCD)
11534 
11535 /******************************************************************************/
11536 
11537 
11538 
11539 /**
11540   * @}
11541   */
11542 
11543 /**
11544   * @}
11545   */
11546 
11547 #ifdef __cplusplus
11548 }
11549 #endif /* __cplusplus */
11550 
11551 #endif /* STM32U083xx_H */
11552 /**
11553   * @}
11554   */
11555